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[/] [adv_debug_sys/] [trunk/] [Hardware/] [adv_dbg_if/] [rtl/] [verilog/] [syncflop.v] - Blame information for rev 42

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1 42 nyawn
//////////////////////////////////////////////////////////////////////
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////                                                              ////
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////  syncflop.v                                                  ////
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////                                                              ////
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////                                                              ////
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////  A generic synchronization device between two clock domains  ////
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////                                                              ////
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////  Author(s):                                                  ////
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////       Nathan Yawn (nathan.yawn@opencores.org)                ////
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////                                                              ////
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////                                                              ////
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////                                                              ////
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//////////////////////////////////////////////////////////////////////
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////                                                              ////
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//// Copyright (C) 2010 Authors                                   ////
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////                                                              ////
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//// This source file may be used and distributed without         ////
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//// restriction provided that this copyright statement is not    ////
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//// removed from the file and that any derivative work contains  ////
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//// the original copyright notice and the associated disclaimer. ////
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////                                                              ////
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//// This source file is free software; you can redistribute it   ////
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//// and/or modify it under the terms of the GNU Lesser General   ////
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//// Public License as published by the Free Software Foundation; ////
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//// either version 2.1 of the License, or (at your option) any   ////
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//// later version.                                               ////
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////                                                              ////
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//// This source is distributed in the hope that it will be       ////
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//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
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//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
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//// PURPOSE.  See the GNU Lesser General Public License for more ////
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//// details.                                                     ////
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////                                                              ////
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//// You should have received a copy of the GNU Lesser General    ////
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//// Public License along with this source; if not, download it   ////
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//// from http://www.opencores.org/lgpl.shtml                     ////
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////                                                              ////
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//////////////////////////////////////////////////////////////////////
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//
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// This is a synchronization element between two clock domains. It
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// uses toggle signaling - that is, clock domain 1 changes the state
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// of TOGGLE_IN to indicate a change, rather than setting the level
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// high.  When TOGGLE_IN changes state, the output on D_OUT will be
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// set to level '1', and will hold that value until D_RST is held
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// high during a rising edge of DEST_CLK.  D_OUT will be updated
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// on the second rising edge of DEST_CLK after the state of
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// TOGGLE_IN has changed.
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// RESET is asynchronous.  This is necessary to coordinate the reset
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// between different clock domains with potentially different reset
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// signals.
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//
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// Ports:
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// DEST_CLK:  Clock for the target clock domain
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// D_SET:     Synchronously set the output to '1'
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// D_CLR:     Synchronously reset the output to '0'
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// RESET:     Set all FF's to '0' (asynchronous)
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// TOGGLE_IN: Toggle data signal from source clock domain
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// D_OUT:     Output to clock domain 2
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// Top module
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module syncflop(
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                DEST_CLK,
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                D_SET,
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                D_RST,
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                RESET,
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                TOGGLE_IN,
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                D_OUT
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                );
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   input   DEST_CLK;
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   input   D_SET;
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   input   D_RST;
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   input   RESET;
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   input   TOGGLE_IN;
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   output  D_OUT;
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   reg     sync1;
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   reg     sync2;
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   reg     syncprev;
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   reg     srflop;
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   wire    syncxor;
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   wire    srinput;
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   wire    D_OUT;
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   // Combinatorial assignments
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   assign  syncxor = sync2 ^ syncprev;
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   assign  srinput = syncxor | D_SET;
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   assign  D_OUT = srflop | syncxor;
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   // First DFF (always enabled)
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   always @ (posedge DEST_CLK or posedge RESET)
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     begin
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        if(RESET) sync1 <= 1'b0;
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        else sync1 <= TOGGLE_IN;
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     end
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   // Second DFF (always enabled)
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   always @ (posedge DEST_CLK or posedge RESET)
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     begin
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        if(RESET) sync2 <= 1'b0;
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        else sync2 <= sync1;
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     end
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   // Third DFF (always enabled, used to detect toggles)
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   always @ (posedge DEST_CLK or posedge RESET)
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     begin
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        if(RESET) syncprev <= 1'b0;
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        else syncprev <= sync2;
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     end
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   // Set/Reset FF (holds detected toggles)
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   always @ (posedge DEST_CLK or posedge RESET)
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     begin
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        if(RESET)         srflop <= 1'b0;
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        else if(D_RST)    srflop <= 1'b0;
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        else if (srinput) srflop <= 1'b1;
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     end
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endmodule

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