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[/] [adv_debug_sys/] [trunk/] [Hardware/] [jtag/] [tap/] [rtl/] [verilog/] [tap_top.v] - Blame information for rev 14

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//////////////////////////////////////////////////////////////////////
////                                                              ////
////  tap_top.v                                                   ////
////                                                              ////
////                                                              ////
////  This file is part of the JTAG Test Access Port (TAP)        ////
////                                                              ////
////  Author(s):                                                  ////
////       Igor Mohor (igorm@opencores.org)                       ////
////       Nathan Yawn (nathan.yawn@opencores.org)                ////
////                                                              ////
////                                                              ////
////  All additional information is avaliable in the jtag.pdf     ////
////  file.                                                       ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
////                                                              ////
//// Copyright (C) 2000 - 2008 Authors                            ////
////                                                              ////
//// This source file may be used and distributed without         ////
//// restriction provided that this copyright statement is not    ////
//// removed from the file and that any derivative work contains  ////
//// the original copyright notice and the associated disclaimer. ////
////                                                              ////
//// This source file is free software; you can redistribute it   ////
//// and/or modify it under the terms of the GNU Lesser General   ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any   ////
//// later version.                                               ////
////                                                              ////
//// This source is distributed in the hope that it will be       ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
//// PURPOSE.  See the GNU Lesser General Public License for more ////
//// details.                                                     ////
////                                                              ////
//// You should have received a copy of the GNU Lesser General    ////
//// Public License along with this source; if not, download it   ////
//// from http://www.opencores.org/lgpl.shtml                     ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: tap_top.v,v $
// Revision 1.5  2009/06/16 02:53:58  Nathan
// Changed some signal names for better consistency between different hardware modules. Removed stale CVS log/comments.
//
// Revision 1.4  2009/05/17 20:54:38  Nathan
// Changed email address to opencores.org
//
// Revision 1.3  2008/06/18 18:45:07  Nathan
// Improved reset slightly.  Cleanup.
//
//
// Revision 1.2 2008/05/14 13:13:24 Nathan
// Rewrote TAP FSM in canonical form, for readability.  Switched
// from one-hot to binary encoding.  Made reset signal active-
// low, per JTAG spec.  Removed FF chain for 5 TMS reset - reset
// done in Test Logic Reset mode.  Added test_logic_reset_o and
// run_test_idle_o signals.  Removed double registers from IR data
// path.  Unified the registers at the output of each data register
// to a single shared FF.
//
 
`include "tap_defines.v"
 
// Top module
module tap_top(
                // JTAG pads
                tms_pad_i,
                tck_pad_i,
                trstn_pad_i,
                tdi_pad_i,
                tdo_pad_o,
                tdo_padoe_o,
 
                // TAP states
                                test_logic_reset_o,
                                run_test_idle_o,
                shift_dr_o,
                pause_dr_o,
                update_dr_o,
                capture_dr_o,
 
                // Select signals for boundary scan or mbist
                extest_select_o,
                sample_preload_select_o,
                mbist_select_o,
                debug_select_o,
 
                // TDO signal that is connected to TDI of sub-modules.
                tdi_o,
 
                // TDI signals from sub-modules
                debug_tdo_i,    // from debug module
                bs_chain_tdo_i, // from Boundary Scan Chain
                mbist_tdo_i     // from Mbist Chain
              );
 
 
// JTAG pins
input   tms_pad_i;      // JTAG test mode select pad
input   tck_pad_i;      // JTAG test clock pad
input   trstn_pad_i;     // JTAG test reset pad
input   tdi_pad_i;      // JTAG test data input pad
output  tdo_pad_o;      // JTAG test data output pad
output  tdo_padoe_o;    // Output enable for JTAG test data output pad 
 
// TAP states
output  test_logic_reset_o;
output  run_test_idle_o;
output  shift_dr_o;
output  pause_dr_o;
output  update_dr_o;
output  capture_dr_o;
 
// Select signals for boundary scan or mbist
output  extest_select_o;
output  sample_preload_select_o;
output  mbist_select_o;
output  debug_select_o;
 
// TDO signal that is connected to TDI of sub-modules.
output  tdi_o;
 
// TDI signals from sub-modules
input   debug_tdo_i;    // from debug module
input   bs_chain_tdo_i; // from Boundary Scan Chain
input   mbist_tdo_i;    // from Mbist Chain
 
// Wires which depend on the state of the TAP FSM
reg     test_logic_reset;
reg     run_test_idle;
reg     select_dr_scan;
reg     capture_dr;
reg     shift_dr;
reg     exit1_dr;
reg     pause_dr;
reg     exit2_dr;
reg     update_dr;
reg     select_ir_scan;
reg     capture_ir;
reg     shift_ir;
reg     exit1_ir;
reg     pause_ir;
reg     exit2_ir;
reg     update_ir;
 
// Wires which depend on the current value in the IR
reg     extest_select;
reg     sample_preload_select;
reg     idcode_select;
reg     mbist_select;
reg     debug_select;
reg     bypass_select;
 
// TDO and enable
reg     tdo_pad_o;
reg     tdo_padoe_o;
 
assign tdi_o = tdi_pad_i;
 
assign test_logic_reset_o = test_logic_reset;
assign run_test_idle_o = run_test_idle;
assign shift_dr_o = shift_dr;
assign pause_dr_o = pause_dr;
assign update_dr_o = update_dr;
assign capture_dr_o = capture_dr;
 
assign extest_select_o = extest_select;
assign sample_preload_select_o = sample_preload_select;
assign mbist_select_o = mbist_select;
assign debug_select_o = debug_select;
 
 
/**********************************************************************************
*                                                                                 *
*   TAP State Machine: Fully JTAG compliant                                       *
*                                                                                 *
**********************************************************************************/
// Definition of machine state values.  We could one-hot encode this, and use 16
// registers, but this uses binary encoding for the minimum of 4 DFF's instead.
`define STATE_test_logic_reset 4'hF
`define STATE_run_test_idle    4'hC
`define STATE_select_dr_scan   4'h7
`define STATE_capture_dr       4'h6
`define STATE_shift_dr         4'h2
`define STATE_exit1_dr         4'h1
`define STATE_pause_dr         4'h3
`define STATE_exit2_dr         4'h0
`define STATE_update_dr        4'h5
`define STATE_select_ir_scan   4'h4
`define STATE_capture_ir       4'hE
`define STATE_shift_ir         4'hA
`define STATE_exit1_ir         4'h9
`define STATE_pause_ir         4'hB
`define STATE_exit2_ir         4'h8
`define STATE_update_ir        4'hD
 
reg [3:0] TAP_state = `STATE_test_logic_reset;  // current state of the TAP controller
reg [3:0] next_TAP_state;  // state TAP will take at next rising TCK, combinational signal
 
// sequential part of the FSM
always @ (posedge tck_pad_i or negedge trstn_pad_i)
begin
        if(trstn_pad_i == 0)
                TAP_state = `STATE_test_logic_reset;
        else
                TAP_state = next_TAP_state;
end
 
 
// Determination of next state; purely combinatorial
always @ (TAP_state or tms_pad_i)
begin
        case(TAP_state)
                `STATE_test_logic_reset:
                        begin
                        if(tms_pad_i) next_TAP_state = `STATE_test_logic_reset;
                        else next_TAP_state = `STATE_run_test_idle;
                        end
                `STATE_run_test_idle:
                        begin
                        if(tms_pad_i) next_TAP_state = `STATE_select_dr_scan;
                        else next_TAP_state = `STATE_run_test_idle;
                        end
                `STATE_select_dr_scan:
                        begin
                        if(tms_pad_i) next_TAP_state = `STATE_select_ir_scan;
                        else next_TAP_state = `STATE_capture_dr;
                        end
                `STATE_capture_dr:
                        begin
                        if(tms_pad_i) next_TAP_state = `STATE_exit1_dr;
                        else next_TAP_state = `STATE_shift_dr;
                        end
                `STATE_shift_dr:
                        begin
                        if(tms_pad_i) next_TAP_state = `STATE_exit1_dr;
                        else next_TAP_state = `STATE_shift_dr;
                        end
                `STATE_exit1_dr:
                        begin
                        if(tms_pad_i) next_TAP_state = `STATE_update_dr;
                        else next_TAP_state = `STATE_pause_dr;
                        end
                `STATE_pause_dr:
                        begin
                        if(tms_pad_i) next_TAP_state = `STATE_exit2_dr;
                        else next_TAP_state = `STATE_pause_dr;
                        end
                `STATE_exit2_dr:
                        begin
                        if(tms_pad_i) next_TAP_state = `STATE_update_dr;
                        else next_TAP_state = `STATE_shift_dr;
                        end
                `STATE_update_dr:
                        begin
                        if(tms_pad_i) next_TAP_state = `STATE_select_dr_scan;
                        else next_TAP_state = `STATE_run_test_idle;
                        end
                `STATE_select_ir_scan:
                        begin
                        if(tms_pad_i) next_TAP_state = `STATE_test_logic_reset;
                        else next_TAP_state = `STATE_capture_ir;
                        end
                `STATE_capture_ir:
                        begin
                        if(tms_pad_i) next_TAP_state = `STATE_exit1_ir;
                        else next_TAP_state = `STATE_shift_ir;
                        end
                `STATE_shift_ir:
                        begin
                        if(tms_pad_i) next_TAP_state = `STATE_exit1_ir;
                        else next_TAP_state = `STATE_shift_ir;
                        end
                `STATE_exit1_ir:
                        begin
                        if(tms_pad_i) next_TAP_state = `STATE_update_ir;
                        else next_TAP_state = `STATE_pause_ir;
                        end
                `STATE_pause_ir:
                        begin
                        if(tms_pad_i) next_TAP_state = `STATE_exit2_ir;
                        else next_TAP_state = `STATE_pause_ir;
                        end
                `STATE_exit2_ir:
                        begin
                        if(tms_pad_i) next_TAP_state = `STATE_update_ir;
                        else next_TAP_state = `STATE_shift_ir;
                        end
                `STATE_update_ir:
                        begin
                        if(tms_pad_i) next_TAP_state = `STATE_select_dr_scan;
                        else next_TAP_state = `STATE_run_test_idle;
                        end
                default: next_TAP_state = `STATE_test_logic_reset;  // can't actually happen
        endcase
end
 
 
// Outputs of state machine, pure combinatorial
always @ (TAP_state)
begin
        // Default everything to 0, keeps the case statement simple
        test_logic_reset = 1'b0;
        run_test_idle = 1'b0;
        select_dr_scan = 1'b0;
        capture_dr = 1'b0;
        shift_dr = 1'b0;
        exit1_dr = 1'b0;
        pause_dr = 1'b0;
        exit2_dr = 1'b0;
        update_dr = 1'b0;
        select_ir_scan = 1'b0;
        capture_ir = 1'b0;
        shift_ir = 1'b0;
        exit1_ir = 1'b0;
        pause_ir = 1'b0;
        exit2_ir = 1'b0;
        update_ir = 1'b0;
 
        case(TAP_state)
                `STATE_test_logic_reset: test_logic_reset = 1'b1;
                `STATE_run_test_idle:    run_test_idle = 1'b1;
                `STATE_select_dr_scan:   select_dr_scan = 1'b1;
                `STATE_capture_dr:       capture_dr = 1'b1;
                `STATE_shift_dr:         shift_dr = 1'b1;
                `STATE_exit1_dr:         exit1_dr = 1'b1;
                `STATE_pause_dr:         pause_dr = 1'b1;
                `STATE_exit2_dr:         exit2_dr = 1'b1;
                `STATE_update_dr:        update_dr = 1'b1;
                `STATE_select_ir_scan:   select_ir_scan = 1'b1;
                `STATE_capture_ir:       capture_ir = 1'b1;
                `STATE_shift_ir:         shift_ir = 1'b1;
                `STATE_exit1_ir:         exit1_ir = 1'b1;
                `STATE_pause_ir:         pause_ir = 1'b1;
                `STATE_exit2_ir:         exit2_ir = 1'b1;
                `STATE_update_ir:        update_ir = 1'b1;
                default: ;
        endcase
end
 
/**********************************************************************************
*                                                                                 *
*   End: TAP State Machine                                                        *
*                                                                                 *
**********************************************************************************/
 
 
 
/**********************************************************************************
*                                                                                 *
*   jtag_ir:  JTAG Instruction Register                                           *
*                                                                                 *
**********************************************************************************/
reg [`IR_LENGTH-1:0]  jtag_ir;          // Instruction register
reg [`IR_LENGTH-1:0]  latched_jtag_ir; //, latched_jtag_ir_neg;
wire                  instruction_tdo;
 
always @ (posedge tck_pad_i or negedge trstn_pad_i)
begin
  if(trstn_pad_i == 0)
    jtag_ir[`IR_LENGTH-1:0] <= #1 `IR_LENGTH'b0;
  else if (test_logic_reset == 1)
        jtag_ir[`IR_LENGTH-1:0] <= #1 `IR_LENGTH'b0;
  else if(capture_ir)
    jtag_ir <= #1 4'b0101;          // This value is fixed for easier fault detection
  else if(shift_ir)
    jtag_ir[`IR_LENGTH-1:0] <= #1 {tdi_pad_i, jtag_ir[`IR_LENGTH-1:1]};
end
 
assign instruction_tdo = jtag_ir[0];  // This is latched on a negative TCK edge after the output MUX
 
// Updating jtag_ir (Instruction Register)
// jtag_ir should be latched on FALLING EDGE of TCK when capture_ir == 1
always @ (negedge tck_pad_i or negedge trstn_pad_i)
begin
  if(trstn_pad_i == 0)
    latched_jtag_ir <=#1 `IDCODE;   // IDCODE selected after reset
  else if (test_logic_reset)
    latched_jtag_ir <=#1 `IDCODE;   // IDCODE selected after reset
  else if(update_ir)
    latched_jtag_ir <=#1 jtag_ir;
end
 
/**********************************************************************************
*                                                                                 *
*   End: jtag_ir                                                                  *
*                                                                                 *
**********************************************************************************/
 
 
 
/**********************************************************************************
*                                                                                 *
*   idcode logic                                                                  *
*                                                                                 *
**********************************************************************************/
reg [31:0] idcode_reg;
wire        idcode_tdo;
 
always @ (posedge tck_pad_i or negedge trstn_pad_i)
begin
  if(trstn_pad_i == 0)
    idcode_reg <=#1 `IDCODE_VALUE;   // IDCODE selected after reset
  else if (test_logic_reset)
    idcode_reg <=#1 `IDCODE_VALUE;   // IDCODE selected after reset
  else if(idcode_select & capture_dr)
    idcode_reg <= #1 `IDCODE_VALUE;
  else if(idcode_select & shift_dr)
    idcode_reg <= #1 {tdi_pad_i, idcode_reg[31:1]};
 
end
 
assign idcode_tdo = idcode_reg[0];   // This is latched on a negative TCK edge after the output MUX
 
/**********************************************************************************
*                                                                                 *
*   End: idcode logic                                                             *
*                                                                                 *
**********************************************************************************/
 
 
/**********************************************************************************
*                                                                                 *
*   Bypass logic                                                                  *
*                                                                                 *
**********************************************************************************/
wire  bypassed_tdo;
reg   bypass_reg;  // This is a 1-bit register
 
always @ (posedge tck_pad_i or negedge trstn_pad_i)
begin
  if (trstn_pad_i == 0)
     bypass_reg <= #1 1'b0;
  else if (test_logic_reset == 1)
     bypass_reg <= #1 1'b0;
  else if (bypass_select & capture_dr)
    bypass_reg<=#1 1'b0;
  else if(bypass_select & shift_dr)
    bypass_reg<=#1 tdi_pad_i;
end
 
assign bypassed_tdo = bypass_reg;   // This is latched on a negative TCK edge after the output MUX
 
/**********************************************************************************
*                                                                                 *
*   End: Bypass logic                                                             *
*                                                                                 *
**********************************************************************************/
 
 
/**********************************************************************************
*                                                                                 *
*   Selecting active data register                                                *
*                                                                                 *
**********************************************************************************/
always @ (latched_jtag_ir)
begin
  extest_select           = 1'b0;
  sample_preload_select   = 1'b0;
  idcode_select           = 1'b0;
  mbist_select            = 1'b0;
  debug_select            = 1'b0;
  bypass_select           = 1'b0;
 
  case(latched_jtag_ir)    /* synthesis parallel_case */
    `EXTEST:            extest_select           = 1'b1;    // External test
    `SAMPLE_PRELOAD:    sample_preload_select   = 1'b1;    // Sample preload
    `IDCODE:            idcode_select           = 1'b1;    // ID Code
    `MBIST:             mbist_select            = 1'b1;    // Mbist test
    `DEBUG:             debug_select            = 1'b1;    // Debug
    `BYPASS:            bypass_select           = 1'b1;    // BYPASS
    default:            bypass_select           = 1'b1;    // BYPASS
  endcase
end
 
 
/**********************************************************************************
*                                                                                 *
*   Multiplexing TDO data                                                         *
*                                                                                 *
**********************************************************************************/
reg tdo_mux_out;  // really just a wire
 
always @ (shift_ir or instruction_tdo or latched_jtag_ir or idcode_tdo or
          debug_tdo_i or bs_chain_tdo_i or mbist_tdo_i or bypassed_tdo or
                        bs_chain_tdo_i)
begin
  if(shift_ir)
    tdo_mux_out = instruction_tdo;
  else
    begin
      case(latched_jtag_ir)    // synthesis parallel_case
        `IDCODE:            tdo_mux_out = idcode_tdo;       // Reading ID code
        `DEBUG:             tdo_mux_out = debug_tdo_i;      // Debug
        `SAMPLE_PRELOAD:    tdo_mux_out = bs_chain_tdo_i;   // Sampling/Preloading
        `EXTEST:            tdo_mux_out = bs_chain_tdo_i;   // External test
        `MBIST:             tdo_mux_out = mbist_tdo_i;      // Mbist test
        default:            tdo_mux_out = bypassed_tdo;     // BYPASS instruction
      endcase
    end
end
 
 
// TDO changes state at negative edge of TCK
always @ (negedge tck_pad_i)
begin
        tdo_pad_o = tdo_mux_out;
end
 
 
// Tristate control for tdo_pad_o pin
always @ (posedge tck_pad_i)
begin
  tdo_padoe_o <= #1 shift_ir | shift_dr;
end
/**********************************************************************************
*                                                                                 *
*   End: Multiplexing TDO data                                                    *
*                                                                                 *
**********************************************************************************/
 
endmodule

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Subversion Repositories adv_debug_sys

[/] [adv_debug_sys/] [trunk/] [Hardware/] [jtag/] [tap/] [rtl/] [verilog/] [tap_top.v] - Blame information for rev 14

Line No.	Rev	Author	Line
1	3	nyawn	`//////////////////////////////////////////////////////////////////////`
2			`//// ////`
3			`//// tap_top.v ////`
4			`//// ////`
5			`//// ////`
6			`//// This file is part of the JTAG Test Access Port (TAP) ////`
7			`//// ////`
8			`//// Author(s): ////`
9			`//// Igor Mohor (igorm@opencores.org) ////`
10			`//// Nathan Yawn (nathan.yawn@opencores.org) ////`
11			`//// ////`
12			`//// ////`
13			`//// All additional information is avaliable in the jtag.pdf ////`
14			`//// file. ////`
15			`//// ////`
16			`//////////////////////////////////////////////////////////////////////`
17			`//// ////`
18			`//// Copyright (C) 2000 - 2008 Authors ////`
19			`//// ////`
20			`//// This source file may be used and distributed without ////`
21			`//// restriction provided that this copyright statement is not ////`
22			`//// removed from the file and that any derivative work contains ////`
23			`//// the original copyright notice and the associated disclaimer. ////`
24			`//// ////`
25			`//// This source file is free software; you can redistribute it ////`
26			`//// and/or modify it under the terms of the GNU Lesser General ////`
27			`//// Public License as published by the Free Software Foundation; ////`
28			`//// either version 2.1 of the License, or (at your option) any ////`
29			`//// later version. ////`
30			`//// ////`
31			`//// This source is distributed in the hope that it will be ////`
32			`//// useful, but WITHOUT ANY WARRANTY; without even the implied ////`
33			`//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////`
34			`//// PURPOSE. See the GNU Lesser General Public License for more ////`
35			`//// details. ////`
36			`//// ////`
37			`//// You should have received a copy of the GNU Lesser General ////`
38			`//// Public License along with this source; if not, download it ////`
39			`//// from http://www.opencores.org/lgpl.shtml ////`
40			`//// ////`
41			`//////////////////////////////////////////////////////////////////////`
42			`//`
43			`// CVS Revision History`
44			`//`
45			`// $Log: tap_top.v,v $`
46	14	nyawn	`// Revision 1.5 2009/06/16 02:53:58 Nathan`
47			`// Changed some signal names for better consistency between different hardware modules. Removed stale CVS log/comments.`
48	3	nyawn	`//`
49	14	nyawn	`// Revision 1.4 2009/05/17 20:54:38 Nathan`
50			`// Changed email address to opencores.org`
51			`//`
52	3	nyawn	`// Revision 1.3 2008/06/18 18:45:07 Nathan`
53			`// Improved reset slightly. Cleanup.`
54			`//`
55			`//`
56			`// Revision 1.2 2008/05/14 13:13:24 Nathan`
57			`// Rewrote TAP FSM in canonical form, for readability. Switched`
58			`// from one-hot to binary encoding. Made reset signal active-`
59			`// low, per JTAG spec. Removed FF chain for 5 TMS reset - reset`
60			`// done in Test Logic Reset mode. Added test_logic_reset_o and`
61			`// run_test_idle_o signals. Removed double registers from IR data`
62			`// path. Unified the registers at the output of each data register`
63			`// to a single shared FF.`
64			`//`
65
66			`include "tap_defines.v"
67
68			`// Top module`
69			`module tap_top(`
70			`// JTAG pads`
71			`tms_pad_i,`
72			`tck_pad_i,`
73			`trstn_pad_i,`
74			`tdi_pad_i,`
75			`tdo_pad_o,`
76			`tdo_padoe_o,`
77
78			`// TAP states`
79			`test_logic_reset_o,`
80			`run_test_idle_o,`
81			`shift_dr_o,`
82			`pause_dr_o,`
83			`update_dr_o,`
84			`capture_dr_o,`
85
86			`// Select signals for boundary scan or mbist`
87			`extest_select_o,`
88			`sample_preload_select_o,`
89			`mbist_select_o,`
90			`debug_select_o,`
91
92			`// TDO signal that is connected to TDI of sub-modules.`
93	14	nyawn	`tdi_o,`
94	3	nyawn
95			`// TDI signals from sub-modules`
96	14	nyawn	`debug_tdo_i, // from debug module`
97			`bs_chain_tdo_i, // from Boundary Scan Chain`
98			`mbist_tdo_i // from Mbist Chain`
99	3	nyawn	`);`
100
101
102			`// JTAG pins`
103			`input tms_pad_i; // JTAG test mode select pad`
104			`input tck_pad_i; // JTAG test clock pad`
105			`input trstn_pad_i; // JTAG test reset pad`
106			`input tdi_pad_i; // JTAG test data input pad`
107			`output tdo_pad_o; // JTAG test data output pad`
108			`output tdo_padoe_o; // Output enable for JTAG test data output pad`
109
110			`// TAP states`
111			`output test_logic_reset_o;`
112			`output run_test_idle_o;`
113			`output shift_dr_o;`
114			`output pause_dr_o;`
115			`output update_dr_o;`
116			`output capture_dr_o;`
117
118			`// Select signals for boundary scan or mbist`
119			`output extest_select_o;`
120			`output sample_preload_select_o;`
121			`output mbist_select_o;`
122			`output debug_select_o;`
123
124			`// TDO signal that is connected to TDI of sub-modules.`
125	14	nyawn	`output tdi_o;`
126	3	nyawn
127			`// TDI signals from sub-modules`
128	14	nyawn	`input debug_tdo_i; // from debug module`
129			`input bs_chain_tdo_i; // from Boundary Scan Chain`
130			`input mbist_tdo_i; // from Mbist Chain`
131	3	nyawn
132			`// Wires which depend on the state of the TAP FSM`
133			`reg test_logic_reset;`
134			`reg run_test_idle;`
135			`reg select_dr_scan;`
136			`reg capture_dr;`
137			`reg shift_dr;`
138			`reg exit1_dr;`
139			`reg pause_dr;`
140			`reg exit2_dr;`
141			`reg update_dr;`
142			`reg select_ir_scan;`
143			`reg capture_ir;`
144			`reg shift_ir;`
145			`reg exit1_ir;`
146			`reg pause_ir;`
147			`reg exit2_ir;`
148			`reg update_ir;`
149
150			`// Wires which depend on the current value in the IR`
151			`reg extest_select;`
152			`reg sample_preload_select;`
153			`reg idcode_select;`
154			`reg mbist_select;`
155			`reg debug_select;`
156			`reg bypass_select;`
157
158			`// TDO and enable`
159			`reg tdo_pad_o;`
160			`reg tdo_padoe_o;`
161
162	14	nyawn	`assign tdi_o = tdi_pad_i;`
163	3	nyawn
164			`assign test_logic_reset_o = test_logic_reset;`
165			`assign run_test_idle_o = run_test_idle;`
166			`assign shift_dr_o = shift_dr;`
167			`assign pause_dr_o = pause_dr;`
168			`assign update_dr_o = update_dr;`
169			`assign capture_dr_o = capture_dr;`
170
171			`assign extest_select_o = extest_select;`
172			`assign sample_preload_select_o = sample_preload_select;`
173			`assign mbist_select_o = mbist_select;`
174			`assign debug_select_o = debug_select;`
175
176
177			`/**********************************************************************************`
178			`* *`
179			`* TAP State Machine: Fully JTAG compliant *`
180			`* *`
181			`**********************************************************************************/`
182			`// Definition of machine state values. We could one-hot encode this, and use 16`
183			`// registers, but this uses binary encoding for the minimum of 4 DFF's instead.`
184			`define STATE_test_logic_reset 4'hF
185			`define STATE_run_test_idle 4'hC
186			`define STATE_select_dr_scan 4'h7
187			`define STATE_capture_dr 4'h6
188			`define STATE_shift_dr 4'h2
189			`define STATE_exit1_dr 4'h1
190			`define STATE_pause_dr 4'h3
191			`define STATE_exit2_dr 4'h0
192			`define STATE_update_dr 4'h5
193			`define STATE_select_ir_scan 4'h4
194			`define STATE_capture_ir 4'hE
195			`define STATE_shift_ir 4'hA
196			`define STATE_exit1_ir 4'h9
197			`define STATE_pause_ir 4'hB
198			`define STATE_exit2_ir 4'h8
199			`define STATE_update_ir 4'hD
200
201			reg [3:0] TAP_state = `STATE_test_logic_reset; // current state of the TAP controller
202			`reg [3:0] next_TAP_state; // state TAP will take at next rising TCK, combinational signal`
203
204			`// sequential part of the FSM`
205			`always @ (posedge tck_pad_i or negedge trstn_pad_i)`
206			`begin`
207			`if(trstn_pad_i == 0)`
208			TAP_state = `STATE_test_logic_reset;
209			`else`
210			`TAP_state = next_TAP_state;`
211			`end`
212
213
214			`// Determination of next state; purely combinatorial`
215			`always @ (TAP_state or tms_pad_i)`
216			`begin`
217			`case(TAP_state)`
218			`STATE_test_logic_reset:
219			`begin`
220			if(tms_pad_i) next_TAP_state = `STATE_test_logic_reset;
221			else next_TAP_state = `STATE_run_test_idle;
222			`end`
223			`STATE_run_test_idle:
224			`begin`
225			if(tms_pad_i) next_TAP_state = `STATE_select_dr_scan;
226			else next_TAP_state = `STATE_run_test_idle;
227			`end`
228			`STATE_select_dr_scan:
229			`begin`
230			if(tms_pad_i) next_TAP_state = `STATE_select_ir_scan;
231			else next_TAP_state = `STATE_capture_dr;
232			`end`
233			`STATE_capture_dr:
234			`begin`
235			if(tms_pad_i) next_TAP_state = `STATE_exit1_dr;
236			else next_TAP_state = `STATE_shift_dr;
237			`end`
238			`STATE_shift_dr:
239			`begin`
240			if(tms_pad_i) next_TAP_state = `STATE_exit1_dr;
241			else next_TAP_state = `STATE_shift_dr;
242			`end`
243			`STATE_exit1_dr:
244			`begin`
245			if(tms_pad_i) next_TAP_state = `STATE_update_dr;
246			else next_TAP_state = `STATE_pause_dr;
247			`end`
248			`STATE_pause_dr:
249			`begin`
250			if(tms_pad_i) next_TAP_state = `STATE_exit2_dr;
251			else next_TAP_state = `STATE_pause_dr;
252			`end`
253			`STATE_exit2_dr:
254			`begin`
255			if(tms_pad_i) next_TAP_state = `STATE_update_dr;
256			else next_TAP_state = `STATE_shift_dr;
257			`end`
258			`STATE_update_dr:
259			`begin`
260			if(tms_pad_i) next_TAP_state = `STATE_select_dr_scan;
261			else next_TAP_state = `STATE_run_test_idle;
262			`end`
263			`STATE_select_ir_scan:
264			`begin`
265			if(tms_pad_i) next_TAP_state = `STATE_test_logic_reset;
266			else next_TAP_state = `STATE_capture_ir;
267			`end`
268			`STATE_capture_ir:
269			`begin`
270			if(tms_pad_i) next_TAP_state = `STATE_exit1_ir;
271			else next_TAP_state = `STATE_shift_ir;
272			`end`
273			`STATE_shift_ir:
274			`begin`
275			if(tms_pad_i) next_TAP_state = `STATE_exit1_ir;
276			else next_TAP_state = `STATE_shift_ir;
277			`end`
278			`STATE_exit1_ir:
279			`begin`
280			if(tms_pad_i) next_TAP_state = `STATE_update_ir;
281			else next_TAP_state = `STATE_pause_ir;
282			`end`
283			`STATE_pause_ir:
284			`begin`
285			if(tms_pad_i) next_TAP_state = `STATE_exit2_ir;
286			else next_TAP_state = `STATE_pause_ir;
287			`end`
288			`STATE_exit2_ir:
289			`begin`
290			if(tms_pad_i) next_TAP_state = `STATE_update_ir;
291			else next_TAP_state = `STATE_shift_ir;
292			`end`
293			`STATE_update_ir:
294			`begin`
295			if(tms_pad_i) next_TAP_state = `STATE_select_dr_scan;
296			else next_TAP_state = `STATE_run_test_idle;
297			`end`
298			default: next_TAP_state = `STATE_test_logic_reset; // can't actually happen
299			`endcase`
300			`end`
301
302
303			`// Outputs of state machine, pure combinatorial`
304			`always @ (TAP_state)`
305			`begin`
306			`// Default everything to 0, keeps the case statement simple`
307			`test_logic_reset = 1'b0;`
308			`run_test_idle = 1'b0;`
309			`select_dr_scan = 1'b0;`
310			`capture_dr = 1'b0;`
311			`shift_dr = 1'b0;`
312			`exit1_dr = 1'b0;`
313			`pause_dr = 1'b0;`
314			`exit2_dr = 1'b0;`
315			`update_dr = 1'b0;`
316			`select_ir_scan = 1'b0;`
317			`capture_ir = 1'b0;`
318			`shift_ir = 1'b0;`
319			`exit1_ir = 1'b0;`
320			`pause_ir = 1'b0;`
321			`exit2_ir = 1'b0;`
322			`update_ir = 1'b0;`
323
324			`case(TAP_state)`
325			`STATE_test_logic_reset: test_logic_reset = 1'b1;
326			`STATE_run_test_idle: run_test_idle = 1'b1;
327			`STATE_select_dr_scan: select_dr_scan = 1'b1;
328			`STATE_capture_dr: capture_dr = 1'b1;
329			`STATE_shift_dr: shift_dr = 1'b1;
330			`STATE_exit1_dr: exit1_dr = 1'b1;
331			`STATE_pause_dr: pause_dr = 1'b1;
332			`STATE_exit2_dr: exit2_dr = 1'b1;
333			`STATE_update_dr: update_dr = 1'b1;
334			`STATE_select_ir_scan: select_ir_scan = 1'b1;
335			`STATE_capture_ir: capture_ir = 1'b1;
336			`STATE_shift_ir: shift_ir = 1'b1;
337			`STATE_exit1_ir: exit1_ir = 1'b1;
338			`STATE_pause_ir: pause_ir = 1'b1;
339			`STATE_exit2_ir: exit2_ir = 1'b1;
340			`STATE_update_ir: update_ir = 1'b1;
341			`default: ;`
342			`endcase`
343			`end`
344
345			`/**********************************************************************************`
346			`* *`
347			`* End: TAP State Machine *`
348			`* *`
349			`**********************************************************************************/`
350
351
352
353			`/**********************************************************************************`
354			`* *`
355			`* jtag_ir: JTAG Instruction Register *`
356			`* *`
357			`**********************************************************************************/`
358			reg [`IR_LENGTH-1:0] jtag_ir; // Instruction register
359			reg [`IR_LENGTH-1:0] latched_jtag_ir; //, latched_jtag_ir_neg;
360			`wire instruction_tdo;`
361
362			`always @ (posedge tck_pad_i or negedge trstn_pad_i)`
363			`begin`
364			`if(trstn_pad_i == 0)`
365			jtag_ir[`IR_LENGTH-1:0] <= #1 `IR_LENGTH'b0;
366			`else if (test_logic_reset == 1)`
367			jtag_ir[`IR_LENGTH-1:0] <= #1 `IR_LENGTH'b0;
368			`else if(capture_ir)`
369			`jtag_ir <= #1 4'b0101; // This value is fixed for easier fault detection`
370			`else if(shift_ir)`
371			jtag_ir[`IR_LENGTH-1:0] <= #1 {tdi_pad_i, jtag_ir[`IR_LENGTH-1:1]};
372			`end`
373
374			`assign instruction_tdo = jtag_ir[0]; // This is latched on a negative TCK edge after the output MUX`
375
376			`// Updating jtag_ir (Instruction Register)`
377			`// jtag_ir should be latched on FALLING EDGE of TCK when capture_ir == 1`
378			`always @ (negedge tck_pad_i or negedge trstn_pad_i)`
379			`begin`
380			`if(trstn_pad_i == 0)`
381			latched_jtag_ir <=#1 `IDCODE; // IDCODE selected after reset
382			`else if (test_logic_reset)`
383			latched_jtag_ir <=#1 `IDCODE; // IDCODE selected after reset
384			`else if(update_ir)`
385			`latched_jtag_ir <=#1 jtag_ir;`
386			`end`
387
388			`/**********************************************************************************`
389			`* *`
390			`* End: jtag_ir *`
391			`* *`
392			`**********************************************************************************/`
393
394
395
396			`/**********************************************************************************`
397			`* *`
398			`* idcode logic *`
399			`* *`
400			`**********************************************************************************/`
401			`reg [31:0] idcode_reg;`
402			`wire idcode_tdo;`
403
404			`always @ (posedge tck_pad_i or negedge trstn_pad_i)`
405			`begin`
406			`if(trstn_pad_i == 0)`
407			idcode_reg <=#1 `IDCODE_VALUE; // IDCODE selected after reset
408			`else if (test_logic_reset)`
409			idcode_reg <=#1 `IDCODE_VALUE; // IDCODE selected after reset
410			`else if(idcode_select & capture_dr)`
411			idcode_reg <= #1 `IDCODE_VALUE;
412			`else if(idcode_select & shift_dr)`
413			`idcode_reg <= #1 {tdi_pad_i, idcode_reg[31:1]};`
414
415			`end`
416
417			`assign idcode_tdo = idcode_reg[0]; // This is latched on a negative TCK edge after the output MUX`
418
419			`/**********************************************************************************`
420			`* *`
421			`* End: idcode logic *`
422			`* *`
423			`**********************************************************************************/`
424
425
426			`/**********************************************************************************`
427			`* *`
428			`* Bypass logic *`
429			`* *`
430			`**********************************************************************************/`
431			`wire bypassed_tdo;`
432			`reg bypass_reg; // This is a 1-bit register`
433
434			`always @ (posedge tck_pad_i or negedge trstn_pad_i)`
435			`begin`
436			`if (trstn_pad_i == 0)`
437			`bypass_reg <= #1 1'b0;`
438			`else if (test_logic_reset == 1)`
439			`bypass_reg <= #1 1'b0;`
440			`else if (bypass_select & capture_dr)`
441			`bypass_reg<=#1 1'b0;`
442			`else if(bypass_select & shift_dr)`
443			`bypass_reg<=#1 tdi_pad_i;`
444			`end`
445
446			`assign bypassed_tdo = bypass_reg; // This is latched on a negative TCK edge after the output MUX`
447
448			`/**********************************************************************************`
449			`* *`
450			`* End: Bypass logic *`
451			`* *`
452			`**********************************************************************************/`
453
454
455			`/**********************************************************************************`
456			`* *`
457			`* Selecting active data register *`
458			`* *`
459			`**********************************************************************************/`
460			`always @ (latched_jtag_ir)`
461			`begin`
462			`extest_select = 1'b0;`
463			`sample_preload_select = 1'b0;`
464			`idcode_select = 1'b0;`
465			`mbist_select = 1'b0;`
466			`debug_select = 1'b0;`
467			`bypass_select = 1'b0;`
468
469			`case(latched_jtag_ir) /* synthesis parallel_case */`
470			`EXTEST: extest_select = 1'b1; // External test
471			`SAMPLE_PRELOAD: sample_preload_select = 1'b1; // Sample preload
472			`IDCODE: idcode_select = 1'b1; // ID Code
473			`MBIST: mbist_select = 1'b1; // Mbist test
474			`DEBUG: debug_select = 1'b1; // Debug
475			`BYPASS: bypass_select = 1'b1; // BYPASS
476			`default: bypass_select = 1'b1; // BYPASS`
477			`endcase`
478			`end`
479
480
481			`/**********************************************************************************`
482			`* *`
483			`* Multiplexing TDO data *`
484			`* *`
485			`**********************************************************************************/`
486			`reg tdo_mux_out; // really just a wire`
487
488			`always @ (shift_ir or instruction_tdo or latched_jtag_ir or idcode_tdo or`
489	14	nyawn	`debug_tdo_i or bs_chain_tdo_i or mbist_tdo_i or bypassed_tdo or`
490			`bs_chain_tdo_i)`
491	3	nyawn	`begin`
492			`if(shift_ir)`
493			`tdo_mux_out = instruction_tdo;`
494			`else`
495			`begin`
496			`case(latched_jtag_ir) // synthesis parallel_case`
497			`IDCODE: tdo_mux_out = idcode_tdo; // Reading ID code
498	14	nyawn	`DEBUG: tdo_mux_out = debug_tdo_i; // Debug
499			`SAMPLE_PRELOAD: tdo_mux_out = bs_chain_tdo_i; // Sampling/Preloading
500			`EXTEST: tdo_mux_out = bs_chain_tdo_i; // External test
501			`MBIST: tdo_mux_out = mbist_tdo_i; // Mbist test
502	3	nyawn	`default: tdo_mux_out = bypassed_tdo; // BYPASS instruction`
503			`endcase`
504			`end`
505			`end`
506
507
508			`// TDO changes state at negative edge of TCK`
509			`always @ (negedge tck_pad_i)`
510			`begin`
511			`tdo_pad_o = tdo_mux_out;`
512			`end`
513
514
515			`// Tristate control for tdo_pad_o pin`
516			`always @ (posedge tck_pad_i)`
517			`begin`
518			`tdo_padoe_o <= #1 shift_ir \| shift_dr;`
519			`end`
520			`/**********************************************************************************`
521			`* *`
522			`* End: Multiplexing TDO data *`
523			`* *`
524			`**********************************************************************************/`
525
526			`endmodule`