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[/] [adv_debug_sys/] [trunk/] [Software/] [AdvancedWatchpointControl/] [src/] [advancedWatchpointControl/] [targetDebugRegisterSet.java] - Blame information for rev 51

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Line No. Rev Author Line
1 51 nyawn 
// This class holds a direct, cached copy of the debug registers
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// on the OR1000 target CPU.  It relies on other classes to
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// interpret the meanings of the values.
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package advancedWatchpointControl;
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public class targetDebugRegisterSet {
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        public enum regType { DCR0, DVR0, DCR1, DVR1, DCR2, DVR2, DCR3, DVR3,
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                DCR4, DVR4, DCR5, DVR5, DCR6, DVR6, DCR7, DVR7, DMR1, DMR2, DWCR0, DWCR1 }
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        // These reflect the values of the registers on the target
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        // They must be 'long's, because they're unsigned ints.
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        private long dcr[] = { 1, 1, 0, 0, 1, 1, 1, 1 };
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        private long dvr[] = { 0, 0, 0, 0, 0, 0, 0, 0 };
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        private long dmr1 = 0;
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        private long dmr2 = 0;
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        private long dwcr0 = 0;
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        private long dwcr1 = 0;
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        public void setDCR(int which, long val) {
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                dcr[which] = val;
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        }
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        public long getDCR(int which) {
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                return dcr[which];
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        }
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        public void setDVR(int which, long val) {
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                dvr[which] = val;
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        }
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        public long getDVR(int which) {
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                return dvr[which];
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        }
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        public void setDMR1(long val) {
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                dmr1 = val;
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        }
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        public long getDMR1() {
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                return dmr1;
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        }
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        public void setDMR2(long val) {
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                dmr2 = val;
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        }
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        public long getDMR2() {
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                return dmr2;
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        }
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        public void setDWCR0(long val) {
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                dwcr0 = val;
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        }
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        public long getDWCR0() {
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                return dwcr0;
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        }
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        public void setDWCR1(long val) {
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                dwcr1 = val;
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        }
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        public long getDWCR1() {
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                return dwcr1;
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        }
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        public static int getRegisterAddress(regType reg) {
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                int retval = 0;
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                int dgroup = 6 << 11;  // DEBUG group is 6, 11 bits is the group offset
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                switch(reg) {
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                case DCR0:
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                        retval = dgroup | 8;
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                        break;
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                case DVR0:
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                        retval = dgroup | 0;
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                        break;
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                case DCR1:
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                        retval = dgroup | 9;
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                        break;
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                case DVR1:
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                        retval = dgroup | 1;
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                        break;
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                case DCR2:
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                        retval = dgroup | 10;
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                        break;
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                case DVR2:
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                        retval = dgroup | 2;
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                        break;
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                case DCR3:
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                        retval = dgroup | 11;
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                        break;
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                case DVR3:
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                        retval = dgroup | 3;
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                        break;
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                case DCR4:
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                        retval = dgroup | 12;
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                        break;
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                case DVR4:
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                        retval = dgroup | 4;
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                        break;
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                case DCR5:
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                        retval = dgroup | 13;
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                        break;
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                case DVR5:
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                        retval = dgroup | 5;
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                        break;
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                case DCR6:
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                        retval = dgroup | 14;
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                        break;
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                case DVR6:
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                        retval = dgroup | 6;
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                        break;
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                case DCR7:
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                        retval = dgroup | 15;
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                        break;
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                case DVR7:
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                        retval = dgroup | 7;
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                        break;
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                case DMR1:
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                        retval = dgroup | 16;
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                        break;
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                case DMR2:
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                        retval = dgroup | 17;
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                        break;
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                case DWCR0:
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                        retval = dgroup | 18;
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                        break;
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                case DWCR1:
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                        retval = dgroup | 19;
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                        break;
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                default:
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                        break;  // Register address 0 is the version register...read-only and harmless.
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                }
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                return retval;
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        }
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}

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