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[/] [adv_debug_sys/] [trunk/] [Software/] [adv_jtag_bridge/] [dbg_api.c] - Blame information for rev 59

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Line No. Rev Author Line
1 21 nyawn 
/* dbg_api.c -- JTAG protocol bridge between GDB and Advanced debug module.
2 59 nyawn 
   Copyright(C) 2009 - 2011 Nathan Yawn, nyawn@opencores.net
3 21 nyawn 
   based on code from jp2 by Marko Mlinar, markom@opencores.org
4 
 
5 
   This file contains API functions which may be called from the GDB
6 
   interface server.  These functions call the appropriate hardware-
7 
   specific functions for the advanced debug interface or the legacy
8 
   debug interface, depending on which is selected.
9 
 
10 
   This program is free software; you can redistribute it and/or modify
11 
   it under the terms of the GNU General Public License as published by
12 
   the Free Software Foundation; either version 2 of the License, or
13 
   (at your option) any later version.
14 
 
15 
   This program is distributed in the hope that it will be useful,
16 
   but WITHOUT ANY WARRANTY; without even the implied warranty of
17 
   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
18 
   GNU General Public License for more details.
19 
 
20 
   You should have received a copy of the GNU General Public License
21 
   along with this program; if not, write to the Free Software
22 
   Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
23 
*/
24 
 
25 
 
26 
 
27 
#include <stdio.h>
28 
#include <pthread.h>  // for mutexes
29 
#include <arpa/inet.h>  // for ntohl()
30 
 
31 
#include "adv_dbg_commands.h"
32 
#include "legacy_dbg_commands.h"
33 
#include "cable_common.h"
34 
#include "errcodes.h"
35 
 
36 
#define debug(...) //fprintf(stderr, __VA_ARGS__ )
37 
 
38 
#define DBG_HW_ADVANCED 1
39 
#define DBG_HW_LEGACY   2
40 
#ifdef __LEGACY__
41 
#define DEBUG_HARDWARE DBG_HW_LEGACY
42 
#else
43 
#define DEBUG_HARDWARE  DBG_HW_ADVANCED
44 
#endif
45 
 
46 
pthread_mutex_t dbg_access_mutex = PTHREAD_MUTEX_INITIALIZER;
47 
 
48 
/* read a word from wishbone */
49 50 nyawn 
int dbg_wb_read32(uint32_t adr, uint32_t *data) {
50 21 nyawn 
  int err;
51 
  pthread_mutex_lock(&dbg_access_mutex);
52 
 
53 
  if(DEBUG_HARDWARE == DBG_HW_ADVANCED)
54 
    {
55 
      if ((err = adbg_select_module(DC_WISHBONE)))
56 
        {
57 
          cable_flush();
58 
          pthread_mutex_unlock(&dbg_access_mutex);
59 
          return err;
60 
        }
61 
      err = adbg_wb_burst_read(4, 1, adr, (void *)data); // All WB reads / writes are bursts
62 
    }
63 
  else if(DEBUG_HARDWARE == DBG_HW_LEGACY)
64 
    {
65 
      if (APP_ERR_NONE == (err = legacy_dbg_set_chain(DC_WISHBONE)))
66 
        if (APP_ERR_NONE == (err = legacy_dbg_command(0x6, adr, 4)))
67 
          err = legacy_dbg_go((unsigned char*)data, 4, 1);
68 
      *data = ntohl(*data);
69 
    }
70 
  cable_flush();
71 
  pthread_mutex_unlock(&dbg_access_mutex);
72 
  return err;
73 
}
74 
 
75 
/* write a word to wishbone */
76 50 nyawn 
int dbg_wb_write32(uint32_t adr, uint32_t data) {
77 21 nyawn 
  int err;
78 
  pthread_mutex_lock(&dbg_access_mutex);
79 
 
80 
  if(DEBUG_HARDWARE == DBG_HW_ADVANCED)
81 
    {
82 
      if ((err = adbg_select_module(DC_WISHBONE)))
83 
        {
84 
          cable_flush();
85 
          pthread_mutex_unlock(&dbg_access_mutex);
86 
          return err;
87 
        }
88 
      err = adbg_wb_burst_write((void *)&data, 4, 1, adr);
89 
    }
90 
  else if(DEBUG_HARDWARE == DBG_HW_LEGACY)
91 
    {
92 
      data = ntohl(data);
93 
      if (APP_ERR_NONE == (err = legacy_dbg_set_chain(DC_WISHBONE)))
94 
        if (APP_ERR_NONE == (err = legacy_dbg_command(0x2, adr, 4)))
95 
          err = legacy_dbg_go((unsigned char*)&data, 4, 0);
96 
    }
97 
  cable_flush();
98 
  pthread_mutex_unlock(&dbg_access_mutex);
99 
  return err;
100 
}
101 
 
102 
// write a word to wishbone
103 
// Never actually called from the GDB interface
104 50 nyawn 
int dbg_wb_write16(uint32_t adr, uint16_t data) {
105 21 nyawn 
  int err;
106 
  pthread_mutex_lock(&dbg_access_mutex);
107 
 
108 
  if(DEBUG_HARDWARE == DBG_HW_ADVANCED)
109 
    {
110 
      if ((err = adbg_select_module(DC_WISHBONE)))
111 
        {
112 
          cable_flush();
113 
          pthread_mutex_unlock(&dbg_access_mutex);
114 
          return err;
115 
        }
116 
      err = adbg_wb_burst_write((void *)&data, 2, 1, adr);
117 
    }
118 
  else if(DEBUG_HARDWARE == DBG_HW_LEGACY)
119 
    {
120 
        data = ntohs(data);
121 
        if (APP_ERR_NONE == (err = legacy_dbg_set_chain(DC_WISHBONE)))
122 
          if (APP_ERR_NONE == (err = legacy_dbg_command(0x1, adr, 2)))
123 
            err = legacy_dbg_go((unsigned char*)&data, 2, 0);
124 
    }
125 
  cable_flush();
126 
  pthread_mutex_unlock(&dbg_access_mutex);
127 
  return err;
128 
}
129 
 
130 
// write a word to wishbone
131 
// Never actually called from the GDB interface
132 50 nyawn 
int dbg_wb_write8(uint32_t adr, uint8_t data) {
133 21 nyawn 
  int err;
134 
  pthread_mutex_lock(&dbg_access_mutex);
135 
 
136 
  if(DEBUG_HARDWARE == DBG_HW_ADVANCED)
137 
    {
138 
      if ((err = adbg_select_module(DC_WISHBONE)))
139 
        {
140 
          cable_flush();
141 
          pthread_mutex_unlock(&dbg_access_mutex);
142 
          return err;
143 
        }
144 
      err = adbg_wb_burst_write((void *)&data, 1, 1, adr);
145 
    }
146 
  else if(DEBUG_HARDWARE == DBG_HW_LEGACY)
147 
    {
148 
        if (APP_ERR_NONE == (err = legacy_dbg_set_chain(DC_WISHBONE)))
149 
          if (APP_ERR_NONE == (err = legacy_dbg_command(0x0, adr, 1)))
150 
            err = legacy_dbg_go((unsigned char*)&data, 1, 0);
151 
    }
152 
  cable_flush();
153 
  pthread_mutex_unlock(&dbg_access_mutex);
154 
  return err;
155 
}
156 
 
157 
 
158 50 nyawn 
int dbg_wb_read_block32(uint32_t adr, uint32_t *data, int len) {
159 21 nyawn 
  int err;
160 
 
161 
  if(!len)
162 
    return APP_ERR_NONE;  // GDB may issue a 0-length transaction to test if a feature is supported
163 
 
164 29 nyawn 
  pthread_mutex_lock(&dbg_access_mutex);
165 21 nyawn 
  if(DEBUG_HARDWARE == DBG_HW_ADVANCED)
166 
    {
167 
      if ((err = adbg_select_module(DC_WISHBONE)))
168 
        {
169 
          cable_flush();
170 
          pthread_mutex_unlock(&dbg_access_mutex);
171 
          return err;
172 
        }
173 
      err = adbg_wb_burst_read(4, len, adr, (void *)data);  // 'len' is words.
174 
    }
175 
  else if(DEBUG_HARDWARE == DBG_HW_LEGACY)
176 
    {
177 
      int i;
178 
      int bytelen = len<<2;
179 
      if (APP_ERR_NONE == (err = legacy_dbg_set_chain(DC_WISHBONE)))
180 
        if (APP_ERR_NONE == (err = legacy_dbg_command(0x6, adr, bytelen)))
181 
          if (APP_ERR_NONE == (err = legacy_dbg_go((unsigned char*)data, bytelen, 1))) // 'len' is words, call wants bytes
182 
            for (i = 0; i < len; i ++) data[i] = ntohl(data[i]);
183 
    }
184 
  cable_flush();
185 
  pthread_mutex_unlock(&dbg_access_mutex);
186 
  return err;
187 
}
188 
 
189 
 
190 
// Never actually called from the GDB interface
191 50 nyawn 
int dbg_wb_read_block16(uint32_t adr, uint16_t *data, int len) {
192 21 nyawn 
  int err;
193 
 
194 
  if(!len)
195 
    return APP_ERR_NONE;  // GDB may issue a 0-length transaction to test if a feature is supported
196 
 
197 29 nyawn 
  pthread_mutex_lock(&dbg_access_mutex);
198 21 nyawn 
  if(DEBUG_HARDWARE == DBG_HW_ADVANCED)
199 
    {
200 
      if ((err = adbg_select_module(DC_WISHBONE)))
201 
        {
202 
          cable_flush();
203 
          pthread_mutex_unlock(&dbg_access_mutex);
204 
          return err;
205 
        }
206 
      err = adbg_wb_burst_read(2, len, adr, (void *)data);  // 'len' is 16-bit halfwords
207 
    }
208 
  else if(DEBUG_HARDWARE == DBG_HW_LEGACY)
209 
    {
210 
      int i;
211 
      int bytelen = len<<1;
212 
      if (APP_ERR_NONE == (err = legacy_dbg_set_chain(DC_WISHBONE)))
213 
        if (APP_ERR_NONE == (err = legacy_dbg_command(0x5, adr, bytelen)))
214 
          if (APP_ERR_NONE == (err = legacy_dbg_go((unsigned char*)data, bytelen, 1)))  // 'len' is halfwords, call wants bytes
215 
            for (i = 0; i < len; i ++) data[i] = ntohs(data[i]);
216 
    }
217 
  cable_flush();
218 
  pthread_mutex_unlock(&dbg_access_mutex);
219 
  return err;
220 
}
221 
 
222 
// Never actually called from the GDB interface
223 50 nyawn 
int dbg_wb_read_block8(uint32_t adr, uint8_t *data, int len) {
224 21 nyawn 
  int err;
225 
 
226 
  if(!len)
227 
    return APP_ERR_NONE;  // GDB may issue a 0-length transaction to test if a feature is supported
228 
 
229 29 nyawn 
  pthread_mutex_lock(&dbg_access_mutex);
230 21 nyawn 
  if(DEBUG_HARDWARE == DBG_HW_ADVANCED)
231 
    {
232 
      if ((err = adbg_select_module(DC_WISHBONE)))
233 
        {
234 
          cable_flush();
235 
          pthread_mutex_unlock(&dbg_access_mutex);
236 
          return err;
237 
        }
238 
      err = adbg_wb_burst_read(1, len, adr, (void *)data);  // *** is 'len' bits or words?? Call wants words...
239 
    }
240 
  else if(DEBUG_HARDWARE == DBG_HW_LEGACY)
241 
    {
242 
      if (APP_ERR_NONE == (err = legacy_dbg_set_chain(DC_WISHBONE)))
243 
        if (APP_ERR_NONE == (err = legacy_dbg_command(0x4, adr, len)))
244 
          err = legacy_dbg_go((unsigned char*)data, len, 1);
245 
    }
246 
  cable_flush();
247 
  pthread_mutex_unlock(&dbg_access_mutex);
248 
  return err;
249 
}
250 
 
251 
 
252 
// write a block to wishbone
253 50 nyawn 
int dbg_wb_write_block32(uint32_t adr, uint32_t *data, int len) {
254 21 nyawn 
  int err;
255 
 
256 
  if(!len)
257 
    return APP_ERR_NONE;  // GDB may issue a 0-length transaction to test if a feature is supported
258 
 
259 29 nyawn 
  pthread_mutex_lock(&dbg_access_mutex);
260 21 nyawn 
  if(DEBUG_HARDWARE == DBG_HW_ADVANCED)
261 
    {
262 
      if ((err = adbg_select_module(DC_WISHBONE)))
263 
        {
264 
          cable_flush();
265 
          pthread_mutex_unlock(&dbg_access_mutex);
266 
          return err;
267 
        }
268 
      err = adbg_wb_burst_write((void *)data, 4, len, adr);  // 'len' is words.
269 
    }
270 
  else if(DEBUG_HARDWARE == DBG_HW_LEGACY)
271 
    {
272 
      int i;
273 
      int bytelen = len << 2;
274 
      for (i = 0; i < len; i ++) data[i] = ntohl(data[i]);
275 
      if (APP_ERR_NONE == (err = legacy_dbg_set_chain(DC_WISHBONE)))
276 
        if (APP_ERR_NONE == (err = legacy_dbg_command(0x2, adr, bytelen)))
277 
          err = legacy_dbg_go((unsigned char*)data, bytelen, 0);  // 'len' is words, call wants bytes
278 
    }
279 
  cable_flush();
280 
  pthread_mutex_unlock(&dbg_access_mutex);
281 
  return err;
282 
}
283 
 
284 
 
285 
// write a block to wishbone
286 
// Never actually called from the GDB interface
287 50 nyawn 
int dbg_wb_write_block16(uint32_t adr, uint16_t *data, int len) {
288 21 nyawn 
  int err;
289 
 
290 
  if(!len)
291 
    return APP_ERR_NONE;  // GDB may issue a 0-length transaction to test if a feature is supported
292 
 
293 29 nyawn 
  pthread_mutex_lock(&dbg_access_mutex);
294 21 nyawn 
  if(DEBUG_HARDWARE == DBG_HW_ADVANCED)
295 
    {
296 
      if ((err = adbg_select_module(DC_WISHBONE)))
297 
        {
298 
          cable_flush();
299 
          pthread_mutex_unlock(&dbg_access_mutex);
300 
          return err;
301 
        }
302 
      err = adbg_wb_burst_write((void *)data, 2, len, adr);  // 'len' is (half)words
303 
    }
304 
  else if(DEBUG_HARDWARE == DBG_HW_LEGACY)
305 
    {
306 
      int i;
307 
      int bytelen = len<<1;
308 
      for (i = 0; i < len; i ++) data[i] = ntohs(data[i]);
309 
      if (APP_ERR_NONE == (err = legacy_dbg_set_chain(DC_WISHBONE)))
310 
        if (APP_ERR_NONE == (err = legacy_dbg_command(0x1, adr, bytelen)))
311 
          err = legacy_dbg_go((unsigned char*)data, bytelen, 0);  // 'len' is 16-bit halfwords, call wants bytes
312 
    }
313 
  cable_flush();
314 
  pthread_mutex_unlock(&dbg_access_mutex);
315 
  return err;
316 
}
317 
 
318 
// write a block to wishbone
319 50 nyawn 
int dbg_wb_write_block8(uint32_t adr, uint8_t *data, int len) {
320 21 nyawn 
  int err;
321 
 
322 
  if(!len)
323 
    return APP_ERR_NONE;  // GDB may issue a 0-length transaction to test if a feature is supported
324 
 
325 29 nyawn 
  pthread_mutex_lock(&dbg_access_mutex);
326 21 nyawn 
  if(DEBUG_HARDWARE == DBG_HW_ADVANCED)
327 
    {
328 
      if ((err = adbg_select_module(DC_WISHBONE)))
329 
        {
330 
          cable_flush();
331 
          pthread_mutex_unlock(&dbg_access_mutex);
332 
          return err;
333 
        }
334 
      err = adbg_wb_burst_write((void *)data, 1, len, adr);  // 'len' is in words...
335 
    }
336 
  else if(DEBUG_HARDWARE == DBG_HW_LEGACY)
337 
    {
338 
      if (APP_ERR_NONE == (err = legacy_dbg_set_chain(DC_WISHBONE)))
339 
        if (APP_ERR_NONE == (err = legacy_dbg_command(0x0, adr, len)))
340 
          err = legacy_dbg_go((unsigned char*)data, len, 0);
341 
    }
342 
  cable_flush();
343 
  pthread_mutex_unlock(&dbg_access_mutex);
344 
  return err;
345 
}
346 
 
347 
 
348 
/* read a register from cpu0.  This is assumed to be an OR32 CPU, with 32-bit regs. */
349 50 nyawn 
int dbg_cpu0_read(uint32_t adr, uint32_t *data) {
350 21 nyawn 
  int err;
351 
  pthread_mutex_lock(&dbg_access_mutex);
352 
 
353 
  if(DEBUG_HARDWARE == DBG_HW_ADVANCED)
354 
    {
355 
      if ((err = adbg_select_module(DC_CPU0)))
356 
        {
357 
          cable_flush();
358 
          pthread_mutex_unlock(&dbg_access_mutex);
359 
          return err;
360 
        }
361 
      err = adbg_wb_burst_read(4, 1, adr, (void *) data); // All CPU register reads / writes are bursts
362 
    }
363 
  else if(DEBUG_HARDWARE == DBG_HW_LEGACY)
364 
    {
365 
      if (APP_ERR_NONE == (err = legacy_dbg_set_chain(DC_CPU0)))
366 
        if (APP_ERR_NONE == (err = legacy_dbg_command(0x6, adr, 4)))
367 
          if (APP_ERR_NONE == (err = legacy_dbg_go((unsigned char*)data, 4, 1)))
368 
            *data = ntohl(*data);
369 
    }
370 
  cable_flush();
371 
  pthread_mutex_unlock(&dbg_access_mutex);
372 
  debug("dbg_cpu_read(), addr 0x%X, data[0] = 0x%X\n", adr, data[0]);
373 
  return err;
374 
}
375 
 
376 
/* read multiple registers from cpu0.  This is assumed to be an OR32 CPU, with 32-bit regs. */
377 50 nyawn 
int dbg_cpu0_read_block(uint32_t adr, uint32_t *data, int count) {
378 21 nyawn 
  int err;
379 
 
380 
  if(DEBUG_HARDWARE == DBG_HW_ADVANCED)
381 
    {
382 29 nyawn 
      pthread_mutex_lock(&dbg_access_mutex);
383 21 nyawn 
      if ((err = adbg_select_module(DC_CPU0)))
384 
        {
385 
          cable_flush();
386 
          pthread_mutex_unlock(&dbg_access_mutex);
387 
          return err;
388 
        }
389 
      err = adbg_wb_burst_read(4, count, adr, (void *) data); // All CPU register reads / writes are bursts
390 29 nyawn 
      cable_flush();
391 
      pthread_mutex_unlock(&dbg_access_mutex);
392 21 nyawn 
    }
393 
  else if(DEBUG_HARDWARE == DBG_HW_LEGACY)
394 
    {
395 
      int i;
396 
      unsigned long readaddr = adr;
397 
      err = APP_ERR_NONE;
398 
      for(i = 0; i < count; i++) {
399 
        err |= dbg_cpu0_read(readaddr++, &data[i]);
400 14 nyawn 
      }
401 21 nyawn 
    }
402 29 nyawn 
 
403 21 nyawn 
  debug("dbg_cpu_read_block(), addr 0x%X, count %i, data[0] = 0x%X\n", adr, count, data[0]);
404 
  return err;
405 
}
406 
 
407 
/* write a cpu register to cpu0.  This is assumed to be an OR32 CPU, with 32-bit regs. */
408 50 nyawn 
int dbg_cpu0_write(uint32_t adr, uint32_t data) {
409 21 nyawn 
  int err;
410 
  pthread_mutex_lock(&dbg_access_mutex);
411 
 
412 
  if(DEBUG_HARDWARE == DBG_HW_ADVANCED)
413 
    {
414 
      if ((err = adbg_select_module(DC_CPU0)))
415 
        {
416 
          cable_flush();
417 
          pthread_mutex_unlock(&dbg_access_mutex);
418 
          return err;
419 
        }
420 
      err = adbg_wb_burst_write((void *)&data, 4, 1, adr);
421 
    }
422 
  else if(DEBUG_HARDWARE == DBG_HW_LEGACY)
423 
    {
424 
      data = ntohl(data);
425 
      if (APP_ERR_NONE == (err = legacy_dbg_set_chain(DC_CPU0)))
426 
        if (APP_ERR_NONE == (err = legacy_dbg_command(0x2, adr, 4)))
427 
          err = legacy_dbg_go((unsigned char*)&data, 4, 0);
428 
    }
429 
  debug("cpu0_write, adr 0x%X, data 0x%X, ret %i\n", adr, data, err);
430 
  cable_flush();
431 
  pthread_mutex_unlock(&dbg_access_mutex);
432 
  return err;
433 
}
434 
 
435 
/* write multiple cpu registers to cpu0.  This is assumed to be an OR32 CPU, with 32-bit regs. */
436 50 nyawn 
int dbg_cpu0_write_block(uint32_t adr, uint32_t *data, int count) {
437 21 nyawn 
  int err;
438 29 nyawn 
 
439 21 nyawn 
  if(DEBUG_HARDWARE == DBG_HW_ADVANCED)
440 
    {
441 29 nyawn 
      pthread_mutex_lock(&dbg_access_mutex);
442 21 nyawn 
      if ((err = adbg_select_module(DC_CPU0)))
443 
        {
444 
          cable_flush();
445 
          pthread_mutex_unlock(&dbg_access_mutex);
446 
          return err;
447 
        }
448 
      err = adbg_wb_burst_write((void *)data, 4, count, adr);
449 29 nyawn 
      cable_flush();
450 
      pthread_mutex_unlock(&dbg_access_mutex);
451 21 nyawn 
    }
452 
  else if(DEBUG_HARDWARE == DBG_HW_LEGACY)
453 
    {
454 
      int i;
455 
      unsigned long writeaddr = adr;
456 
      err = APP_ERR_NONE;
457 
      for(i = 0; i < count; i++) {
458 
        err |= dbg_cpu0_write(writeaddr++, data[i]);
459 
      }
460 
    }
461 
  debug("cpu0_write_block, adr 0x%X, data[0] 0x%X, count %i, ret %i\n", adr, data[0], count, err);
462 29 nyawn 
 
463 21 nyawn 
  return err;
464 
}
465 
 
466 
/* write a debug unit cpu module register
467 
 * Since OR32 debug module has only 1 register,
468 
 * adr is ignored (for now) */
469 50 nyawn 
int dbg_cpu0_write_ctrl(uint32_t adr, uint8_t data) {
470 21 nyawn 
  int err = APP_ERR_NONE;
471 
  uint32_t dataword = data;
472 
  pthread_mutex_lock(&dbg_access_mutex);
473 
 
474 
  if(DEBUG_HARDWARE == DBG_HW_ADVANCED)
475 
    {
476 
      if ((err = adbg_select_module(DC_CPU0))) {
477 
        printf("Failed to set chain to 0x%X\n", DC_CPU0);
478 
        cable_flush();
479 
        pthread_mutex_unlock(&dbg_access_mutex);
480 
        return err;
481 
      }
482 
      if((err = adbg_ctrl_write(DBG_CPU0_REG_STATUS, &dataword, 2))) {
483 
        printf("Failed to write chain to 0x%X control reg 0x%X\n", DC_CPU0,DBG_CPU0_REG_STATUS );  // Only 2 bits: Reset, Stall
484 
        cable_flush();
485 
        pthread_mutex_unlock(&dbg_access_mutex);
486 
        return err;
487 
      }
488 
    }
489 
  else if(DEBUG_HARDWARE == DBG_HW_LEGACY)
490 
    {
491 
      if (APP_ERR_NONE == (err = legacy_dbg_set_chain(DC_CPU0)))
492 
        err = legacy_dbg_ctrl(data & 2, data &1);
493 
    }
494 
  debug("cpu0_write_ctrl(): set reg to 0x%X\n", data);
495 
  cable_flush();
496 
  pthread_mutex_unlock(&dbg_access_mutex);
497 
  return err;
498 
}
499 
 
500 
 
501 
/* read a register from cpu module of the debug unit.
502 
 * Currently, there is only 1 register, so we do not need to select it, adr is ignored
503 
 */
504 50 nyawn 
int dbg_cpu0_read_ctrl(uint32_t adr, uint8_t *data) {
505 21 nyawn 
  int err = APP_ERR_NONE;
506 
  uint32_t dataword;
507 
  pthread_mutex_lock(&dbg_access_mutex);
508 
 
509 
  // reset is bit 1, stall is bit 0 in *data
510 
  if(DEBUG_HARDWARE == DBG_HW_ADVANCED)
511 
    {
512 
      if ((err = adbg_select_module(DC_CPU0))) {
513 
        printf("Failed to set chain to 0x%X\n", DC_CPU0);
514 
        cable_flush();
515 
        pthread_mutex_unlock(&dbg_access_mutex);
516 
        return err;
517 
      }
518 
      if ((err = adbg_ctrl_read(DBG_CPU0_REG_STATUS, &dataword, 2))) {
519 
        printf("Failed to read chain 0x%X control reg 0x%X\n", DC_CPU0, DBG_CPU0_REG_STATUS);
520 
        cable_flush();
521 
        pthread_mutex_unlock(&dbg_access_mutex);
522 
        return err;
523 
      }
524 
      *data = dataword;
525 
    }
526 
  else if(DEBUG_HARDWARE == DBG_HW_LEGACY)
527 
    {
528 
      int r, s;
529 
      if (APP_ERR_NONE == (err = legacy_dbg_set_chain(DC_CPU0)))
530 
        err = legacy_dbg_ctrl_read(&r, &s);
531 
      *data = (r << 1) | s;
532 
      debug("api cpu0 read ctrl: r = %i, s = %i, data = %i\n", r, s, *data);
533 
    }
534 
  cable_flush();
535 
  pthread_mutex_unlock(&dbg_access_mutex);
536 
  return err;
537 
}
538 
 
539 
// CPU1 Functions.  Note that 2 CPUs are not currently supported by GDB, so these are never actually
540 
// called from the GDB interface.  They are included for completeness and future use.
541 
// read a register from cpu1
542 50 nyawn 
int dbg_cpu1_read(uint32_t adr, uint32_t *data)
543 21 nyawn 
 {
544 
  int err;
545 
  pthread_mutex_lock(&dbg_access_mutex);
546 
 
547 
  if(DEBUG_HARDWARE == DBG_HW_ADVANCED)
548 
    {
549 
      if ((err = adbg_select_module(DC_CPU1)))
550 
        {
551 
          cable_flush();
552 
          pthread_mutex_unlock(&dbg_access_mutex);
553 
          return err;
554 
        }
555 
      err = adbg_wb_burst_read(4, 1, adr, (void *) data); // All CPU register reads / writes are bursts
556 
    }
557 
  else if(DEBUG_HARDWARE == DBG_HW_LEGACY)
558 
    {
559 
      if (APP_ERR_NONE == (err = legacy_dbg_set_chain(DC_CPU1)))
560 
        if (APP_ERR_NONE == (err = legacy_dbg_command(0x6, adr, 4)))
561 
          err = legacy_dbg_go((unsigned char*)data, 4, 1);
562 
      *data = ntohl(*data);
563 
    }
564 
  cable_flush();
565 
  pthread_mutex_unlock(&dbg_access_mutex);
566 
  return err;
567 
}
568 
 
569 
 
570 
// write a cpu register
571 50 nyawn 
int dbg_cpu1_write(uint32_t adr, uint32_t data)
572 21 nyawn 
{
573 
  int err;
574 
  pthread_mutex_lock(&dbg_access_mutex);
575 
 
576 
  if(DEBUG_HARDWARE == DBG_HW_ADVANCED)
577 
    {
578 
  if ((err = adbg_select_module(DC_CPU0)))
579 
    {
580 
      cable_flush();
581 
      pthread_mutex_unlock(&dbg_access_mutex);
582 
      return err;
583 
    }
584 
  err = adbg_wb_burst_write((void *)&data, 4, 1, adr);
585 
    }
586 
  else if(DEBUG_HARDWARE == DBG_HW_LEGACY)
587 
    {
588 
      data = ntohl(data);
589 
      if (APP_ERR_NONE == (err = legacy_dbg_set_chain(DC_CPU1)))
590 
        if (APP_ERR_NONE == (err = legacy_dbg_command(0x2, adr, 4)))
591 
          err = legacy_dbg_go((unsigned char*)&data, 4, 0);
592 
    }
593 
  cable_flush();
594 
  pthread_mutex_unlock(&dbg_access_mutex);
595 
  return err;
596 
}
597 
 
598 
 
599 
// write a debug unit cpu module register
600 50 nyawn 
int dbg_cpu1_write_ctrl(uint32_t adr, uint8_t data) {
601 21 nyawn 
   int err;
602 
  uint32_t dataword = data;
603 
  pthread_mutex_lock(&dbg_access_mutex);
604 
 
605 
  if(DEBUG_HARDWARE == DBG_HW_ADVANCED)
606 
    {
607 
      if ((err = adbg_select_module(DC_CPU1))) {
608 
        printf("Failed to set chain to 0x%X\n", DC_CPU1);
609 
        cable_flush();
610 
        pthread_mutex_unlock(&dbg_access_mutex);
611 
        return err;
612 
      }
613 
      if((err = adbg_ctrl_write(DBG_CPU1_REG_STATUS, &dataword, 2))) {
614 
        printf("Failed to write chain to 0x%X control reg 0x%X\n", DC_CPU1,DBG_CPU0_REG_STATUS );  // Only 2 bits: Reset, Stall
615 
        cable_flush();
616 
        pthread_mutex_unlock(&dbg_access_mutex);
617 
        return err;
618 
      }
619 
    }
620 
  else if(DEBUG_HARDWARE == DBG_HW_LEGACY)
621 
    {
622 
      if (APP_ERR_NONE == (err = legacy_dbg_set_chain(DC_CPU1)))
623 
        err = legacy_dbg_ctrl(data & 2, data & 1);
624 
    }
625 
  cable_flush();
626 
  pthread_mutex_unlock(&dbg_access_mutex);
627 
  return err;
628 
}
629 
 
630 
 
631 
// read a debug unit cpu module register
632 50 nyawn 
int dbg_cpu1_read_ctrl(uint32_t adr, uint8_t *data) {
633 21 nyawn 
  int err;
634 
  uint32_t dataword;
635 
  pthread_mutex_lock(&dbg_access_mutex);
636 
 
637 
  // reset is bit 1, stall is bit 0 in *data
638 
 
639 
  if(DEBUG_HARDWARE == DBG_HW_ADVANCED)
640 
    {
641 
      if ((err = adbg_select_module(DC_CPU1))) {
642 
        printf("Failed to set chain to 0x%X\n", DC_CPU1);
643 
        cable_flush();
644 
        pthread_mutex_unlock(&dbg_access_mutex);
645 
        return err;
646 
      }
647 
      if ((err = adbg_ctrl_read(DBG_CPU1_REG_STATUS, &dataword, 2))) {
648 
        printf("Failed to read chain 0x%X control reg 0x%X\n", DC_CPU0, DBG_CPU1_REG_STATUS);
649 
        cable_flush();
650 
        pthread_mutex_unlock(&dbg_access_mutex);
651 
        return err;
652 
      }
653 
     *data = dataword;
654 
    }
655 
  else if(DEBUG_HARDWARE == DBG_HW_LEGACY)
656 
    {
657 
      int r, s;
658 
      if (APP_ERR_NONE == (err = legacy_dbg_set_chain(DC_CPU1)))
659 
        err = legacy_dbg_ctrl_read(&r, &s);
660 
      *data = (r << 1) | s;
661 
    }
662 
  cable_flush();
663 
  pthread_mutex_unlock(&dbg_access_mutex);
664 
  return err;
665 
}
666 
 
667 50 nyawn 
int dbg_serial_sndrcv(unsigned int *bytes_to_send, const uint8_t *data_to_send, unsigned int *bytes_received, uint8_t *data_received) {
668 42 nyawn 
  int err;
669 21 nyawn 
 
670 42 nyawn 
  pthread_mutex_lock(&dbg_access_mutex);
671 21 nyawn 
 
672 42 nyawn 
  if ((err = adbg_select_module(DC_JSP))) {
673 
    printf("Failed to set chain to 0x%X\n", DC_JSP);
674 
    cable_flush();
675 
    pthread_mutex_unlock(&dbg_access_mutex);
676 
    return err;
677 
  }
678 
 
679 
  err = adbg_jsp_transact(bytes_to_send, data_to_send, bytes_received, data_received);
680 
 
681 
  cable_flush();
682 
  pthread_mutex_unlock(&dbg_access_mutex);
683 
 
684 
  return err;
685 
}
686 
 
687 
 

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