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1 195 sybreon 
/* $Id: fasm_fifo.v,v 1.2 2008/06/05 21:07:13 sybreon Exp $
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**
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** FASM MEMORY LIBRARY
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** Copyright (C) 2004-2008 Shawn Tan <shawn.tan@aeste.net>
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** All rights reserved.
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**
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** FASM is free software: you can redistribute it and/or modify it
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** under the terms of the GNU Lesser General Public License as
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** published by the Free Software Foundation, either version 3 of the
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** License, or (at your option) any later version.
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**
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** FASM is distributed in the hope that it will be useful, but WITHOUT
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** ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
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** or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU Lesser General
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** Public License for more details.
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**
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** You should have received a copy of the GNU Lesser General Public
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** License along with FASM. If not, see <http:**www.gnu.org/licenses/>.
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*/
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/*
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 * SMALL INTERNAL BUFFER (FIFO)
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 * Synthesis proven on:
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 * - Xilinx ISE
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 * - Altera Quartus (>=8.0)
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 */
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module fasm_fifo (/*AUTOARG*/
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   // Outputs
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   dat_o, rok_o, wok_o,
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   // Inputs
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   dat_i, rde_i, wre_i, clr_i, rst_i, ena_i, clk_i
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   );
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   parameter AW = 4; // fifo depth
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   parameter DW = 32; // fifo width
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   output [DW-1:0] dat_o;
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   output          rok_o, // empty signal
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                   wok_o; // full signal
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   input [DW-1:0]  dat_i;
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   input           rde_i,
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                   wre_i;
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   input           clr_i,
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                   rst_i,
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                   ena_i,
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                   clk_i; // global clock
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   /*AUTOREG*/
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   // Beginning of automatic regs (for this module's undeclared outputs)
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   reg                  rok_o;
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   reg                  wok_o;
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   // End of automatics
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   reg [AW:1]   rRADR,
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                        rWADR;
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   wire                 wWRE = wre_i & wok_o;
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   wire                 wRDE = rde_i & rok_o;
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   //wire [AW:1]                wRNXT = {~^rRADR[2:1],rRADR[AW:2]};
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   //wire [AW:1]                wWNXT = {~^rWADR[2:1],rWADR[AW:2]};
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   wire [AW:1]          wRNXT = rRADR + 1;
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   wire [AW:1]          wWNXT = rWADR + 1;
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   always @(posedge clk_i)
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     if (rst_i | clr_i) begin
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        rok_o <= 1'b0;
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        wok_o <= 1'b1;
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        /*AUTORESET*/
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        // Beginning of autoreset for uninitialized flops
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        rRADR <= {(1+(AW)-(1)){1'b0}};
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        rWADR <= {(1+(AW)-(1)){1'b0}};
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        // End of automatics
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     end else if (ena_i) begin
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        if (wWRE) rWADR <= #1 wWNXT;
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        if (wRDE) rRADR <= #1 wRNXT;
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        if (wWRE ^ wRDE) begin
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           if (wWRE) begin
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              wok_o <= #1 (wWNXT != rRADR); // FIXME: use XOR
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              rok_o <= #1 1'b1;
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           end else begin
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              wok_o <= #1 1'b1;
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              rok_o <= #1 (wRNXT != rWADR);
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           end
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        end
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     end // if (ena_i)
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   /* fasm_tparam AUTO_TEMPLATE
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    (
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    .AW(AW),
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    .DW(DW),
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    .clk_i(clk_i),
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    .rst_i(),
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    .stb_i(),
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    .wre_i(),
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    .dat_i(),
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    .adr_i(rRADR),
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    .dat_o(dat_o),
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    .xclk_i(clk_i),
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    .xrst_i(),
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    .xstb_i(),
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    .xwre_i(wWRE),
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    .xadr_i(rWADR),
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    .xdat_i(dat_i),
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    .xdat_o(),
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    ); */
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   fasm_tparam
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     #(/*AUTOINSTPARAM*/
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       // Parameters
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       .AW                              (AW),                    // Templated
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       .DW                              (DW))                    // Templated
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   fiforam0
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     (/*AUTOINST*/
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      // Outputs
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      .dat_o                            (dat_o),                 // Templated
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      .xdat_o                           (),                      // Templated
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      // Inputs
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      .dat_i                            (),                      // Templated
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      .adr_i                            (rRADR),                 // Templated
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      .wre_i                            (),                      // Templated
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      .stb_i                            (),                      // Templated
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      .rst_i                            (),                      // Templated
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      .clk_i                            (clk_i),                 // Templated
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      .xdat_i                           (dat_i),                 // Templated
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      .xadr_i                           (rWADR),                 // Templated
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      .xwre_i                           (wWRE),                  // Templated
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      .xstb_i                           (),                      // Templated
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      .xrst_i                           (),                      // Templated
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      .xclk_i                           (clk_i));                // Templated
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   // ### SIMULATION ONLY ###
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   // synopsys translate_on
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   initial begin
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      // This depends on target technology. All regular FPGAs have a
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      // 16x1 dual port asynchronous RAM block.
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      if (AW > 4) $display("Warning: FIFO too large!");
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      if (AW < 2) $display("Warning: FIFO too small!");
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   end
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   // synopsys translate_off
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endmodule // fasm_fifo

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