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[/] [aes-128_pipelined_encryption/] [trunk/] [rtl/] [AddRoundKey.v] - Blame information for rev 2

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Line No. Rev Author Line
1 2 Amr_Salah
/*
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Project        : AES
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Standard doc.  : FIPS 197
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Module name    : AddRoundKey block
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Dependancy     :
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Design doc.    :
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References     :
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Description    : This module is used for xoring data and round  key
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Owner          : Amr Salah
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*/
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`timescale 1 ns/1 ps
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module AddRoundKey
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#
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(
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parameter DATA_W = 128            //data width
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)
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(
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input clk,                        //system clock
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input reset,                      //asynch active low reset
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input data_valid_in,              //data valid signal
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input key_valid_in,               //key valid signal  
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input [DATA_W-1:0] data_in,       //input data
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input [DATA_W-1:0] round_key,     //input round key
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output reg valid_out,             //output valid signal
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output reg [DATA_W-1:0] data_out  //output data
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)
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;
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always@(posedge clk or negedge reset)
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if(!reset)begin
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    data_out <= 'b0;
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    valid_out <= 1'b0;
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end
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else begin
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    if(data_valid_in && key_valid_in) begin
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    data_out <=  data_in ^ round_key;      //xoring data and round key       
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    end
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    valid_out <=  data_valid_in & key_valid_in;
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end
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endmodule

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