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[/] [aes-encryption/] [trunk/] [aes_5cycle_2stage/] [test_bench_top.v] - Blame information for rev 2

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/////////////////////////////////////////////////////////////////////
////                                                             ////
////     Test Bench for 5 cycles - 2 stage AES128-ENC            ////
////                                                             ////
////                                                             ////
////  Author: Tariq Bashir Ahmad                                 ////
////          tariq.bashir@gmail.com                             ////
////                                                             ////
////                                                             ////
/////////////////////////////////////////////////////////////////////
////                                                             ////
//// Copyright (C) 2010          Tariq Bashir Ahmad              ////   
////                         http://www.ecs.umass.edu/~tbashir   ////
////                                                             ////
////                                                             ////
//// This source file may be used and distributed without        ////
//// restriction provided that this copyright statement is not   ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer.////
////                                                             ////
////     THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY     ////
//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED   ////
//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS   ////
//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR      ////
//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,         ////
//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES    ////
//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE   ////
//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR        ////
//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF  ////
//// LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT  ////
//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT  ////
//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE         ////
//// POSSIBILITY OF SUCH DAMAGE.                                 ////
////                                                             ////
/////////////////////////////////////////////////////////////////////
 
 
`timescale 1 ns/1 ps
 
module test;
 
reg             clk;
reg             rst;
reg      aes_en;
reg             kld;
reg     [127:0]  key;
reg     [127:0]  text_in;
 
wire    [127:0]  text_out;
wire            done;
 
 
 
initial
   begin
 
        clk <=  0;
        aes_en =  1;
        repeat(1) @(posedge clk);
        rst =  1;
        repeat(200) @(posedge clk);
        rst =  0;
//      kld = 0;
        repeat(1) @(posedge clk);
        kld             =  1;
        key             =  128'h0;
        text_in  =  128'h00112233445566778899aabbccddeeff;
        repeat(1) @(posedge clk);            //you need 2 cycles after loading the key and input
        kld  =  0;
        repeat(8) @(posedge clk);
        aes_en =  0;
        end
 
 
/*
initial
   begin
        aes_en = 1;
        kld = 0;
        clk = 0;
        rst = 1;
        key = 128'b0;
        text_in  = 128'h00112233445566778899aabbccddeeff;
        repeat(2) @(posedge clk);
        rst = 0;
        end
*/
 
 
aes_cipher_top uut(
        .clk(           clk             ),
        .rst(           rst             ),
        .ld(            kld             ),
        .done(          done            ),
        .key(           key             ),
        .text_in(       text_in         ),
        .text_out(      text_out        ),
        .aes_en(aes_en)
        );
 
/*
initial
begin
        #50 kld = 1;
end
 
initial
        #90 kld = 0;
*/
 
initial
        forever #10 clk = ~clk;
 
initial
        #4300 $stop;
 
initial
                $monitor($time," TEXT_OUT is %h, DONE is %b\n",text_out,done);
 
endmodule
 
 

Line No.	Rev	Author	Line
1	2	tariq786	`/////////////////////////////////////////////////////////////////////`
2			`//// ////`
3			`//// Test Bench for 5 cycles - 2 stage AES128-ENC ////`
4			`//// ////`
5			`//// ////`
6			`//// Author: Tariq Bashir Ahmad ////`
7			`//// tariq.bashir@gmail.com ////`
8			`//// ////`
9			`//// ////`
10			`/////////////////////////////////////////////////////////////////////`
11			`//// ////`
12			`//// Copyright (C) 2010 Tariq Bashir Ahmad ////`
13			`//// http://www.ecs.umass.edu/~tbashir ////`
14			`//// ////`
15			`//// ////`
16			`//// This source file may be used and distributed without ////`
17			`//// restriction provided that this copyright statement is not ////`
18			`//// removed from the file and that any derivative work contains ////`
19			`//// the original copyright notice and the associated disclaimer.////`
20			`//// ////`
21			//// THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY ////
22			`//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED ////`
23			`//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS ////`
24			`//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR ////`
25			`//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, ////`
26			`//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ////`
27			`//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE ////`
28			`//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR ////`
29			`//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF ////`
30			`//// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ////`
31			`//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT ////`
32			`//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ////`
33			`//// POSSIBILITY OF SUCH DAMAGE. ////`
34			`//// ////`
35			`/////////////////////////////////////////////////////////////////////`
36
37
38			`timescale 1 ns/1 ps
39
40			`module test;`
41
42			`reg clk;`
43			`reg rst;`
44			`reg aes_en;`
45			`reg kld;`
46			`reg [127:0] key;`
47			`reg [127:0] text_in;`
48
49			`wire [127:0] text_out;`
50			`wire done;`
51
52
53
54			`initial`
55			`begin`
56
57			`clk <= 0;`
58			`aes_en = 1;`
59			`repeat(1) @(posedge clk);`
60			`rst = 1;`
61			`repeat(200) @(posedge clk);`
62			`rst = 0;`
63			`// kld = 0;`
64			`repeat(1) @(posedge clk);`
65			`kld = 1;`
66			`key = 128'h0;`
67			`text_in = 128'h00112233445566778899aabbccddeeff;`
68			`repeat(1) @(posedge clk); //you need 2 cycles after loading the key and input`
69			`kld = 0;`
70			`repeat(8) @(posedge clk);`
71			`aes_en = 0;`
72			`end`
73
74
75			`/*`
76			`initial`
77			`begin`
78			`aes_en = 1;`
79			`kld = 0;`
80			`clk = 0;`
81			`rst = 1;`
82			`key = 128'b0;`
83			`text_in = 128'h00112233445566778899aabbccddeeff;`
84			`repeat(2) @(posedge clk);`
85			`rst = 0;`
86			`end`
87			`*/`
88
89
90			`aes_cipher_top uut(`
91			`.clk( clk ),`
92			`.rst( rst ),`
93			`.ld( kld ),`
94			`.done( done ),`
95			`.key( key ),`
96			`.text_in( text_in ),`
97			`.text_out( text_out ),`
98			`.aes_en(aes_en)`
99			`);`
100
101			`/*`
102			`initial`
103			`begin`
104			`#50 kld = 1;`
105			`end`
106
107			`initial`
108			`#90 kld = 0;`
109			`*/`
110
111			`initial`
112			`forever #10 clk = ~clk;`
113
114			`initial`
115			`#4300 $stop;`
116
117			`initial`
118			`$monitor($time," TEXT_OUT is %h, DONE is %b\n",text_out,done);`
119
120			`endmodule`
121
122

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[/] [aes-encryption/] [trunk/] [aes_5cycle_2stage/] [test_bench_top.v] - Blame information for rev 2