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[/] [aes3rx/] [trunk/] [rtl/] [vhdl/] [aes3rx.vhd] - Blame information for rev 7

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----------------------------------------------------------------------------------
-- Company:  Czech Television
-- Engineer: Petr Nohavica
-- 
-- Create Date:    09:02:45 05/09/2009 
-- Module Name:    aes3rx - Behavioral 
-- Project Name:   AES3 minimalistic receiver
-- Target Devices: Spartan 3
-- Tool versions:  ISE 10.1
--
-- Revision: 
-- Revision 0.01 - File Created
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
 
entity aes3rx is
        generic (
                reg_width : integer := 5
        );
        port (
                clk     : in  std_logic; -- master clock
                aes3    : in  std_logic; -- input 
                reset : in  std_logic; -- synchronous reset
                --ch_a  : out std_logic_vector(27 downto 0) := (others => '0'); -- channel A output register
                --ch_b  : out std_logic_vector(27 downto 0) := (others => '0'); -- channel B output register
                --ch_a_w: out std_logic := '0'; -- channel A reg has new data (active high for one clk period)
                --ch_b_w: out std_logic := '0'; -- channel B reg has new data (active high for one clk period)
                sdata : out std_logic := '0';
                sclk  : out std_logic := '0';
                bsync   : out std_logic := '0'; -- block start (active high for one clk period)
                fsync   : out std_logic := '0';
                active: out std_logic := '0' -- receiver has valid data on its outputs
        );
end aes3rx;
 
architecture Behavioral of aes3rx is
        constant X_PREAMBLE             : std_logic_vector(7 downto 0) := "01000111";
        constant Y_PREAMBLE             : std_logic_vector(7 downto 0) := "00100111";
        constant Z_PREAMBLE             : std_logic_vector(7 downto 0) := "00010111";
        signal aes3_sync                        : std_logic_vector(3 downto 0) := (others => '0'); -- input shift reg for double sampling, change detection and input delaying
        signal change                           : std_logic := '0'; -- signal signifying a change on the input
        signal aes3_clk                 : std_logic := '0'; -- recovered clock signal (actually a stream of pulses on supposed clock edges for implementation on single edge driven FFs)
        signal decoder_shift            : std_logic_vector(7 downto 0) := (others => '0');
        signal align_counter            : std_logic := '0';
        signal clk_counter              : std_logic_vector(reg_width - 1 downto 0) := (others => '0'); -- counter for aes3 clock regeneration
        signal dur_counter              : std_logic_vector(reg_width + 1 downto 0) := (others => '0'); -- counts durration (in clk periods) of current input invariant state (i.e. from "edge to edge")
        signal upd_timer                        : std_logic_vector(5 downto 0) := (others => '0'); -- timer counting input changes
        signal reg_reset                        : std_logic := '0'; -- resets reg_shortest on upd_timer overflow
        signal reg_shortest             : std_logic_vector(reg_width - 1 downto 0) := (others => '1'); -- stores durration of shortest measured input invariant state
        signal reg_shortest_ref : std_logic_vector(reg_width - 1 downto 0) := (others => '1'); -- copied from reg_shortest on update counter overflows, serves as reference for aes3 clock regeneration
 
        signal sdata_int                        : std_logic := '0';
        signal bsync_int                        : std_logic := '0';
        signal fsync_int                        : std_logic := '0';
        signal sync_ok                          : std_logic := '0';
        signal active_int                       : std_logic := '0';
        signal timeout                          : std_logic := '1';
begin
 
        ------------------------------------------
        -- input_shift_reg_proc
        -- Carries out input double sampling in 
        -- order to avoid metastable states on FFs
        -- and creation of delayed signals for
        -- change detector (1 clk period) and 
        -- decoder (2 clk periods)
        ------------------------------------------
        input_shift_reg_proc: process (clk)
        begin
                if clk'event and clk = '1' then
                        if reset = '1' then
                                aes3_sync <= (others => '0');
                        else
                                aes3_sync <= aes3 & aes3_sync(3 downto 1); -- synthetizes  shift reg
                        end if;
                end if;
        end process;
 
        ------------------------------------------
        -- change_detect_proc
        -- Detects edge on sampled input in the 
        -- way of comparsion of delayed input 
        -- and current state on XOR gate
        ------------------------------------------      
        change_detect_proc: process (clk)
        begin
                if clk'event and clk = '1' then
                        if reset = '1' then
                                change <= '0';
                        else
                                change <= '0';
                                if aes3_sync(2) /= aes3_sync(1) then
                                        change <= '1';
                                end if;
                        end if;
                end if;
        end process;
 
        shortest_pulse_dur_cnt_proc: process (clk)
        begin
                if clk'event and clk = '1' then
                        if reset = '1' then
                                reg_shortest <= (others => '1');
                                dur_counter <= (others => '0');
                        else
                                if change = '1' then
                                        timeout <= '0';
                                        if dur_counter < reg_shortest then
                                                reg_shortest <= dur_counter(reg_width - 1 downto 0);
                                        end if;
                                        dur_counter <= (others => '0');
                                elsif dur_counter = 2**(reg_width + 2) - 1 then
                                        timeout <= '1';
                                else
                                        dur_counter <= dur_counter + 1;
                                end if;
                                if reg_reset = '1' then
                                        reg_shortest <= (others => '1');
                                end if;
                        end if;
                end if;
        end process;
 
        register_update_timer_proc: process (clk)
        begin
                if clk'event and clk = '1' then
                        reg_reset <= '0';
                        if reset = '1' then
                                reg_shortest_ref <= (others => '1');
                                upd_timer <= (others => '0');
                        else
                                if change = '1' then
                                        if upd_timer = 63 then
                                                reg_shortest_ref <= reg_shortest;
                                                reg_reset <= '1';
                                        end if;
                                        upd_timer <= upd_timer + 1;
                                end if;
                        end if;
                end if;
        end process;
 
        aes3_clk_regen_proc: process (clk)
        begin
                if clk'event and clk = '1' then
                        if reset = '1' then
                                clk_counter <= (others => '0');
                                aes3_clk <= '0';
                        else
                                clk_counter <= clk_counter - 1;
                                aes3_clk <= '0';
                                if change = '1' then
                                        clk_counter <= '0' & reg_shortest_ref(reg_width - 1 downto 1);
                                elsif clk_counter = 0 then
                                        clk_counter <= reg_shortest_ref;
                                        aes3_clk <= '1';
                                end if;
                        end if;
                end if;
        end process;
 
        decoder_shift_reg_proc: process (clk)
        begin
                if clk'event and clk = '1' then
                        if reset = '1' then
                                decoder_shift <= (others => '0');
                        elsif aes3_clk = '1' then
                                decoder_shift <= aes3_sync(0) & decoder_shift(7  downto 1);
                        end if;
                end if;
        end process;
 
        decoder_proc: process (clk)
        begin
                if clk'event and clk = '1' then
                        if timeout = '1' then
                                sync_ok <= '0';
                        end if;
                        if aes3_clk = '1' then
                                align_counter <= not align_counter;
                                if decoder_shift = X_PREAMBLE or decoder_shift = not X_PREAMBLE then
                                        fsync_int <= '1';
                                        bsync_int <= '0';
                                        sync_ok <= '1';
                                        align_counter <= '0';
                                elsif decoder_shift = Y_PREAMBLE or decoder_shift = not Y_PREAMBLE then
                                        fsync_int <= '0';
                                        bsync_int <= '0';
                                        sync_ok <= '1';
                                        align_counter <= '0';
                                elsif decoder_shift = Z_PREAMBLE or decoder_shift = not Z_PREAMBLE then
                                        fsync_int <= '1';
                                        bsync_int <= '1';
                                        sync_ok <= '1';
                                        align_counter <= '0';
                                end if;
                                if align_counter = '1' then
                                        if decoder_shift(1) = decoder_shift(0) then
                                                sdata_int <= '0';
                                        else
                                                sdata_int <= '1';
                                        end if;
                                end if;
                        end if;
                end if;
        end process;
 
        active_int <= sync_ok and not timeout;
 
        sclk <= align_counter and active_int;
        sdata <= sdata_int and active_int;
        fsync <= fsync_int and active_int;
        bsync <= bsync_int and active_int;
        active <= active_int;
 
 
end Behavioral;
 

Line No.	Rev	Author	Line
1	7	nohous	`----------------------------------------------------------------------------------`
2			`-- Company: Czech Television`
3			`-- Engineer: Petr Nohavica`
4			`--`
5			`-- Create Date: 09:02:45 05/09/2009`
6			`-- Module Name: aes3rx - Behavioral`
7			`-- Project Name: AES3 minimalistic receiver`
8			`-- Target Devices: Spartan 3`
9			`-- Tool versions: ISE 10.1`
10			`--`
11			`-- Revision:`
12			`-- Revision 0.01 - File Created`
13			`----------------------------------------------------------------------------------`
14			`library IEEE;`
15			`use IEEE.STD_LOGIC_1164.ALL;`
16			`use IEEE.STD_LOGIC_ARITH.ALL;`
17			`use IEEE.STD_LOGIC_UNSIGNED.ALL;`
18
19			`entity aes3rx is`
20			`generic (`
21			`reg_width : integer := 5`
22			`);`
23			`port (`
24			`clk : in std_logic; -- master clock`
25			`aes3 : in std_logic; -- input`
26			`reset : in std_logic; -- synchronous reset`
27			`--ch_a : out std_logic_vector(27 downto 0) := (others => '0'); -- channel A output register`
28			`--ch_b : out std_logic_vector(27 downto 0) := (others => '0'); -- channel B output register`
29			`--ch_a_w: out std_logic := '0'; -- channel A reg has new data (active high for one clk period)`
30	3	nohous	`--ch_b_w: out std_logic := '0'; -- channel B reg has new data (active high for one clk period)`
31			`sdata : out std_logic := '0';`
32	7	nohous	`sclk : out std_logic := '0';`
33	3	nohous	`bsync : out std_logic := '0'; -- block start (active high for one clk period)`
34	7	nohous	`fsync : out std_logic := '0';`
35			`active: out std_logic := '0' -- receiver has valid data on its outputs`
36			`);`
37			`end aes3rx;`
38
39	3	nohous	`architecture Behavioral of aes3rx is`
40			`constant X_PREAMBLE : std_logic_vector(7 downto 0) := "01000111";`
41			`constant Y_PREAMBLE : std_logic_vector(7 downto 0) := "00100111";`
42	7	nohous	`constant Z_PREAMBLE : std_logic_vector(7 downto 0) := "00010111";`
43			`signal aes3_sync : std_logic_vector(3 downto 0) := (others => '0'); -- input shift reg for double sampling, change detection and input delaying`
44			`signal change : std_logic := '0'; -- signal signifying a change on the input`
45	3	nohous	`signal aes3_clk : std_logic := '0'; -- recovered clock signal (actually a stream of pulses on supposed clock edges for implementation on single edge driven FFs)`
46			`signal decoder_shift : std_logic_vector(7 downto 0) := (others => '0');`
47	7	nohous	`signal align_counter : std_logic := '0';`
48			`signal clk_counter : std_logic_vector(reg_width - 1 downto 0) := (others => '0'); -- counter for aes3 clock regeneration`
49			`signal dur_counter : std_logic_vector(reg_width + 1 downto 0) := (others => '0'); -- counts durration (in clk periods) of current input invariant state (i.e. from "edge to edge")`
50			`signal upd_timer : std_logic_vector(5 downto 0) := (others => '0'); -- timer counting input changes`
51			`signal reg_reset : std_logic := '0'; -- resets reg_shortest on upd_timer overflow`
52			`signal reg_shortest : std_logic_vector(reg_width - 1 downto 0) := (others => '1'); -- stores durration of shortest measured input invariant state`
53	3	nohous	`signal reg_shortest_ref : std_logic_vector(reg_width - 1 downto 0) := (others => '1'); -- copied from reg_shortest on update counter overflows, serves as reference for aes3 clock regeneration`
54
55			`signal sdata_int : std_logic := '0';`
56			`signal bsync_int : std_logic := '0';`
57			`signal fsync_int : std_logic := '0';`
58			`signal sync_ok : std_logic := '0';`
59			`signal active_int : std_logic := '0';`
60	7	nohous	`signal timeout : std_logic := '1';`
61			`begin`
62
63			`------------------------------------------`
64			`-- input_shift_reg_proc`
65			`-- Carries out input double sampling in`
66	3	nohous	`-- order to avoid metastable states on FFs`
67			`-- and creation of delayed signals for`
68			`-- change detector (1 clk period) and`
69	7	nohous	`-- decoder (2 clk periods)`
70			`------------------------------------------`
71			`input_shift_reg_proc: process (clk)`
72			`begin`
73			`if clk'event and clk = '1' then`
74			`if reset = '1' then`
75			`aes3_sync <= (others => '0');`
76	3	nohous	`else`
77	7	nohous	`aes3_sync <= aes3 & aes3_sync(3 downto 1); -- synthetizes shift reg`
78			`end if;`
79			`end if;`
80			`end process;`
81
82			`------------------------------------------`
83			`-- change_detect_proc`
84			`-- Detects edge on sampled input in the`
85			`-- way of comparsion of delayed input`
86			`-- and current state on XOR gate`
87			`------------------------------------------`
88			`change_detect_proc: process (clk)`
89			`begin`
90			`if clk'event and clk = '1' then`
91			`if reset = '1' then`
92			`change <= '0';`
93			`else`
94			`change <= '0';`
95			`if aes3_sync(2) /= aes3_sync(1) then`
96			`change <= '1';`
97			`end if;`
98			`end if;`
99			`end if;`
100			`end process;`
101
102			`shortest_pulse_dur_cnt_proc: process (clk)`
103			`begin`
104			`if clk'event and clk = '1' then`
105			`if reset = '1' then`
106			`reg_shortest <= (others => '1');`
107			`dur_counter <= (others => '0');`
108			`else`
109	3	nohous	`if change = '1' then`
110	7	nohous	`timeout <= '0';`
111			`if dur_counter < reg_shortest then`
112			`reg_shortest <= dur_counter(reg_width - 1 downto 0);`
113			`end if;`
114			`dur_counter <= (others => '0');`
115	3	nohous	`elsif dur_counter = 2**(reg_width + 2) - 1 then`
116			`timeout <= '1';`
117	7	nohous	`else`
118			`dur_counter <= dur_counter + 1;`
119	3	nohous	`end if;`
120	7	nohous	`if reg_reset = '1' then`
121			`reg_shortest <= (others => '1');`
122			`end if;`
123			`end if;`
124			`end if;`
125	3	nohous	`end process;`
126
127	7	nohous	`register_update_timer_proc: process (clk)`
128			`begin`
129			`if clk'event and clk = '1' then`
130			`reg_reset <= '0';`
131			`if reset = '1' then`
132			`reg_shortest_ref <= (others => '1');`
133			`upd_timer <= (others => '0');`
134			`else`
135			`if change = '1' then`
136			`if upd_timer = 63 then`
137			`reg_shortest_ref <= reg_shortest;`
138			`reg_reset <= '1';`
139			`end if;`
140			`upd_timer <= upd_timer + 1;`
141			`end if;`
142			`end if;`
143			`end if;`
144			`end process;`
145
146			`aes3_clk_regen_proc: process (clk)`
147			`begin`
148			`if clk'event and clk = '1' then`
149			`if reset = '1' then`
150			`clk_counter <= (others => '0');`
151			`aes3_clk <= '0';`
152			`else`
153			`clk_counter <= clk_counter - 1;`
154			`aes3_clk <= '0';`
155			`if change = '1' then`
156			`clk_counter <= '0' & reg_shortest_ref(reg_width - 1 downto 1);`
157			`elsif clk_counter = 0 then`
158			`clk_counter <= reg_shortest_ref;`
159			`aes3_clk <= '1';`
160			`end if;`
161			`end if;`
162			`end if;`
163			`end process;`
164
165	3	nohous	`decoder_shift_reg_proc: process (clk)`
166			`begin`
167			`if clk'event and clk = '1' then`
168			`if reset = '1' then`
169			`decoder_shift <= (others => '0');`
170			`elsif aes3_clk = '1' then`
171			`decoder_shift <= aes3_sync(0) & decoder_shift(7 downto 1);`
172			`end if;`
173			`end if;`
174	7	nohous	`end process;`
175
176	3	nohous	`decoder_proc: process (clk)`
177			`begin`
178			`if clk'event and clk = '1' then`
179			`if timeout = '1' then`
180			`sync_ok <= '0';`
181			`end if;`
182			`if aes3_clk = '1' then`
183			`align_counter <= not align_counter;`
184			`if decoder_shift = X_PREAMBLE or decoder_shift = not X_PREAMBLE then`
185			`fsync_int <= '1';`
186			`bsync_int <= '0';`
187			`sync_ok <= '1';`
188			`align_counter <= '0';`
189			`elsif decoder_shift = Y_PREAMBLE or decoder_shift = not Y_PREAMBLE then`
190			`fsync_int <= '0';`
191			`bsync_int <= '0';`
192			`sync_ok <= '1';`
193			`align_counter <= '0';`
194			`elsif decoder_shift = Z_PREAMBLE or decoder_shift = not Z_PREAMBLE then`
195			`fsync_int <= '1';`
196			`bsync_int <= '1';`
197			`sync_ok <= '1';`
198			`align_counter <= '0';`
199			`end if;`
200			`if align_counter = '1' then`
201			`if decoder_shift(1) = decoder_shift(0) then`
202			`sdata_int <= '0';`
203			`else`
204			`sdata_int <= '1';`
205			`end if;`
206			`end if;`
207			`end if;`
208			`end if;`
209			`end process;`
210
211			`active_int <= sync_ok and not timeout;`
212
213			`sclk <= align_counter and active_int;`
214			`sdata <= sdata_int and active_int;`
215			`fsync <= fsync_int and active_int;`
216			`bsync <= bsync_int and active_int;`
217			`active <= active_int;`
218	7	nohous
219
220			`end Behavioral;`
221

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[/] [aes3rx/] [trunk/] [rtl/] [vhdl/] [aes3rx.vhd] - Blame information for rev 7