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[/] [aes3rx/] [trunk/] [testbench/] [vhdl/] [rx-test.vhd] - Blame information for rev 10

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--------------------------------------------------------------------------------
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-- Company:
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-- Engineer:
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--
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-- Create Date:   12:17:15 10/10/2008
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-- Design Name:   receiver
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-- Module Name:   C:/Xilinx92i/projects/citac/tb_rx.vhd
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-- Project Name:  citac
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-- Target Device:
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-- Tool versions:
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-- Description:
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--
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-- VHDL Test Bench Created by ISE for module: receiver
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--
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-- Dependencies:
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--
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-- Revision:
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-- Revision 0.01 - File Created
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-- Additional Comments:
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--
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-- Notes:
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-- This testbench has been automatically generated using types std_logic and
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-- std_logic_vector for the ports of the unit under test.  Xilinx recommends
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-- that these types always be used for the top-level I/O of a design in order
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-- to guarantee that the testbench will bind correctly to the post-implementation
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-- simulation model.
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--------------------------------------------------------------------------------
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LIBRARY ieee;
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USE ieee.std_logic_1164.ALL;
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USE ieee.std_logic_unsigned.all;
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USE ieee.std_logic_arith.all;
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USE ieee.numeric_std.ALL;
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use ieee.math_real.all; -- for UNIFORM, TRUNC
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ENTITY tb_rx_vhd IS
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END tb_rx_vhd;
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ARCHITECTURE behavior OF tb_rx_vhd IS
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        -- Component Declaration for the Unit Under Test (UUT)
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        COMPONENT aes3rx
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        generic (
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                reg_width : integer := 5
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        );
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   port (
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      clk   : in  std_logic; -- master clock
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      aes3  : in  std_logic; -- input
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      reset : in  std_logic; -- synchronous reset
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      sdata : out std_logic; -- output serial data
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      sclk  : out std_logic; -- output serial data clock
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      bsync : out std_logic; -- block start (high when Z subframe is being transmitted)
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      lrck  : out std_logic; -- frame sync (high for channel A, low for B)
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      active: out std_logic  -- receiver has valid data on its outputs
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   );
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        end component;
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        --Inputs
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        SIGNAL CLK_50MHZ :  std_logic := '0';
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        SIGNAL RX :  std_logic := '0';
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   signal TX : std_logic := '0';
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        --Outputs
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--      SIGNAL active : std_logic;
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--      SIGNAL sdata :  std_logic;
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--      SIGNAL sclk :  std_logic;
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--      SIGNAL fsync :  std_logic;
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--      signal bsync : std_logic;
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   constant PERIOD : time := 20ns;
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   constant DUTY_CYCLE : real := 0.5;
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   constant OFFSET : time := 100 ns;
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        type INT_ARRAY is array (integer range <>) of integer;
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        shared variable vals : INT_ARRAY(0 to 191);
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        shared variable S : time :=150 ns;
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        shared variable M : time :=310 ns;
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        shared variable L : time :=485 ns;
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        procedure vector2aes(vector : in std_logic_vector (23 downto 0); signal aes : inout  std_logic) is
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        begin
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                for i in 0 to 23 loop
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                        if vector(i) = '0' then
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                                aes <= not aes;
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                                wait for M;
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                        elsif vector(i) = '1' then
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                                aes <= not aes;
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                                wait for S;
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                                aes <= not aes;
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                                wait for S;
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                        end if;
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                end loop;
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        end procedure;
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        procedure generate_block(pcm_data : in INT_ARRAY(0 to 191); signal aes : inout  std_logic; signal curr_val : out std_logic_vector(23 downto 0)) is
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        begin
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                -- Z preamble
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                aes <= not aes;
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                wait for L;
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                aes <= not aes;
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                wait for S;
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                aes <= not aes;
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                wait for S;
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                aes <= not aes;
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                wait for L;
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                vector2aes(conv_std_logic_vector(pcm_data(0), 24), aes);
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                curr_val <= conv_std_logic_vector(pcm_data(0), 24);
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                aes <= not aes; -- 1.5
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                wait for M;
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                aes <= not aes; -- 1.5
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                wait for M;
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                aes <= not aes; -- 1.5
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                wait for M;
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                aes <= not aes; -- 1.5
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                wait for M;
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                for i in 1 to 191 loop
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                        if i mod 2 /= 0 then --B subframe
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                                --Y preamble
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                                aes <= not aes; -- 1.5
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                                wait for L;
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                                aes <= not aes; -- 1.5
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                                wait for M;
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                                aes <= not aes; -- 3
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                                wait for S;
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                                aes <= not aes; -- 3.5
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                                wait for M;
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                        else --A subframe
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                                --X preamble
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                                aes <= not aes; -- 1.5
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                                wait for L;
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                                aes <= not aes;
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                                wait for L;
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                                aes <= not aes;
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                                wait for S;
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                                aes <= not aes;
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                                wait for S;
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                        end if;
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                        curr_val <= conv_std_logic_vector(pcm_data(i), 24);
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                        vector2aes(conv_std_logic_vector(pcm_data(i), 24), aes);
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                        aes <= not aes; -- 1.5
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                        wait for M;
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                        aes <= not aes; -- 1.5
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                        wait for M;
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                        aes <= not aes; -- 1.5
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                        wait for M;
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                        aes <= not aes; -- 1.5
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                        wait for M;
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                end loop;
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        end procedure;
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        shared variable seed1 : positive;
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        shared variable seed2 : positive;
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        shared variable rand : real;
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        signal curr_val : std_logic_vector(23 downto 0);
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BEGIN
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        -- Instantiate the Unit Under Test (UUT)
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        uut: aes3rx PORT MAP(
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                clk  => CLK_50MHZ,
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                aes3 => RX,
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                reset => '0'
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                --bsync => bsync
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                --bsync => bsync
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        );
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        PROCESS    -- clock process for CLK_50MHZ
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        BEGIN
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                WAIT for OFFSET;
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                CLOCK_LOOP : LOOP
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                         CLK_50MHZ <= '0';
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                         WAIT FOR (PERIOD - (PERIOD * DUTY_CYCLE));
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                         CLK_50MHZ <= '1';
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                         WAIT FOR (PERIOD * DUTY_CYCLE);
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                END LOOP CLOCK_LOOP;
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        END PROCESS;
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        tb : PROCESS
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        BEGIN
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                wait for 100 ns;
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                for i in 0 to 191 loop
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                        if i = 0 then
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                                vals(i) := 8388609;
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                        else
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                                vals(i) := 8388609;
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                        end if;
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                end loop;
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                generate_block(vals, RX, curr_val);
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                for i in 0 to 191 loop
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                        if i = 0 then
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                                vals(i) := 0;
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                        else
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                                vals(i) := vals(i-1) + 10000;
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                        end if;
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                end loop;
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                generate_block(vals, RX, curr_val);
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                -- Wait 100 ns for global reset to finish
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                wait for 100 us;
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      S := 81.2 ns;
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      M := 162.6 ns;
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      L := 244 ns;
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      wait for 100 ns;
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                for i in 0 to 191 loop
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                        if i = 0 then
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                                vals(i) := 0;
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                        else
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                                vals(i) := 1;
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                        end if;
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                end loop;
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                generate_block(vals, RX, curr_val);
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                for i in 0 to 191 loop
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                        if i = 0 then
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                                vals(i) := 0;
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                        else
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                                vals(i) := vals(i-1) + 10000;
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                        end if;
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                end loop;
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                wait; -- will wait forever
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        END PROCESS;
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END;

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