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[/] [aes_all_keylength/] [trunk/] [aes.vhd] - Blame information for rev 4

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library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_unsigned.all;
 
entity aes is
    port ( --system signals
           reset              : in  std_logic;
           clock              : in  std_logic;
           --key input related signals
           key                : in  std_logic_vector (31 downto 0);
           keynew             : in  std_logic;
           keyload            : in  std_logic;
           keyexpansionready  : out std_logic;
           --text input related signals
           text               : in  std_logic_vector (127 downto 0);
           empty              : out std_logic;
           enable             : in  std_logic;
           --text output related signals
           ciphertext         : out std_logic_vector (127 downto 0);
           ready              : out std_logic);
end aes;
 
architecture Behavioral of aes is
        component keyexpansion
        port(
                reset : in std_logic;
                clock : in std_logic;
                loadkey : in std_logic;
                key : in std_logic_vector(31 downto 0);
                keyexpansionready : inout std_logic;
                subkeyenable : out std_logic;
                subkeyaddress : out std_logic_vector(3 downto 0);
                subkey : out std_logic_vector(127 downto 0);
                numberofrounds : out std_logic_vector(3 downto 0)
                );
        end component;
        signal subKeyEnable,keyExpansionReadyI : std_logic;
        signal subKeyAddress, numberOfRounds : std_logic_vector(3 downto 0);
        signal subKey : std_logic_vector(127 downto 0);
   type keyRamT is array (0 to 15) of std_logic_vector(127 downto 0);
   signal keyRam : keyRamT;
   signal addIn, addOut, addReg, addKey, subIn, subOut, subReg, shiftIn, shiftOut, shiftReg, mixIn, mixOut, mixReg : std_logic_vector(127 downto 0);
   type stateRowT is array (0 to 3) of std_logic_vector(7 downto 0);
   type stateT is array (0 to 3) of stateRowT;
   signal shiftInState, shiftOutState: stateT;
   signal addCnt, subCnt, shiftCnt, mixCnt : std_logic_vector(3 downto 0);
 
begin
 
--CONTROLLING STATE MACHINE
ctrlFsm:process(clock)
begin
   if rising_edge(clock) then
      if mixCnt = x"f" then
         if enable = '1' then
            addCnt <= mixCnt + '1';
         else
            addCnt <= mixCnt;
         end if;
      else
         addCnt <= mixCnt + '1';
      end if;
      if addCnt = numberOfRounds then
         subCnt <= x"f";
      else
         subCnt <= addCnt;
      end if;
      shiftCnt <= subCnt;
      mixCnt <= shiftCnt;
      if reset = '1' then
         addCnt <= x"f";
         subCnt <= x"f";
         shiftCnt <= x"f";
         mixCnt <= x"f";
      end if;
   end if;
end process;
empty <= '1' when addCnt = x"f" else '0';
ready <= '1' when addCnt = numberOfRounds else '0';
 
--KEY EXPANSION ROUTINE
instKeyExpansion: keyExpansion PORT MAP(
   reset             => keyNew,
   clock             => clock,
   loadKey           => keyLoad,
   key               => key,
   keyExpansionReady => keyExpansionReadyI,
   subKeyEnable      => subKeyEnable,
   subKeyAddress     => subKeyAddress,
   subKey            => subKey,
   numberOfRounds    => numberOfRounds);
keyExpansionReady <= keyExpansionReadyI;
 
--KEY RAM
dualPortRAM:process(clock)
begin
   if rising_edge(clock) then
      if subKeyEnable = '1' then
         keyRAM(conv_integer(subKeyAddress)) <= subKey;
      end if;
      addKey <= keyRAM(conv_integer(shiftCnt + '1'));
   end if;
end process;
 
--INPUT
addIn <= mixReg when mixCnt /= x"f" else
         text when enable = '1' else
         x"10000000000000000000000000000000";
 
--ADD BYTES TRANSFORM
addOut <= addIn xor addKey;
process(clock)
begin
   if rising_edge(clock) then
      addReg <= addOut;
   end if;
end process;
 
--SUB BYTES TRANSFORM
subIn <= addReg;
subBytes: for i in 0 to 15 generate
   type subT is array(0 to 255) of std_logic_vector(7 downto 0);
   constant sub : subT :=
     (x"63", x"7c", x"77", x"7b", x"f2", x"6b", x"6f", x"c5", x"30", x"01", x"67", x"2b", x"fe", x"d7", x"ab", x"76",
 
      x"ca", x"82", x"c9", x"7d", x"fa", x"59", x"47", x"f0", x"ad", x"d4", x"a2", x"af", x"9c", x"a4", x"72", x"c0",
      x"b7", x"fd", x"93", x"26", x"36", x"3f", x"f7", x"cc", x"34", x"a5", x"e5", x"f1", x"71", x"d8", x"31", x"15",
      x"04", x"c7", x"23", x"c3", x"18", x"96", x"05", x"9a", x"07", x"12", x"80", x"e2", x"eb", x"27", x"b2", x"75",
      x"09", x"83", x"2c", x"1a", x"1b", x"6e", x"5a", x"a0", x"52", x"3b", x"d6", x"b3", x"29", x"e3", x"2f", x"84",
      x"53", x"d1", x"00", x"ed", x"20", x"fc", x"b1", x"5b", x"6a", x"cb", x"be", x"39", x"4a", x"4c", x"58", x"cf",
      x"d0", x"ef", x"aa", x"fb", x"43", x"4d", x"33", x"85", x"45", x"f9", x"02", x"7f", x"50", x"3c", x"9f", x"a8",
      x"51", x"a3", x"40", x"8f", x"92", x"9d", x"38", x"f5", x"bc", x"b6", x"da", x"21", x"10", x"ff", x"f3", x"d2",
      x"cd", x"0c", x"13", x"ec", x"5f", x"97", x"44", x"17", x"c4", x"a7", x"7e", x"3d", x"64", x"5d", x"19", x"73",
      x"60", x"81", x"4f", x"dc", x"22", x"2a", x"90", x"88", x"46", x"ee", x"b8", x"14", x"de", x"5e", x"0b", x"db",
      x"e0", x"32", x"3a", x"0a", x"49", x"06", x"24", x"5c", x"c2", x"d3", x"ac", x"62", x"91", x"95", x"e4", x"79",
      x"e7", x"c8", x"37", x"6d", x"8d", x"d5", x"4e", x"a9", x"6c", x"56", x"f4", x"ea", x"65", x"7a", x"ae", x"08",
      x"ba", x"78", x"25", x"2e", x"1c", x"a6", x"b4", x"c6", x"e8", x"dd", x"74", x"1f", x"4b", x"bd", x"8b", x"8a",
      x"70", x"3e", x"b5", x"66", x"48", x"03", x"f6", x"0e", x"61", x"35", x"57", x"b9", x"86", x"c1", x"1d", x"9e",
      x"e1", x"f8", x"98", x"11", x"69", x"d9", x"8e", x"94", x"9b", x"1e", x"87", x"e9", x"ce", x"55", x"28", x"df",
      x"8c", x"a1", x"89", x"0d", x"bf", x"e6", x"42", x"68", x"41", x"99", x"2d", x"0f", x"b0", x"54", x"bb", x"16");
begin
   subOut(8*(i+1)-1 downto 8*i) <= sub(conv_integer(subIn(8*(i+1)-1 downto 8*i)));
end generate;
process(clock)
begin
   if rising_edge(clock) then
      subReg <= subOut;
   end if;
end process;
 
--SHIFT ROWS TRANSFORM
shiftIn <= subReg;
shiftGenCol:for row in 0 to 3 generate begin
   shiftGenRow:for col in 0 to 3 generate begin
      shiftInState(3-col)(3-row) <= shiftIn(32*col+8*(row+1)-1 downto 32*col+8*row);
      shiftOut(32*col+8*(row+1)-1 downto 32*col+8*row) <= shiftOutState(3-col)(3-row);
   end generate;
end generate;
shiftOutState(0)(0) <= shiftInState(0)(0);
shiftOutState(0)(1) <= shiftInState(1)(1);
shiftOutState(0)(2) <= shiftInState(2)(2);
shiftOutState(0)(3) <= shiftInState(3)(3);
shiftOutState(1)(0) <= shiftInState(1)(0);
shiftOutState(1)(1) <= shiftInState(2)(1);
shiftOutState(1)(2) <= shiftInState(3)(2);
shiftOutState(1)(3) <= shiftInState(0)(3);
shiftOutState(2)(0) <= shiftInState(2)(0);
shiftOutState(2)(1) <= shiftInState(3)(1);
shiftOutState(2)(2) <= shiftInState(0)(2);
shiftOutState(2)(3) <= shiftInState(1)(3);
shiftOutState(3)(0) <= shiftInState(3)(0);
shiftOutState(3)(1) <= shiftInState(0)(1);
shiftOutState(3)(2) <= shiftInState(1)(2);
shiftOutState(3)(3) <= shiftInState(2)(3);
process(clock)
begin
   if rising_edge(clock) then
      shiftReg <= shiftOut;
   end if;
end process;
 
--MIX COLUMNS TRANSFORM
mixIn <= shiftReg;
mixColumns : for i in 0 to 3 generate
   signal xi, xo : std_logic_vector(31 downto 0);
   signal s0i, s1i, s2i, s3i, s0o, s1o, s2o, s3o : std_logic_vector(7 downto 0);
   signal s0x2, s1x2, s2x2, s3x2, s0x3, s1x3, s2x3, s3x3 : std_logic_vector(7 downto 0);
begin
   xi <= mixIn(32*(i+1)-1 downto 32*i);
   s0i <= xi(31 downto 24);
   s1i <= xi(23 downto 16);
   s2i <= xi(15 downto 8);
   s3i <= xi(7 downto 0);
   --multiplication by two over Galois field
   s0x2 <= s0i(6 downto 0) & '0' when s0i(7) = '0' else (s0i(6 downto 0) & '0') xor "00011011";
   s1x2 <= s1i(6 downto 0) & '0' when s1i(7) = '0' else (s1i(6 downto 0) & '0') xor "00011011";
   s2x2 <= s2i(6 downto 0) & '0' when s2i(7) = '0' else (s2i(6 downto 0) & '0') xor "00011011";
   s3x2 <= s3i(6 downto 0) & '0' when s3i(7) = '0' else (s3i(6 downto 0) & '0') xor "00011011";
   --multiplication by three over Galois field: addition of times 1 and times 2
   s0x3 <= s0i xor s0x2;
   s1x3 <= s1i xor s1x2;
   s2x3 <= s2i xor s2x2;
   s3x3 <= s3i xor s3x2;
   --addition over Galois field
   s0o <= s0x2 xor s1x3 xor s2i xor s3i;
   s1o <= s0i xor s1x2 xor s2x3 xor s3i;
   s2o <= s0i xor s1i xor s2x2 xor s3x3;
   s3o <= s0x3 xor s1i xor s2i xor s3x2;
   xo <= s0o & s1o & s2o & s3o;
   mixOut(32*(i+1)-1 downto 32*i) <= xo;
end generate;
process(clock)
begin
   if rising_edge(clock) then
      if shiftCnt + '1' = numberOfRounds then
         mixReg <= shiftReg;
      else
         mixReg <= mixOut;
      end if;
   end if;
end process;
 
--OUTPUT
cipherText <= addReg;
 
end Behavioral;
 

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Subversion Repositories aes_all_keylength

[/] [aes_all_keylength/] [trunk/] [aes.vhd] - Blame information for rev 4

Line No.	Rev	Author	Line
1	4	feketebv	`library ieee;`
2			`use ieee.std_logic_1164.all;`
3			`use ieee.numeric_std.all;`
4			`use ieee.std_logic_unsigned.all;`
5
6			`entity aes is`
7			`port ( --system signals`
8			`reset : in std_logic;`
9			`clock : in std_logic;`
10			`--key input related signals`
11			`key : in std_logic_vector (31 downto 0);`
12			`keynew : in std_logic;`
13			`keyload : in std_logic;`
14			`keyexpansionready : out std_logic;`
15			`--text input related signals`
16			`text : in std_logic_vector (127 downto 0);`
17			`empty : out std_logic;`
18			`enable : in std_logic;`
19			`--text output related signals`
20			`ciphertext : out std_logic_vector (127 downto 0);`
21			`ready : out std_logic);`
22			`end aes;`
23
24			`architecture Behavioral of aes is`
25			`component keyexpansion`
26			`port(`
27			`reset : in std_logic;`
28			`clock : in std_logic;`
29			`loadkey : in std_logic;`
30			`key : in std_logic_vector(31 downto 0);`
31			`keyexpansionready : inout std_logic;`
32			`subkeyenable : out std_logic;`
33			`subkeyaddress : out std_logic_vector(3 downto 0);`
34			`subkey : out std_logic_vector(127 downto 0);`
35			`numberofrounds : out std_logic_vector(3 downto 0)`
36			`);`
37			`end component;`
38			`signal subKeyEnable,keyExpansionReadyI : std_logic;`
39			`signal subKeyAddress, numberOfRounds : std_logic_vector(3 downto 0);`
40			`signal subKey : std_logic_vector(127 downto 0);`
41			`type keyRamT is array (0 to 15) of std_logic_vector(127 downto 0);`
42			`signal keyRam : keyRamT;`
43			`signal addIn, addOut, addReg, addKey, subIn, subOut, subReg, shiftIn, shiftOut, shiftReg, mixIn, mixOut, mixReg : std_logic_vector(127 downto 0);`
44			`type stateRowT is array (0 to 3) of std_logic_vector(7 downto 0);`
45			`type stateT is array (0 to 3) of stateRowT;`
46			`signal shiftInState, shiftOutState: stateT;`
47			`signal addCnt, subCnt, shiftCnt, mixCnt : std_logic_vector(3 downto 0);`
48
49			`begin`
50
51			`--CONTROLLING STATE MACHINE`
52			`ctrlFsm:process(clock)`
53			`begin`
54			`if rising_edge(clock) then`
55			`if mixCnt = x"f" then`
56			`if enable = '1' then`
57			`addCnt <= mixCnt + '1';`
58			`else`
59			`addCnt <= mixCnt;`
60			`end if;`
61			`else`
62			`addCnt <= mixCnt + '1';`
63			`end if;`
64			`if addCnt = numberOfRounds then`
65			`subCnt <= x"f";`
66			`else`
67			`subCnt <= addCnt;`
68			`end if;`
69			`shiftCnt <= subCnt;`
70			`mixCnt <= shiftCnt;`
71			`if reset = '1' then`
72			`addCnt <= x"f";`
73			`subCnt <= x"f";`
74			`shiftCnt <= x"f";`
75			`mixCnt <= x"f";`
76			`end if;`
77			`end if;`
78			`end process;`
79			`empty <= '1' when addCnt = x"f" else '0';`
80			`ready <= '1' when addCnt = numberOfRounds else '0';`
81
82			`--KEY EXPANSION ROUTINE`
83			`instKeyExpansion: keyExpansion PORT MAP(`
84			`reset => keyNew,`
85			`clock => clock,`
86			`loadKey => keyLoad,`
87			`key => key,`
88			`keyExpansionReady => keyExpansionReadyI,`
89			`subKeyEnable => subKeyEnable,`
90			`subKeyAddress => subKeyAddress,`
91			`subKey => subKey,`
92			`numberOfRounds => numberOfRounds);`
93			`keyExpansionReady <= keyExpansionReadyI;`
94
95			`--KEY RAM`
96			`dualPortRAM:process(clock)`
97			`begin`
98			`if rising_edge(clock) then`
99			`if subKeyEnable = '1' then`
100			`keyRAM(conv_integer(subKeyAddress)) <= subKey;`
101			`end if;`
102			`addKey <= keyRAM(conv_integer(shiftCnt + '1'));`
103			`end if;`
104			`end process;`
105
106			`--INPUT`
107			`addIn <= mixReg when mixCnt /= x"f" else`
108			`text when enable = '1' else`
109			`x"10000000000000000000000000000000";`
110
111			`--ADD BYTES TRANSFORM`
112			`addOut <= addIn xor addKey;`
113			`process(clock)`
114			`begin`
115			`if rising_edge(clock) then`
116			`addReg <= addOut;`
117			`end if;`
118			`end process;`
119
120			`--SUB BYTES TRANSFORM`
121			`subIn <= addReg;`
122			`subBytes: for i in 0 to 15 generate`
123			`type subT is array(0 to 255) of std_logic_vector(7 downto 0);`
124			`constant sub : subT :=`
125			`(x"63", x"7c", x"77", x"7b", x"f2", x"6b", x"6f", x"c5", x"30", x"01", x"67", x"2b", x"fe", x"d7", x"ab", x"76",`
126
127			`x"ca", x"82", x"c9", x"7d", x"fa", x"59", x"47", x"f0", x"ad", x"d4", x"a2", x"af", x"9c", x"a4", x"72", x"c0",`
128			`x"b7", x"fd", x"93", x"26", x"36", x"3f", x"f7", x"cc", x"34", x"a5", x"e5", x"f1", x"71", x"d8", x"31", x"15",`
129			`x"04", x"c7", x"23", x"c3", x"18", x"96", x"05", x"9a", x"07", x"12", x"80", x"e2", x"eb", x"27", x"b2", x"75",`
130			`x"09", x"83", x"2c", x"1a", x"1b", x"6e", x"5a", x"a0", x"52", x"3b", x"d6", x"b3", x"29", x"e3", x"2f", x"84",`
131			`x"53", x"d1", x"00", x"ed", x"20", x"fc", x"b1", x"5b", x"6a", x"cb", x"be", x"39", x"4a", x"4c", x"58", x"cf",`
132			`x"d0", x"ef", x"aa", x"fb", x"43", x"4d", x"33", x"85", x"45", x"f9", x"02", x"7f", x"50", x"3c", x"9f", x"a8",`
133			`x"51", x"a3", x"40", x"8f", x"92", x"9d", x"38", x"f5", x"bc", x"b6", x"da", x"21", x"10", x"ff", x"f3", x"d2",`
134			`x"cd", x"0c", x"13", x"ec", x"5f", x"97", x"44", x"17", x"c4", x"a7", x"7e", x"3d", x"64", x"5d", x"19", x"73",`
135			`x"60", x"81", x"4f", x"dc", x"22", x"2a", x"90", x"88", x"46", x"ee", x"b8", x"14", x"de", x"5e", x"0b", x"db",`
136			`x"e0", x"32", x"3a", x"0a", x"49", x"06", x"24", x"5c", x"c2", x"d3", x"ac", x"62", x"91", x"95", x"e4", x"79",`
137			`x"e7", x"c8", x"37", x"6d", x"8d", x"d5", x"4e", x"a9", x"6c", x"56", x"f4", x"ea", x"65", x"7a", x"ae", x"08",`
138			`x"ba", x"78", x"25", x"2e", x"1c", x"a6", x"b4", x"c6", x"e8", x"dd", x"74", x"1f", x"4b", x"bd", x"8b", x"8a",`
139			`x"70", x"3e", x"b5", x"66", x"48", x"03", x"f6", x"0e", x"61", x"35", x"57", x"b9", x"86", x"c1", x"1d", x"9e",`
140			`x"e1", x"f8", x"98", x"11", x"69", x"d9", x"8e", x"94", x"9b", x"1e", x"87", x"e9", x"ce", x"55", x"28", x"df",`
141			`x"8c", x"a1", x"89", x"0d", x"bf", x"e6", x"42", x"68", x"41", x"99", x"2d", x"0f", x"b0", x"54", x"bb", x"16");`
142			`begin`
143			`subOut(8(i+1)-1 downto 8i) <= sub(conv_integer(subIn(8(i+1)-1 downto 8i)));`
144			`end generate;`
145			`process(clock)`
146			`begin`
147			`if rising_edge(clock) then`
148			`subReg <= subOut;`
149			`end if;`
150			`end process;`
151
152			`--SHIFT ROWS TRANSFORM`
153			`shiftIn <= subReg;`
154			`shiftGenCol:for row in 0 to 3 generate begin`
155			`shiftGenRow:for col in 0 to 3 generate begin`
156			`shiftInState(3-col)(3-row) <= shiftIn(32col+8(row+1)-1 downto 32col+8row);`
157			`shiftOut(32col+8(row+1)-1 downto 32col+8row) <= shiftOutState(3-col)(3-row);`
158			`end generate;`
159			`end generate;`
160			`shiftOutState(0)(0) <= shiftInState(0)(0);`
161			`shiftOutState(0)(1) <= shiftInState(1)(1);`
162			`shiftOutState(0)(2) <= shiftInState(2)(2);`
163			`shiftOutState(0)(3) <= shiftInState(3)(3);`
164			`shiftOutState(1)(0) <= shiftInState(1)(0);`
165			`shiftOutState(1)(1) <= shiftInState(2)(1);`
166			`shiftOutState(1)(2) <= shiftInState(3)(2);`
167			`shiftOutState(1)(3) <= shiftInState(0)(3);`
168			`shiftOutState(2)(0) <= shiftInState(2)(0);`
169			`shiftOutState(2)(1) <= shiftInState(3)(1);`
170			`shiftOutState(2)(2) <= shiftInState(0)(2);`
171			`shiftOutState(2)(3) <= shiftInState(1)(3);`
172			`shiftOutState(3)(0) <= shiftInState(3)(0);`
173			`shiftOutState(3)(1) <= shiftInState(0)(1);`
174			`shiftOutState(3)(2) <= shiftInState(1)(2);`
175			`shiftOutState(3)(3) <= shiftInState(2)(3);`
176			`process(clock)`
177			`begin`
178			`if rising_edge(clock) then`
179			`shiftReg <= shiftOut;`
180			`end if;`
181			`end process;`
182
183			`--MIX COLUMNS TRANSFORM`
184			`mixIn <= shiftReg;`
185			`mixColumns : for i in 0 to 3 generate`
186			`signal xi, xo : std_logic_vector(31 downto 0);`
187			`signal s0i, s1i, s2i, s3i, s0o, s1o, s2o, s3o : std_logic_vector(7 downto 0);`
188			`signal s0x2, s1x2, s2x2, s3x2, s0x3, s1x3, s2x3, s3x3 : std_logic_vector(7 downto 0);`
189			`begin`
190			`xi <= mixIn(32(i+1)-1 downto 32i);`
191			`s0i <= xi(31 downto 24);`
192			`s1i <= xi(23 downto 16);`
193			`s2i <= xi(15 downto 8);`
194			`s3i <= xi(7 downto 0);`
195			`--multiplication by two over Galois field`
196			`s0x2 <= s0i(6 downto 0) & '0' when s0i(7) = '0' else (s0i(6 downto 0) & '0') xor "00011011";`
197			`s1x2 <= s1i(6 downto 0) & '0' when s1i(7) = '0' else (s1i(6 downto 0) & '0') xor "00011011";`
198			`s2x2 <= s2i(6 downto 0) & '0' when s2i(7) = '0' else (s2i(6 downto 0) & '0') xor "00011011";`
199			`s3x2 <= s3i(6 downto 0) & '0' when s3i(7) = '0' else (s3i(6 downto 0) & '0') xor "00011011";`
200			`--multiplication by three over Galois field: addition of times 1 and times 2`
201			`s0x3 <= s0i xor s0x2;`
202			`s1x3 <= s1i xor s1x2;`
203			`s2x3 <= s2i xor s2x2;`
204			`s3x3 <= s3i xor s3x2;`
205			`--addition over Galois field`
206			`s0o <= s0x2 xor s1x3 xor s2i xor s3i;`
207			`s1o <= s0i xor s1x2 xor s2x3 xor s3i;`
208			`s2o <= s0i xor s1i xor s2x2 xor s3x3;`
209			`s3o <= s0x3 xor s1i xor s2i xor s3x2;`
210			`xo <= s0o & s1o & s2o & s3o;`
211			`mixOut(32(i+1)-1 downto 32i) <= xo;`
212			`end generate;`
213			`process(clock)`
214			`begin`
215			`if rising_edge(clock) then`
216			`if shiftCnt + '1' = numberOfRounds then`
217			`mixReg <= shiftReg;`
218			`else`
219			`mixReg <= mixOut;`
220			`end if;`
221			`end if;`
222			`end process;`
223
224			`--OUTPUT`
225			`cipherText <= addReg;`
226
227			`end Behavioral;`
228