URL https://opencores.org/ocsvn/aes_decrypt_fpga/aes_decrypt_fpga/trunk

Subversion Repositories aes_decrypt_fpga

[/] [aes_decrypt_fpga/] [trunk/] [bench/] [verilog/] [aes_decrypt128_tb.sv] - Blame information for rev 3

Details | Compare with Previous | View Log


////////////////////////////////////////////////////////////////// ////
////                                                                                                                            ////
//// AES Decryption Core for FPGA                                                                       ////
////                                                                                                                            ////
//// This file is part of the AES Decryption Core for FPGA project      ////
//// http://www.opencores.org/cores/xxx/                                                        ////
////                                                                                                                            ////
//// Description                                                                                                        ////
//// Implementation of  AES Decryption Core for FPGA according to       ////
//// core specification document.                                                                       ////
////                                                                                                                            ////
//// To Do:                                                                                                             ////
//// -                                                                                                                          ////
////                                                                                                                            ////
//// Author(s):                                                                                                         ////
//// - scheng, schengopencores@opencores.org                                            ////
////                                                                                                                            ////
//////////////////////////////////////////////////////////////////////
////                                                                                                                            ////
//// Copyright (C) 2009 Authors and OPENCORES.ORG                                       ////
////                                                                                                                            ////
//// This source file may be used and distributed without                       ////
//// restriction provided that this copyright statement is not          ////
//// removed from the file and that any derivative work contains        ////
//// the original copyright notice and the associated disclaimer.       ////
////                                                                                                                            ////
//// This source file is free software; you can redistribute it         ////
//// and/or modify it under the terms of the GNU Lesser General         ////
//// Public License as published by the Free Software Foundation;       ////
//// either version 2.1 of the License, or (at your option) any         ////
//// later version.                                                                                             ////
////                                                                                                                            ////
//// This source is distributed in the hope that it will be             ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied         ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR            ////
//// PURPOSE. See the GNU Lesser General Public License for more        ////
//// details.                                                                                                           ////
////                                                                                                                            ////
//// You should have received a copy of the GNU Lesser General          ////
//// Public License along with this source; if not, download it         ////
//// from http://www.opencores.org/lgpl.shtml                                           ////
////                                                                                                                            //// ///
///////////////////////////////////////////////////////////////////
////                                                                                                                            ////
//// Testbench for 128-bit decryption                                                           ////
////                                                                                                                            ////
////////////////////////////////////////////////////////////////////////
`timescale 1ns/1ps
 
// Uncomment the following line if you're targetting Xilinx FPGA
//`define XILINX 1
 
// generic_muxfx.v defines a generic 2-to-1 MUX. This file is used to provide
// a generic definition of MUXF7 and MUXF8 in case you are not targetting Xilinx.
// When targetting Xilinx, skip this file to allow the simulator to locate the
// MUXF7 and MUXF8 in the Xilinx unisim library.
`ifndef XILINX
`include "generic/generic_muxfx.v"
`endif
 
`include "InvSbox.sv"
`include "InvSubBytes.sv"
`include "InvShiftRows.sv"
`include "InvAddRoundKey.sv"
`include "gfmul.sv"
`include "InvMixCol_slice.sv"
`include "InvMixColumns.sv"
`include "decrypt.sv"
`include "KschBuffer.sv"
`include "Sbox.sv"
`include "SubWord.sv"
`include "RotWord.sv"
`include "KeyExpand128.sv"
`include "aes_decrypt128.sv"
`include "aes_beh_model.sv"
 
`define PERIOD 10
`define T (`PERIOD/2)
`define Tcko 1
 
`define WAIT_N_CLK(num_of_clk) repeat(num_of_clk) @(posedge clk); #(`Tcko)
 
module aes_decrypt128_tb;
 
        logic   [0:127] ct;
        logic   ct_vld;
        wire    ct_rdy;
 
        logic   [0:127] kt;
        logic   kt_vld;
        wire    kt_rdy;
 
        wire    [0:127] pt;
        wire    pt_vld;
 
        logic   clk;
        logic   rst;
 
        int     sample_vec_failed = 0;
        int     back_to_back_failed = 0;
        int     RandVec_128_failed = 0;
        int     failed = 0;
 
        aes128_decrypt_t ref_model;
 
        logic   [0:127] tmp_kt;
        logic   [0:127] tmp_ct;
 
        `include "decrypt_vec.sv"
 
        task set_kt(input [0:127] x);
                kt = x;
                kt_vld = 1;
                `WAIT_N_CLK(1);
                kt_vld = 0;
                `WAIT_N_CLK(1);
        endtask
 
        task set_ct(input [0:127] x);
                ct = x;
                ct_vld = 1;
                `WAIT_N_CLK(1);
                ct_vld = 0;
                `WAIT_N_CLK(1);
        endtask
 
        function logic [0:127] rand128;
                rand128 = {$random, $random, $random, $random};
        endfunction
 
        always
        begin
                clk <= 1;
                #(`T);
                clk <= 0;
                #(`T);
        end
 
        aes_decrypt128 uut(.*);
 
        initial begin
                ref_model = new;
 
                rst = 1;
                kt_vld = 0;
                ct_vld = 0;
                `WAIT_N_CLK(3);
 
                rst = 0;
                `WAIT_N_CLK(1);
 
                // FIPS-197 sample vector test. FIPS-197 appendix C.1.
 
                $display("FIPS-197 sample vector test");
                $display("kt=000102030405060708090a0b0c0d0e0f ct=69c4e0d86a7b0430d8cdb78070b4c55a");
                wait (kt_rdy);
                set_kt(128'h000102030405060708090a0b0c0d0e0f);
                wait (ct_rdy);
                set_ct(128'h69c4e0d86a7b0430d8cdb78070b4c55a);
                wait (pt_vld);
                $display("pt=%h expected=00112233445566778899aabbccddeeff",pt);
                if (pt != 128'h00112233445566778899aabbccddeeff)
                begin
                        $display("***Mismatch");
                        sample_vec_failed = 1;
                        failed = 1;
                end
                $display("FIPS-197 sample vector test finished : %s", (sample_vec_failed)? "FAILED" : "PASSED");
                `WAIT_N_CLK(2);
 
                // Back-to-back ciphertext test.
                // Two ciphertext are applied back-to-back with no dead cycle in between.
 
                $display("\nBack-to-back ciphertext test");
                tmp_ct = rand128();
                tmp_kt = rand128();
                ref_model.KeyExpand(tmp_kt);
                ref_model.LoadCt(tmp_ct);
                ref_model.run(0);
 
                wait (kt_rdy);
                set_kt(tmp_kt);
                wait (ct_rdy);
                set_ct(tmp_ct);
                wait (pt_vld);
                $display("kt=%h ct=%h pt=%h expected=%h",tmp_kt,tmp_ct,pt,ref_model.GetState());
                if (pt != ref_model.GetState())
                begin
                        $display("***Mismatch");
                        back_to_back_failed = 1;
                        failed = 1;
                end
 
                tmp_ct = rand128();
                ref_model.LoadCt(tmp_ct);
                ref_model.run(0);
                wait (ct_rdy);
                set_ct(tmp_ct);
                wait (pt_vld);
                $display("kt=%h ct=%h pt=%h expected=%h",tmp_kt,tmp_ct,pt,ref_model.GetState());
                if (pt != ref_model.GetState())
                begin
                        $display("***Mismatch");
                        back_to_back_failed = 1;
                        failed = 1;
                end
 
                $display("Back-to-back ciphertext test finished : %s", (back_to_back_failed)? "FAILED" : "PASSED");
                `WAIT_N_CLK(2);
 
                // ECB-AES128.Decrypt sample vector test. SP800-38a appendix F,1.2
 
                $display("\nECB-AES128.Decrypt sample vector test");
                for (int k=0; k<`ECB_DECRYPT_128_VEC_SIZE; k++)
                begin
                        set_kt(ECBDecrypt_128_kt);
                        wait(ct_rdy);
                        set_ct(ECBDecrypt_128_ct[k]);
                        wait(pt_vld);
                        $display("kt=%h ct=%h pt=%h expected=%h",ECBDecrypt_128_kt,ECBDecrypt_128_ct[k],pt,ECBDecrypt_128_pt[k]);
                        if (pt != ECBDecrypt_128_pt[k])
                        begin
                                $display("***Mismatch");
                                ECBDecrypt_128_failed = 1;
                        end
                end
 
                $display("ECB-AES128.Decrypt sample vector test finished : %s", (ECBDecrypt_128_failed)? "FAILED" : "PASSED");
                `WAIT_N_CLK(2);
 
                // GFSbox Known Answer Test. AESAVS appendix B.1.
 
                $display("\nGFSbox Known Answer Test");
                for (int k=0; k<`GFSbox_128_VEC_SIZE; k++)
                begin
                        set_kt(GFSbox_128_kt);
                        wait(ct_rdy);
                        set_ct(GFSbox_128_ct[k]);
                        wait(pt_vld);
                        $display("kt=%h ct=%h pt=%h expected=%h",GFSbox_128_kt,GFSbox_128_ct[k],pt,GFSbox_128_pt[k]);
                        if (pt != GFSbox_128_pt[k])
                        begin
                                $display("***Mismatch");
                                GFSbox_128_failed = 1;
                        end
                end
 
                $display("GFSbox test finished : %s", (GFSbox_128_failed)? "FAILED" : "PASSED");
                `WAIT_N_CLK(2);
 
                // KeySbox Known Answer Test. AESAVS appendix C.1.
 
                $display("\nKeySbox Known Answer Test");
                for (int k=0; k<`KEYSBOX_128_VEC_SIZE; k++)
                begin
                        set_kt(KeySbox_128_kt[k]);
                        wait(ct_rdy);
                        set_ct(KeySbox_128_ct[k]);
                        wait(pt_vld);
                        $display("kt=%h ct=%h pt=%h expected=%h",KeySbox_128_kt[k],KeySbox_128_ct[k],pt,KeySbox_128_pt);
                        if (pt != KeySbox_128_pt[k])
                        begin
                                $display("***Mismatch");
                                KeySbox_128_failed = 1;
                        end
                end
 
                $display("KeySbox test finished : %s", (KeySbox_128_failed)? "FAILED" : "PASSED");
                `WAIT_N_CLK(2);
 
                // VarTxt Known Answer Test. AESAVS appendix D.1.
 
                $display("\nVarTxt Known Answer Test");
                for (int k=0; k<`VARTXT_128_VEC_SIZE; k++)
                begin
                        set_kt(VarTxt_128_kt);
                        wait(ct_rdy);
                        set_ct(VarTxt_128_ct[k]);
                        wait(pt_vld);
                        $display("kt=%h ct=%h pt=%h expected=%h",VarTxt_128_kt,VarTxt_128_ct[k],pt,VarTxt_128_pt[k]);
                        if (pt != VarTxt_128_pt[k])
                        begin
                                $display("***Mismatch");
                                VarTxt_128_failed = 1;
                        end
                end
 
                $display("VarTxt Known Answer Test finished : %s", (VarTxt_128_failed)? "FAILED" : "PASSED");
                `WAIT_N_CLK(2);
 
                // VarKey Known Answer Test. AESAVS appendix E.1.
 
                $display("\nVarKey Known Answer Test");
                for (int k=0; k<`VARKEY_128_VEC_SIZE; k++)
                begin
                        set_kt(VarKey_128_kt[k]);
                        wait(ct_rdy);
                        set_ct(VarKey_128_ct[k]);
                        wait(pt_vld);
                        $display("kt=%h ct=%h pt=%h expected=%h",VarKey_128_kt[k],VarKey_128_ct[k],pt,VarKey_128_pt);
                        if (pt != VarKey_128_pt)
                        begin
                                $display("***Mismatch");
                                VarKey_128_failed = 1;
                        end
                end
 
                $display("VarKey Known Answer Test finished : %s", (VarKey_128_failed)? "FAILED" : "PASSED");
                `WAIT_N_CLK(2);
 
                // Random vector test against golden model.
 
                $display("\nRandom Vector Test");
                for (int k=0; k<1000; k++)
                begin
                        tmp_ct = rand128();
                        tmp_kt = rand128();
                        ref_model.KeyExpand(tmp_kt);
                        ref_model.LoadCt(tmp_ct);
                        ref_model.run(0);
 
                        wait (kt_rdy);
                        set_kt(tmp_kt);
                        wait (ct_rdy);
                        set_ct(tmp_ct);
                        wait (pt_vld);
                        $display("kt=%h ct=%h pt=%h expected=%h",tmp_kt,tmp_ct,pt,ref_model.GetState());
                        if (pt != ref_model.GetState())
                        begin
                                $display("***Mismatch");
                                RandVec_128_failed = 1;
                        failed = 1;
                        end
                end
 
                $display("Random Vector Test finished : %s", (RandVec_128_failed)? "FAILED" : "PASSED");
                `WAIT_N_CLK(2);
 
                $display("\nAll tests finished : %s", (failed)? "FAILED" : "OK");
 
                $stop;
        end
 
endmodule

Browse

Tools

Subversion Repositories aes_decrypt_fpga

[/] [aes_decrypt_fpga/] [trunk/] [bench/] [verilog/] [aes_decrypt128_tb.sv] - Blame information for rev 3

Line No.	Rev	Author	Line
1	3	schengopen	`////////////////////////////////////////////////////////////////// ////`
2			`//// ////`
3			`//// AES Decryption Core for FPGA ////`
4			`//// ////`
5			`//// This file is part of the AES Decryption Core for FPGA project ////`
6			`//// http://www.opencores.org/cores/xxx/ ////`
7			`//// ////`
8			`//// Description ////`
9			`//// Implementation of AES Decryption Core for FPGA according to ////`
10			`//// core specification document. ////`
11			`//// ////`
12			`//// To Do: ////`
13			`//// - ////`
14			`//// ////`
15			`//// Author(s): ////`
16			`//// - scheng, schengopencores@opencores.org ////`
17			`//// ////`
18			`//////////////////////////////////////////////////////////////////////`
19			`//// ////`
20			`//// Copyright (C) 2009 Authors and OPENCORES.ORG ////`
21			`//// ////`
22			`//// This source file may be used and distributed without ////`
23			`//// restriction provided that this copyright statement is not ////`
24			`//// removed from the file and that any derivative work contains ////`
25			`//// the original copyright notice and the associated disclaimer. ////`
26			`//// ////`
27			`//// This source file is free software; you can redistribute it ////`
28			`//// and/or modify it under the terms of the GNU Lesser General ////`
29			`//// Public License as published by the Free Software Foundation; ////`
30			`//// either version 2.1 of the License, or (at your option) any ////`
31			`//// later version. ////`
32			`//// ////`
33			`//// This source is distributed in the hope that it will be ////`
34			`//// useful, but WITHOUT ANY WARRANTY; without even the implied ////`
35			`//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////`
36			`//// PURPOSE. See the GNU Lesser General Public License for more ////`
37			`//// details. ////`
38			`//// ////`
39			`//// You should have received a copy of the GNU Lesser General ////`
40			`//// Public License along with this source; if not, download it ////`
41			`//// from http://www.opencores.org/lgpl.shtml ////`
42			`//// //// ///`
43			`///////////////////////////////////////////////////////////////////`
44			`//// ////`
45			`//// Testbench for 128-bit decryption ////`
46			`//// ////`
47			`////////////////////////////////////////////////////////////////////////`
48	2	schengopen	`timescale 1ns/1ps
49
50			`// Uncomment the following line if you're targetting Xilinx FPGA`
51			//`define XILINX 1
52
53			`// generic_muxfx.v defines a generic 2-to-1 MUX. This file is used to provide`
54			`// a generic definition of MUXF7 and MUXF8 in case you are not targetting Xilinx.`
55			`// When targetting Xilinx, skip this file to allow the simulator to locate the`
56			`// MUXF7 and MUXF8 in the Xilinx unisim library.`
57			`ifndef XILINX
58			`include "generic/generic_muxfx.v"
59			`endif
60
61			`include "InvSbox.sv"
62			`include "InvSubBytes.sv"
63			`include "InvShiftRows.sv"
64			`include "InvAddRoundKey.sv"
65			`include "gfmul.sv"
66			`include "InvMixCol_slice.sv"
67			`include "InvMixColumns.sv"
68			`include "decrypt.sv"
69			`include "KschBuffer.sv"
70			`include "Sbox.sv"
71			`include "SubWord.sv"
72			`include "RotWord.sv"
73			`include "KeyExpand128.sv"
74			`include "aes_decrypt128.sv"
75			`include "aes_beh_model.sv"
76
77			`define PERIOD 10
78			`define T (`PERIOD/2)
79			`define Tcko 1
80
81			`define WAIT_N_CLK(num_of_clk) repeat(num_of_clk) @(posedge clk); #(`Tcko)
82
83			`module aes_decrypt128_tb;`
84
85			`logic [0:127] ct;`
86			`logic ct_vld;`
87			`wire ct_rdy;`
88
89			`logic [0:127] kt;`
90			`logic kt_vld;`
91			`wire kt_rdy;`
92
93			`wire [0:127] pt;`
94			`wire pt_vld;`
95
96			`logic clk;`
97			`logic rst;`
98
99			`int sample_vec_failed = 0;`
100			`int back_to_back_failed = 0;`
101			`int RandVec_128_failed = 0;`
102			`int failed = 0;`
103
104			`aes128_decrypt_t ref_model;`
105
106			`logic [0:127] tmp_kt;`
107			`logic [0:127] tmp_ct;`
108
109			`include "decrypt_vec.sv"
110
111			`task set_kt(input [0:127] x);`
112			`kt = x;`
113			`kt_vld = 1;`
114			`WAIT_N_CLK(1);
115			`kt_vld = 0;`
116			`WAIT_N_CLK(1);
117			`endtask`
118
119			`task set_ct(input [0:127] x);`
120			`ct = x;`
121			`ct_vld = 1;`
122			`WAIT_N_CLK(1);
123			`ct_vld = 0;`
124			`WAIT_N_CLK(1);
125			`endtask`
126
127			`function logic [0:127] rand128;`
128			`rand128 = {$random, $random, $random, $random};`
129			`endfunction`
130
131			`always`
132			`begin`
133			`clk <= 1;`
134			#(`T);
135			`clk <= 0;`
136			#(`T);
137			`end`
138
139			`aes_decrypt128 uut(.*);`
140
141			`initial begin`
142			`ref_model = new;`
143
144			`rst = 1;`
145			`kt_vld = 0;`
146			`ct_vld = 0;`
147			`WAIT_N_CLK(3);
148
149			`rst = 0;`
150			`WAIT_N_CLK(1);
151
152			`// FIPS-197 sample vector test. FIPS-197 appendix C.1.`
153
154			`$display("FIPS-197 sample vector test");`
155			`$display("kt=000102030405060708090a0b0c0d0e0f ct=69c4e0d86a7b0430d8cdb78070b4c55a");`
156			`wait (kt_rdy);`
157			`set_kt(128'h000102030405060708090a0b0c0d0e0f);`
158			`wait (ct_rdy);`
159			`set_ct(128'h69c4e0d86a7b0430d8cdb78070b4c55a);`
160			`wait (pt_vld);`
161			`$display("pt=%h expected=00112233445566778899aabbccddeeff",pt);`
162			`if (pt != 128'h00112233445566778899aabbccddeeff)`
163			`begin`
164			`$display("***Mismatch");`
165			`sample_vec_failed = 1;`
166			`failed = 1;`
167			`end`
168			`$display("FIPS-197 sample vector test finished : %s", (sample_vec_failed)? "FAILED" : "PASSED");`
169			`WAIT_N_CLK(2);
170
171			`// Back-to-back ciphertext test.`
172			`// Two ciphertext are applied back-to-back with no dead cycle in between.`
173
174			`$display("\nBack-to-back ciphertext test");`
175			`tmp_ct = rand128();`
176			`tmp_kt = rand128();`
177			`ref_model.KeyExpand(tmp_kt);`
178			`ref_model.LoadCt(tmp_ct);`
179			`ref_model.run(0);`
180
181			`wait (kt_rdy);`
182			`set_kt(tmp_kt);`
183			`wait (ct_rdy);`
184			`set_ct(tmp_ct);`
185			`wait (pt_vld);`
186			`$display("kt=%h ct=%h pt=%h expected=%h",tmp_kt,tmp_ct,pt,ref_model.GetState());`
187			`if (pt != ref_model.GetState())`
188			`begin`
189			`$display("***Mismatch");`
190			`back_to_back_failed = 1;`
191			`failed = 1;`
192			`end`
193
194			`tmp_ct = rand128();`
195			`ref_model.LoadCt(tmp_ct);`
196			`ref_model.run(0);`
197			`wait (ct_rdy);`
198			`set_ct(tmp_ct);`
199			`wait (pt_vld);`
200			`$display("kt=%h ct=%h pt=%h expected=%h",tmp_kt,tmp_ct,pt,ref_model.GetState());`
201			`if (pt != ref_model.GetState())`
202			`begin`
203			`$display("***Mismatch");`
204			`back_to_back_failed = 1;`
205			`failed = 1;`
206			`end`
207
208			`$display("Back-to-back ciphertext test finished : %s", (back_to_back_failed)? "FAILED" : "PASSED");`
209			`WAIT_N_CLK(2);
210
211			`// ECB-AES128.Decrypt sample vector test. SP800-38a appendix F,1.2`
212
213			`$display("\nECB-AES128.Decrypt sample vector test");`
214			for (int k=0; k<`ECB_DECRYPT_128_VEC_SIZE; k++)
215			`begin`
216			`set_kt(ECBDecrypt_128_kt);`
217			`wait(ct_rdy);`
218			`set_ct(ECBDecrypt_128_ct[k]);`
219			`wait(pt_vld);`
220			`$display("kt=%h ct=%h pt=%h expected=%h",ECBDecrypt_128_kt,ECBDecrypt_128_ct[k],pt,ECBDecrypt_128_pt[k]);`
221			`if (pt != ECBDecrypt_128_pt[k])`
222			`begin`
223			`$display("***Mismatch");`
224			`ECBDecrypt_128_failed = 1;`
225			`end`
226			`end`
227
228			`$display("ECB-AES128.Decrypt sample vector test finished : %s", (ECBDecrypt_128_failed)? "FAILED" : "PASSED");`
229			`WAIT_N_CLK(2);
230
231			`// GFSbox Known Answer Test. AESAVS appendix B.1.`
232
233			`$display("\nGFSbox Known Answer Test");`
234			for (int k=0; k<`GFSbox_128_VEC_SIZE; k++)
235			`begin`
236			`set_kt(GFSbox_128_kt);`
237			`wait(ct_rdy);`
238			`set_ct(GFSbox_128_ct[k]);`
239			`wait(pt_vld);`
240			`$display("kt=%h ct=%h pt=%h expected=%h",GFSbox_128_kt,GFSbox_128_ct[k],pt,GFSbox_128_pt[k]);`
241			`if (pt != GFSbox_128_pt[k])`
242			`begin`
243			`$display("***Mismatch");`
244			`GFSbox_128_failed = 1;`
245			`end`
246			`end`
247
248			`$display("GFSbox test finished : %s", (GFSbox_128_failed)? "FAILED" : "PASSED");`
249			`WAIT_N_CLK(2);
250
251			`// KeySbox Known Answer Test. AESAVS appendix C.1.`
252
253			`$display("\nKeySbox Known Answer Test");`
254			for (int k=0; k<`KEYSBOX_128_VEC_SIZE; k++)
255			`begin`
256			`set_kt(KeySbox_128_kt[k]);`
257			`wait(ct_rdy);`
258			`set_ct(KeySbox_128_ct[k]);`
259			`wait(pt_vld);`
260			`$display("kt=%h ct=%h pt=%h expected=%h",KeySbox_128_kt[k],KeySbox_128_ct[k],pt,KeySbox_128_pt);`
261			`if (pt != KeySbox_128_pt[k])`
262			`begin`
263			`$display("***Mismatch");`
264			`KeySbox_128_failed = 1;`
265			`end`
266			`end`
267
268			`$display("KeySbox test finished : %s", (KeySbox_128_failed)? "FAILED" : "PASSED");`
269			`WAIT_N_CLK(2);
270
271			`// VarTxt Known Answer Test. AESAVS appendix D.1.`
272
273			`$display("\nVarTxt Known Answer Test");`
274			for (int k=0; k<`VARTXT_128_VEC_SIZE; k++)
275			`begin`
276			`set_kt(VarTxt_128_kt);`
277			`wait(ct_rdy);`
278			`set_ct(VarTxt_128_ct[k]);`
279			`wait(pt_vld);`
280			`$display("kt=%h ct=%h pt=%h expected=%h",VarTxt_128_kt,VarTxt_128_ct[k],pt,VarTxt_128_pt[k]);`
281			`if (pt != VarTxt_128_pt[k])`
282			`begin`
283			`$display("***Mismatch");`
284			`VarTxt_128_failed = 1;`
285			`end`
286			`end`
287
288			`$display("VarTxt Known Answer Test finished : %s", (VarTxt_128_failed)? "FAILED" : "PASSED");`
289			`WAIT_N_CLK(2);
290
291			`// VarKey Known Answer Test. AESAVS appendix E.1.`
292
293			`$display("\nVarKey Known Answer Test");`
294			for (int k=0; k<`VARKEY_128_VEC_SIZE; k++)
295			`begin`
296			`set_kt(VarKey_128_kt[k]);`
297			`wait(ct_rdy);`
298			`set_ct(VarKey_128_ct[k]);`
299			`wait(pt_vld);`
300			`$display("kt=%h ct=%h pt=%h expected=%h",VarKey_128_kt[k],VarKey_128_ct[k],pt,VarKey_128_pt);`
301			`if (pt != VarKey_128_pt)`
302			`begin`
303			`$display("***Mismatch");`
304			`VarKey_128_failed = 1;`
305			`end`
306			`end`
307
308			`$display("VarKey Known Answer Test finished : %s", (VarKey_128_failed)? "FAILED" : "PASSED");`
309			`WAIT_N_CLK(2);
310
311			`// Random vector test against golden model.`
312
313			`$display("\nRandom Vector Test");`
314			`for (int k=0; k<1000; k++)`
315			`begin`
316			`tmp_ct = rand128();`
317			`tmp_kt = rand128();`
318			`ref_model.KeyExpand(tmp_kt);`
319			`ref_model.LoadCt(tmp_ct);`
320			`ref_model.run(0);`
321
322			`wait (kt_rdy);`
323			`set_kt(tmp_kt);`
324			`wait (ct_rdy);`
325			`set_ct(tmp_ct);`
326			`wait (pt_vld);`
327			`$display("kt=%h ct=%h pt=%h expected=%h",tmp_kt,tmp_ct,pt,ref_model.GetState());`
328			`if (pt != ref_model.GetState())`
329			`begin`
330			`$display("***Mismatch");`
331			`RandVec_128_failed = 1;`
332			`failed = 1;`
333			`end`
334			`end`
335
336			`$display("Random Vector Test finished : %s", (RandVec_128_failed)? "FAILED" : "PASSED");`
337			`WAIT_N_CLK(2);
338
339			`$display("\nAll tests finished : %s", (failed)? "FAILED" : "OK");`
340
341			`$stop;`
342			`end`
343
344			`endmodule`