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[/] [aes_decrypt_fpga/] [trunk/] [bench/] [verilog/] [aes_decrypt192_tb.sv] - Blame information for rev 3

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////////////////////////////////////////////////////////////////// ////
////                                                                                                                            ////
//// AES Decryption Core for FPGA                                                                       ////
////                                                                                                                            ////
//// This file is part of the AES Decryption Core for FPGA project      ////
//// http://www.opencores.org/cores/xxx/                                                        ////
////                                                                                                                            ////
//// Description                                                                                                        ////
//// Implementation of  AES Decryption Core for FPGA according to       ////
//// core specification document.                                                                       ////
////                                                                                                                            ////
//// To Do:                                                                                                             ////
//// -                                                                                                                          ////
////                                                                                                                            ////
//// Author(s):                                                                                                         ////
//// - scheng, schengopencores@opencores.org                                            ////
////                                                                                                                            ////
//////////////////////////////////////////////////////////////////////
////                                                                                                                            ////
//// Copyright (C) 2009 Authors and OPENCORES.ORG                                       ////
////                                                                                                                            ////
//// This source file may be used and distributed without                       ////
//// restriction provided that this copyright statement is not          ////
//// removed from the file and that any derivative work contains        ////
//// the original copyright notice and the associated disclaimer.       ////
////                                                                                                                            ////
//// This source file is free software; you can redistribute it         ////
//// and/or modify it under the terms of the GNU Lesser General         ////
//// Public License as published by the Free Software Foundation;       ////
//// either version 2.1 of the License, or (at your option) any         ////
//// later version.                                                                                             ////
////                                                                                                                            ////
//// This source is distributed in the hope that it will be             ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied         ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR            ////
//// PURPOSE. See the GNU Lesser General Public License for more        ////
//// details.                                                                                                           ////
////                                                                                                                            ////
//// You should have received a copy of the GNU Lesser General          ////
//// Public License along with this source; if not, download it         ////
//// from http://www.opencores.org/lgpl.shtml                                           ////
////                                                                                                                            //// ///
///////////////////////////////////////////////////////////////////
////                                                                                                                            ////
//// Testbench for 192-bit decryption                                                           ////
////                                                                                                                            ////
////////////////////////////////////////////////////////////////////////
`timescale 1ns/1ps
 
// Uncomment the following line if you're targetting Xilinx FPGA
//`define XILINX 1
 
// generic_muxfx.v defines a generic 2-to-1 MUX. This file is used to provide
// a generic definition of MUXF7 and MUXF8 in case you are not targetting Xilinx.
// When targetting Xilinx, skip this file to allow the simulator to locate the
// MUXF7 and MUXF8 in the Xilinx unisim library.
`ifndef XILINX
`include "generic/generic_muxfx.v"
`endif
 
`include "InvSbox.sv"
`include "InvSubBytes.sv"
`include "InvShiftRows.sv"
`include "InvAddRoundKey.sv"
`include "gfmul.sv"
`include "InvMixCol_slice.sv"
`include "InvMixColumns.sv"
`include "decrypt.sv"
`include "KschBuffer.sv"
`include "Sbox.sv"
`include "SubWord.sv"
`include "RotWord.sv"
`include "KeyExpand192.sv"
`include "aes_decrypt192.sv"
`include "aes_beh_model.sv"
 
`define PERIOD 10
`define T (`PERIOD/2)
`define Tcko 1
 
`define WAIT_N_CLK(num_of_clk) repeat(num_of_clk) @(posedge clk); #(`Tcko)
 
module aes_decrypt192_tb;
 
        logic   [0:127] ct;
        logic   ct_vld;
        wire    ct_rdy;
 
        logic   [0:191] kt;
        logic   kt_vld;
        wire    kt_rdy;
 
        wire    [0:127] pt;
        wire    pt_vld;
 
        logic   clk;
        logic   rst;
 
        int     sample_vec_failed = 0;
        int     back_to_back_failed = 0;
        int     RandVec_192_failed = 0;
        int     failed = 0;
 
        aes192_decrypt_t ref_model;
 
        logic   [0:191] tmp_kt;
        logic   [0:127] tmp_ct;
 
        `include "decrypt_vec.sv"
 
        task set_kt(input [0:191] x);
                kt = x;
                kt_vld = 1;
                `WAIT_N_CLK(1);
                kt_vld = 0;
                `WAIT_N_CLK(1);
        endtask
 
        task set_ct(input [0:127] x);
                ct = x;
                ct_vld = 1;
                `WAIT_N_CLK(1);
                ct_vld = 0;
                `WAIT_N_CLK(1);
        endtask
 
        function logic [0:127] rand128;
                rand128 = {$random, $random, $random, $random};
        endfunction
 
 
        function logic [0:191] rand192;
                rand192 = {$random, $random, $random, $random, $random, $random};
        endfunction
 
        always
        begin
                clk <= 1;
                #(`T);
                clk <= 0;
                #(`T);
        end
 
        aes_decrypt192 uut(.*);
 
        initial begin
                ref_model = new;
 
                rst = 1;
                kt_vld = 0;
                ct_vld = 0;
                `WAIT_N_CLK(3);
 
                rst = 0;
                `WAIT_N_CLK(1);
 
                // FIPS-197 sample vector test. FIPS-197 appendix C.2.
 
                $display("FIPS-197 sample vector test");
                $display("kt=000102030405060708090a0b0c0d0e0f1011121314151617 ct=dda97ca4864cdfe06eaf70a0ec0d7191");
                wait (kt_rdy);
                set_kt(192'h000102030405060708090a0b0c0d0e0f1011121314151617);
                wait (ct_rdy);
                set_ct(128'hdda97ca4864cdfe06eaf70a0ec0d7191);
                wait (pt_vld);
                $display("pt=%h expected=00112233445566778899aabbccddeeff",pt);
                if (pt != 128'h00112233445566778899aabbccddeeff)
                begin
                        $display("***Mismatch");
                        sample_vec_failed = 1;
                        failed = 1;
                end
                $display("FIPS-197 sample vector test finished : %s", (sample_vec_failed)? "FAILED" : "PASSED");
                `WAIT_N_CLK(2);
 
                // Back-to-back ciphertext test.
                // Two ciphertext are applied back-to-back with no dead cycle in between.
 
                $display("\nBack-to-back ciphertext test");
                tmp_ct = rand128();
                tmp_kt = rand192();
                ref_model.KeyExpand(tmp_kt);
                ref_model.LoadCt(tmp_ct);
                ref_model.run(0);
 
                wait (kt_rdy);
                set_kt(tmp_kt);
                wait (ct_rdy);
                set_ct(tmp_ct);
                wait (pt_vld);
                $display("kt=%h ct=%h pt=%h expected=%h",tmp_kt,tmp_ct,pt,ref_model.GetState());
                if (pt != ref_model.GetState())
                begin
                        $display("***Mismatch");
                        back_to_back_failed = 1;
                        failed = 1;
                end
 
                tmp_ct = rand128();
                ref_model.LoadCt(tmp_ct);
                ref_model.run(0);
                wait (ct_rdy);
                set_ct(tmp_ct);
                wait (pt_vld);
                $display("kt=%h ct=%h pt=%h expected=%h",tmp_kt,tmp_ct,pt,ref_model.GetState());
                if (pt != ref_model.GetState())
                begin
                        $display("***Mismatch");
                        back_to_back_failed = 1;
                        failed = 1;
                end
 
                $display("Back-to-back ciphertext test finished : %s", (back_to_back_failed)? "FAILED" : "PASSED");
                `WAIT_N_CLK(2);
 
                // ECB-AES192.Decrypt sample vector test. SP800-38a appendix F.1.4
 
                $display("\nECB-AES192.Decrypt sample vector test");
                for (int k=0; k<`ECB_DECRYPT_192_VEC_SIZE; k++)
                begin
                        set_kt(ECBDecrypt_192_kt);
                        wait(ct_rdy);
                        set_ct(ECBDecrypt_192_ct[k]);
                        wait(pt_vld);
                        $display("kt=%h ct=%h pt=%h expected=%h",ECBDecrypt_192_kt,ECBDecrypt_192_ct[k],pt,ECBDecrypt_192_pt[k]);
                        if (pt != ECBDecrypt_192_pt[k])
                        begin
                                $display("***Mismatch");
                                ECBDecrypt_192_failed = 1;
                        end
                end
 
                $display("ECB-AES192.Decrypt sample vector test finished : %s", (ECBDecrypt_192_failed)? "FAILED" : "PASSED");
                `WAIT_N_CLK(2);
 
                // GFSbox Known Answer Test. AESAVS appendix B.2.
 
                $display("\nGFSbox Known Answer Test");
                for (int k=0; k<`GFSbox_192_VEC_SIZE; k++)
                begin
                        set_kt(GFSbox_192_kt);
                        wait(ct_rdy);
                        set_ct(GFSbox_192_ct[k]);
                        wait(pt_vld);
                        $display("kt=%h ct=%h pt=%h expected=%h",GFSbox_192_kt,GFSbox_192_ct[k],pt,GFSbox_192_pt[k]);
                        if (pt != GFSbox_192_pt[k])
                        begin
                                $display("***Mismatch");
                                GFSbox_192_failed = 1;
                        end
                end
 
                $display("GFSbox test finished : %s", (GFSbox_192_failed)? "FAILED" : "PASSED");
                `WAIT_N_CLK(2);
 
                // KeySbox Known Answer Test. AESAVS appendix C.2.
 
                $display("\nKeySbox Known Answer Test");
                for (int k=0; k<`KEYSBOX_192_VEC_SIZE; k++)
                begin
                        set_kt(KeySbox_192_kt[k]);
                        wait(ct_rdy);
                        set_ct(KeySbox_192_ct[k]);
                        wait(pt_vld);
                        $display("kt=%h ct=%h pt=%h expected=%h",KeySbox_192_kt[k],KeySbox_192_ct[k],pt,KeySbox_192_pt);
                        if (pt != KeySbox_192_pt[k])
                        begin
                                $display("***Mismatch");
                                KeySbox_192_failed = 1;
                        end
                end
 
                $display("KeySbox test finished : %s", (KeySbox_192_failed)? "FAILED" : "PASSED");
                `WAIT_N_CLK(2);
 
                // VarTxt Known Answer Test. AESAVS appendix D.2.
 
                $display("\nVarTxt Known Answer Test");
                for (int k=0; k<`VARTXT_192_VEC_SIZE; k++)
                begin
                        set_kt(VarTxt_192_kt);
                        wait(ct_rdy);
                        set_ct(VarTxt_192_ct[k]);
                        wait(pt_vld);
                        $display("kt=%h ct=%h pt=%h expected=%h",VarTxt_192_kt,VarTxt_192_ct[k],pt,VarTxt_192_pt[k]);
                        if (pt != VarTxt_192_pt[k])
                        begin
                                $display("***Mismatch");
                                VarTxt_192_failed = 1;
                        end
                end
 
                $display("VarTxt Known Answer Test finished : %s", (VarTxt_192_failed)? "FAILED" : "PASSED");
                `WAIT_N_CLK(2);
 
                // VarKey Known Answer Test. AESAVS appendix E.2.
 
                $display("\nVarKey Known Answer Test");
                for (int k=0; k<`VARKEY_192_VEC_SIZE; k++)
                begin
                        set_kt(VarKey_192_kt[k]);
                        wait(ct_rdy);
                        set_ct(VarKey_192_ct[k]);
                        wait(pt_vld);
                        $display("kt=%h ct=%h pt=%h expected=%h",VarKey_192_kt[k],VarKey_192_ct[k],pt,VarKey_192_pt);
                        if (pt != VarKey_192_pt)
                        begin
                                $display("***Mismatch");
                                VarKey_192_failed = 1;
                        end
                end
 
                $display("VarKey Known Answer Test finished : %s", (VarKey_192_failed)? "FAILED" : "PASSED");
                `WAIT_N_CLK(2);
 
 
                // Random vector test against golden model.
 
                $display("\nRandom Vector Test");
                for (int k=0; k<1000; k++)
                begin
                        tmp_ct = rand128();
                        tmp_kt = rand192();
                        ref_model.KeyExpand(tmp_kt);
                        ref_model.LoadCt(tmp_ct);
                        ref_model.run(0);
 
                        wait (kt_rdy);
                        set_kt(tmp_kt);
                        wait (ct_rdy);
                        set_ct(tmp_ct);
                        wait (pt_vld);
                        $display("kt=%h ct=%h pt=%h expected=%h",tmp_kt,tmp_ct,pt,ref_model.GetState());
                        if (pt != ref_model.GetState())
                        begin
                                $display("***Mismatch");
                                RandVec_192_failed = 1;
                        failed = 1;
                        end
                end
 
                $display("Random Vector Test finished : %s", (RandVec_192_failed)? "FAILED" : "PASSED");
                `WAIT_N_CLK(2);
 
                $display("\nAll tests finished : %s", (failed)? "FAILED" : "OK");
 
                $stop;
        end
 
endmodule

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Subversion Repositories aes_decrypt_fpga

[/] [aes_decrypt_fpga/] [trunk/] [bench/] [verilog/] [aes_decrypt192_tb.sv] - Blame information for rev 3

Line No.	Rev	Author	Line
1	3	schengopen	`////////////////////////////////////////////////////////////////// ////`
2			`//// ////`
3			`//// AES Decryption Core for FPGA ////`
4			`//// ////`
5			`//// This file is part of the AES Decryption Core for FPGA project ////`
6			`//// http://www.opencores.org/cores/xxx/ ////`
7			`//// ////`
8			`//// Description ////`
9			`//// Implementation of AES Decryption Core for FPGA according to ////`
10			`//// core specification document. ////`
11			`//// ////`
12			`//// To Do: ////`
13			`//// - ////`
14			`//// ////`
15			`//// Author(s): ////`
16			`//// - scheng, schengopencores@opencores.org ////`
17			`//// ////`
18			`//////////////////////////////////////////////////////////////////////`
19			`//// ////`
20			`//// Copyright (C) 2009 Authors and OPENCORES.ORG ////`
21			`//// ////`
22			`//// This source file may be used and distributed without ////`
23			`//// restriction provided that this copyright statement is not ////`
24			`//// removed from the file and that any derivative work contains ////`
25			`//// the original copyright notice and the associated disclaimer. ////`
26			`//// ////`
27			`//// This source file is free software; you can redistribute it ////`
28			`//// and/or modify it under the terms of the GNU Lesser General ////`
29			`//// Public License as published by the Free Software Foundation; ////`
30			`//// either version 2.1 of the License, or (at your option) any ////`
31			`//// later version. ////`
32			`//// ////`
33			`//// This source is distributed in the hope that it will be ////`
34			`//// useful, but WITHOUT ANY WARRANTY; without even the implied ////`
35			`//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////`
36			`//// PURPOSE. See the GNU Lesser General Public License for more ////`
37			`//// details. ////`
38			`//// ////`
39			`//// You should have received a copy of the GNU Lesser General ////`
40			`//// Public License along with this source; if not, download it ////`
41			`//// from http://www.opencores.org/lgpl.shtml ////`
42			`//// //// ///`
43			`///////////////////////////////////////////////////////////////////`
44			`//// ////`
45			`//// Testbench for 192-bit decryption ////`
46			`//// ////`
47			`////////////////////////////////////////////////////////////////////////`
48	2	schengopen	`timescale 1ns/1ps
49
50			`// Uncomment the following line if you're targetting Xilinx FPGA`
51			//`define XILINX 1
52
53			`// generic_muxfx.v defines a generic 2-to-1 MUX. This file is used to provide`
54			`// a generic definition of MUXF7 and MUXF8 in case you are not targetting Xilinx.`
55			`// When targetting Xilinx, skip this file to allow the simulator to locate the`
56			`// MUXF7 and MUXF8 in the Xilinx unisim library.`
57			`ifndef XILINX
58			`include "generic/generic_muxfx.v"
59			`endif
60
61			`include "InvSbox.sv"
62			`include "InvSubBytes.sv"
63			`include "InvShiftRows.sv"
64			`include "InvAddRoundKey.sv"
65			`include "gfmul.sv"
66			`include "InvMixCol_slice.sv"
67			`include "InvMixColumns.sv"
68			`include "decrypt.sv"
69			`include "KschBuffer.sv"
70			`include "Sbox.sv"
71			`include "SubWord.sv"
72			`include "RotWord.sv"
73			`include "KeyExpand192.sv"
74			`include "aes_decrypt192.sv"
75			`include "aes_beh_model.sv"
76
77			`define PERIOD 10
78			`define T (`PERIOD/2)
79			`define Tcko 1
80
81			`define WAIT_N_CLK(num_of_clk) repeat(num_of_clk) @(posedge clk); #(`Tcko)
82
83			`module aes_decrypt192_tb;`
84
85			`logic [0:127] ct;`
86			`logic ct_vld;`
87			`wire ct_rdy;`
88
89			`logic [0:191] kt;`
90			`logic kt_vld;`
91			`wire kt_rdy;`
92
93			`wire [0:127] pt;`
94			`wire pt_vld;`
95
96			`logic clk;`
97			`logic rst;`
98
99			`int sample_vec_failed = 0;`
100			`int back_to_back_failed = 0;`
101			`int RandVec_192_failed = 0;`
102			`int failed = 0;`
103
104			`aes192_decrypt_t ref_model;`
105
106			`logic [0:191] tmp_kt;`
107			`logic [0:127] tmp_ct;`
108
109			`include "decrypt_vec.sv"
110
111			`task set_kt(input [0:191] x);`
112			`kt = x;`
113			`kt_vld = 1;`
114			`WAIT_N_CLK(1);
115			`kt_vld = 0;`
116			`WAIT_N_CLK(1);
117			`endtask`
118
119			`task set_ct(input [0:127] x);`
120			`ct = x;`
121			`ct_vld = 1;`
122			`WAIT_N_CLK(1);
123			`ct_vld = 0;`
124			`WAIT_N_CLK(1);
125			`endtask`
126
127			`function logic [0:127] rand128;`
128			`rand128 = {$random, $random, $random, $random};`
129			`endfunction`
130
131
132			`function logic [0:191] rand192;`
133			`rand192 = {$random, $random, $random, $random, $random, $random};`
134			`endfunction`
135
136			`always`
137			`begin`
138			`clk <= 1;`
139			#(`T);
140			`clk <= 0;`
141			#(`T);
142			`end`
143
144			`aes_decrypt192 uut(.*);`
145
146			`initial begin`
147			`ref_model = new;`
148
149			`rst = 1;`
150			`kt_vld = 0;`
151			`ct_vld = 0;`
152			`WAIT_N_CLK(3);
153
154			`rst = 0;`
155			`WAIT_N_CLK(1);
156
157			`// FIPS-197 sample vector test. FIPS-197 appendix C.2.`
158
159			`$display("FIPS-197 sample vector test");`
160			`$display("kt=000102030405060708090a0b0c0d0e0f1011121314151617 ct=dda97ca4864cdfe06eaf70a0ec0d7191");`
161			`wait (kt_rdy);`
162			`set_kt(192'h000102030405060708090a0b0c0d0e0f1011121314151617);`
163			`wait (ct_rdy);`
164			`set_ct(128'hdda97ca4864cdfe06eaf70a0ec0d7191);`
165			`wait (pt_vld);`
166			`$display("pt=%h expected=00112233445566778899aabbccddeeff",pt);`
167			`if (pt != 128'h00112233445566778899aabbccddeeff)`
168			`begin`
169			`$display("***Mismatch");`
170			`sample_vec_failed = 1;`
171			`failed = 1;`
172			`end`
173			`$display("FIPS-197 sample vector test finished : %s", (sample_vec_failed)? "FAILED" : "PASSED");`
174			`WAIT_N_CLK(2);
175
176			`// Back-to-back ciphertext test.`
177			`// Two ciphertext are applied back-to-back with no dead cycle in between.`
178
179			`$display("\nBack-to-back ciphertext test");`
180			`tmp_ct = rand128();`
181			`tmp_kt = rand192();`
182			`ref_model.KeyExpand(tmp_kt);`
183			`ref_model.LoadCt(tmp_ct);`
184			`ref_model.run(0);`
185
186			`wait (kt_rdy);`
187			`set_kt(tmp_kt);`
188			`wait (ct_rdy);`
189			`set_ct(tmp_ct);`
190			`wait (pt_vld);`
191			`$display("kt=%h ct=%h pt=%h expected=%h",tmp_kt,tmp_ct,pt,ref_model.GetState());`
192			`if (pt != ref_model.GetState())`
193			`begin`
194			`$display("***Mismatch");`
195			`back_to_back_failed = 1;`
196			`failed = 1;`
197			`end`
198
199			`tmp_ct = rand128();`
200			`ref_model.LoadCt(tmp_ct);`
201			`ref_model.run(0);`
202			`wait (ct_rdy);`
203			`set_ct(tmp_ct);`
204			`wait (pt_vld);`
205			`$display("kt=%h ct=%h pt=%h expected=%h",tmp_kt,tmp_ct,pt,ref_model.GetState());`
206			`if (pt != ref_model.GetState())`
207			`begin`
208			`$display("***Mismatch");`
209			`back_to_back_failed = 1;`
210			`failed = 1;`
211			`end`
212
213			`$display("Back-to-back ciphertext test finished : %s", (back_to_back_failed)? "FAILED" : "PASSED");`
214			`WAIT_N_CLK(2);
215
216			`// ECB-AES192.Decrypt sample vector test. SP800-38a appendix F.1.4`
217
218			`$display("\nECB-AES192.Decrypt sample vector test");`
219			for (int k=0; k<`ECB_DECRYPT_192_VEC_SIZE; k++)
220			`begin`
221			`set_kt(ECBDecrypt_192_kt);`
222			`wait(ct_rdy);`
223			`set_ct(ECBDecrypt_192_ct[k]);`
224			`wait(pt_vld);`
225			`$display("kt=%h ct=%h pt=%h expected=%h",ECBDecrypt_192_kt,ECBDecrypt_192_ct[k],pt,ECBDecrypt_192_pt[k]);`
226			`if (pt != ECBDecrypt_192_pt[k])`
227			`begin`
228			`$display("***Mismatch");`
229			`ECBDecrypt_192_failed = 1;`
230			`end`
231			`end`
232
233			`$display("ECB-AES192.Decrypt sample vector test finished : %s", (ECBDecrypt_192_failed)? "FAILED" : "PASSED");`
234			`WAIT_N_CLK(2);
235
236			`// GFSbox Known Answer Test. AESAVS appendix B.2.`
237
238			`$display("\nGFSbox Known Answer Test");`
239			for (int k=0; k<`GFSbox_192_VEC_SIZE; k++)
240			`begin`
241			`set_kt(GFSbox_192_kt);`
242			`wait(ct_rdy);`
243			`set_ct(GFSbox_192_ct[k]);`
244			`wait(pt_vld);`
245			`$display("kt=%h ct=%h pt=%h expected=%h",GFSbox_192_kt,GFSbox_192_ct[k],pt,GFSbox_192_pt[k]);`
246			`if (pt != GFSbox_192_pt[k])`
247			`begin`
248			`$display("***Mismatch");`
249			`GFSbox_192_failed = 1;`
250			`end`
251			`end`
252
253			`$display("GFSbox test finished : %s", (GFSbox_192_failed)? "FAILED" : "PASSED");`
254			`WAIT_N_CLK(2);
255
256			`// KeySbox Known Answer Test. AESAVS appendix C.2.`
257
258			`$display("\nKeySbox Known Answer Test");`
259			for (int k=0; k<`KEYSBOX_192_VEC_SIZE; k++)
260			`begin`
261			`set_kt(KeySbox_192_kt[k]);`
262			`wait(ct_rdy);`
263			`set_ct(KeySbox_192_ct[k]);`
264			`wait(pt_vld);`
265			`$display("kt=%h ct=%h pt=%h expected=%h",KeySbox_192_kt[k],KeySbox_192_ct[k],pt,KeySbox_192_pt);`
266			`if (pt != KeySbox_192_pt[k])`
267			`begin`
268			`$display("***Mismatch");`
269			`KeySbox_192_failed = 1;`
270			`end`
271			`end`
272
273			`$display("KeySbox test finished : %s", (KeySbox_192_failed)? "FAILED" : "PASSED");`
274			`WAIT_N_CLK(2);
275
276			`// VarTxt Known Answer Test. AESAVS appendix D.2.`
277
278			`$display("\nVarTxt Known Answer Test");`
279			for (int k=0; k<`VARTXT_192_VEC_SIZE; k++)
280			`begin`
281			`set_kt(VarTxt_192_kt);`
282			`wait(ct_rdy);`
283			`set_ct(VarTxt_192_ct[k]);`
284			`wait(pt_vld);`
285			`$display("kt=%h ct=%h pt=%h expected=%h",VarTxt_192_kt,VarTxt_192_ct[k],pt,VarTxt_192_pt[k]);`
286			`if (pt != VarTxt_192_pt[k])`
287			`begin`
288			`$display("***Mismatch");`
289			`VarTxt_192_failed = 1;`
290			`end`
291			`end`
292
293			`$display("VarTxt Known Answer Test finished : %s", (VarTxt_192_failed)? "FAILED" : "PASSED");`
294			`WAIT_N_CLK(2);
295
296			`// VarKey Known Answer Test. AESAVS appendix E.2.`
297
298			`$display("\nVarKey Known Answer Test");`
299			for (int k=0; k<`VARKEY_192_VEC_SIZE; k++)
300			`begin`
301			`set_kt(VarKey_192_kt[k]);`
302			`wait(ct_rdy);`
303			`set_ct(VarKey_192_ct[k]);`
304			`wait(pt_vld);`
305			`$display("kt=%h ct=%h pt=%h expected=%h",VarKey_192_kt[k],VarKey_192_ct[k],pt,VarKey_192_pt);`
306			`if (pt != VarKey_192_pt)`
307			`begin`
308			`$display("***Mismatch");`
309			`VarKey_192_failed = 1;`
310			`end`
311			`end`
312
313			`$display("VarKey Known Answer Test finished : %s", (VarKey_192_failed)? "FAILED" : "PASSED");`
314			`WAIT_N_CLK(2);
315
316
317			`// Random vector test against golden model.`
318
319			`$display("\nRandom Vector Test");`
320			`for (int k=0; k<1000; k++)`
321			`begin`
322			`tmp_ct = rand128();`
323			`tmp_kt = rand192();`
324			`ref_model.KeyExpand(tmp_kt);`
325			`ref_model.LoadCt(tmp_ct);`
326			`ref_model.run(0);`
327
328			`wait (kt_rdy);`
329			`set_kt(tmp_kt);`
330			`wait (ct_rdy);`
331			`set_ct(tmp_ct);`
332			`wait (pt_vld);`
333			`$display("kt=%h ct=%h pt=%h expected=%h",tmp_kt,tmp_ct,pt,ref_model.GetState());`
334			`if (pt != ref_model.GetState())`
335			`begin`
336			`$display("***Mismatch");`
337			`RandVec_192_failed = 1;`
338			`failed = 1;`
339			`end`
340			`end`
341
342			`$display("Random Vector Test finished : %s", (RandVec_192_failed)? "FAILED" : "PASSED");`
343			`WAIT_N_CLK(2);
344
345			`$display("\nAll tests finished : %s", (failed)? "FAILED" : "OK");`
346
347			`$stop;`
348			`end`
349
350			`endmodule`