Subversion Repositories alpha_blender

----------------------------------------------------------------------------------

-- Company: 

-- Engineer: 

-- 

-- Create Date:    21:32:03 04/27/2022 

-- Design Name: 

-- Module Name:    half_adder - Behavioral 

-- Project Name: 

-- Target Devices: 

-- Tool versions: 

-- Description: 

--

-- Dependencies: 

--

-- Revision: 

-- Revision 0.01 - File Created

-- Additional Comments: 

--

----------------------------------------------------------------------------------

library IEEE;

use IEEE.STD_LOGIC_1164.ALL;

-- Uncomment the following library declaration if using

-- arithmetic functions with Signed or Unsigned values

--use IEEE.NUMERIC_STD.ALL;

-- Uncomment the following library declaration if instantiating

-- any Xilinx primitives in this code.

--library UNISIM;

--use UNISIM.VComponents.all;

entity half_adder is

    Port ( a : in  STD_LOGIC;

           b : in  STD_LOGIC;

           cin : in  STD_LOGIC;

           sum : out  STD_LOGIC);

end half_adder;

architecture Behavioral of half_adder is

begin

sum <= (a xor b) xor cin;

end Behavioral;