1 |
2 |
hamidrm |
library IEEE;
|
2 |
|
|
use IEEE.STD_LOGIC_1164.ALL;
|
3 |
|
|
|
4 |
|
|
entity mul5x7 is
|
5 |
|
|
Port ( a : in STD_LOGIC_VECTOR (6 downto 0);
|
6 |
|
|
b : in STD_LOGIC_VECTOR (4 downto 0);
|
7 |
|
|
c : out STD_LOGIC_VECTOR (11 downto 0));
|
8 |
|
|
end mul5x7;
|
9 |
|
|
|
10 |
|
|
architecture Behavioral of mul5x7 is
|
11 |
|
|
|
12 |
|
|
signal ab0, ab1, ab2, ab3, ab4 : STD_LOGIC_VECTOR (6 downto 0);
|
13 |
|
|
signal c0, c1 : STD_LOGIC_VECTOR (6 downto 0);
|
14 |
|
|
signal s0, s1 : STD_LOGIC_VECTOR (7 downto 0);
|
15 |
|
|
signal r1, r2, r3, r4 : STD_LOGIC_VECTOR (11 downto 0);
|
16 |
|
|
signal rc1, rc2 : STD_LOGIC_VECTOR (10 downto 0);
|
17 |
|
|
|
18 |
|
|
component full_adder
|
19 |
|
|
Port ( a : in STD_LOGIC;
|
20 |
|
|
b : in STD_LOGIC;
|
21 |
|
|
cin : in STD_LOGIC;
|
22 |
|
|
cout : out STD_LOGIC;
|
23 |
|
|
sum : out STD_LOGIC);
|
24 |
|
|
end component;
|
25 |
|
|
|
26 |
|
|
begin
|
27 |
|
|
ab0(0) <= a(0) and b(0); ab0(1) <= a(1) and b(0); ab0(2) <= a(2) and b(0);
|
28 |
|
|
ab0(3) <= a(3) and b(0); ab0(4) <= a(4) and b(0); ab0(5) <= a(5) and b(0);
|
29 |
|
|
ab0(6) <= a(6) and b(0);
|
30 |
|
|
ab1(0) <= a(0) and b(1); ab1(1) <= a(1) and b(1); ab1(2) <= a(2) and b(1);
|
31 |
|
|
ab1(3) <= a(3) and b(1); ab1(4) <= a(4) and b(1); ab1(5) <= a(5) and b(1);
|
32 |
|
|
ab1(6) <= a(6) and b(1);
|
33 |
|
|
ab2(0) <= a(0) and b(2); ab2(1) <= a(1) and b(2); ab2(2) <= a(2) and b(2);
|
34 |
|
|
ab2(3) <= a(3) and b(2); ab2(4) <= a(4) and b(2); ab2(5) <= a(5) and b(2);
|
35 |
|
|
ab2(6) <= a(6) and b(2);
|
36 |
|
|
ab3(0) <= a(0) and b(3); ab3(1) <= a(1) and b(3); ab3(2) <= a(2) and b(3);
|
37 |
|
|
ab3(3) <= a(3) and b(3); ab3(4) <= a(4) and b(3); ab3(5) <= a(5) and b(3);
|
38 |
|
|
ab3(6) <= a(6) and b(3);
|
39 |
|
|
ab4(0) <= a(0) and b(4); ab4(1) <= a(1) and b(4); ab4(2) <= a(2) and b(4);
|
40 |
|
|
ab4(3) <= a(3) and b(4); ab4(4) <= a(4) and b(4); ab4(5) <= a(5) and b(4);
|
41 |
|
|
ab4(6) <= a(6) and b(4);
|
42 |
|
|
|
43 |
|
|
s0(0) <= ab0(0);
|
44 |
|
|
s0(1) <= ab1(0) xor ab0(1);
|
45 |
|
|
c0(0) <= ab1(0) and ab0(1);
|
46 |
|
|
|
47 |
|
|
s1(0) <= ab2(0);
|
48 |
|
|
s1(1) <= ab3(0) xor ab2(1);
|
49 |
|
|
c1(0) <= ab3(0) and ab2(1);
|
50 |
|
|
|
51 |
|
|
fa11: full_adder port map (ab0(2), ab1(1), c0(0), c0(1), s0(2));
|
52 |
|
|
fa12: full_adder port map (ab0(3), ab1(2), c0(1), c0(2), s0(3));
|
53 |
|
|
fa13: full_adder port map (ab0(4), ab1(3), c0(2), c0(3), s0(4));
|
54 |
|
|
fa14: full_adder port map (ab0(5), ab1(4), c0(3), c0(4), s0(5));
|
55 |
|
|
fa15: full_adder port map (ab0(6), ab1(5), c0(4), c0(5), s0(6));
|
56 |
|
|
s0(7) <= c0(5) xor ab1(6);
|
57 |
|
|
c0(6) <= c0(5) and ab1(6);
|
58 |
|
|
|
59 |
|
|
fa21: full_adder port map (ab2(2), ab3(1), c1(0), c1(1), s1(2));
|
60 |
|
|
fa22: full_adder port map (ab2(3), ab3(2), c1(1), c1(2), s1(3));
|
61 |
|
|
fa23: full_adder port map (ab2(4), ab3(3), c1(2), c1(3), s1(4));
|
62 |
|
|
fa24: full_adder port map (ab2(5), ab3(4), c1(3), c1(4), s1(5));
|
63 |
|
|
fa25: full_adder port map (ab2(6), ab3(5), c1(4), c1(5), s1(6));
|
64 |
|
|
s1(7) <= c1(5) xor ab3(6);
|
65 |
|
|
c1(6) <= c1(5) and ab3(6);
|
66 |
|
|
|
67 |
|
|
r1 <= "000" & c0(6) & s0;
|
68 |
|
|
r2 <= "0" & c1(6) & s1 & "00";
|
69 |
|
|
r3 <= "0" & ab4 & "0000";
|
70 |
|
|
|
71 |
|
|
fa31: full_adder port map (r1(0), r2(0), '0', rc1(0), r4(0));
|
72 |
|
|
fa32: full_adder port map (r1(1), r2(1), rc1(0), rc1(1), r4(1));
|
73 |
|
|
fa33: full_adder port map (r1(2), r2(2), rc1(1), rc1(2), r4(2));
|
74 |
|
|
fa34: full_adder port map (r1(3), r2(3), rc1(2), rc1(3), r4(3));
|
75 |
|
|
fa35: full_adder port map (r1(4), r2(4), rc1(3), rc1(4), r4(4));
|
76 |
|
|
fa36: full_adder port map (r1(5), r2(5), rc1(4), rc1(5), r4(5));
|
77 |
|
|
fa37: full_adder port map (r1(6), r2(6), rc1(5), rc1(6), r4(6));
|
78 |
|
|
fa38: full_adder port map (r1(7), r2(7), rc1(6), rc1(7), r4(7));
|
79 |
|
|
fa39: full_adder port map (r1(8), r2(8), rc1(7), rc1(8), r4(8));
|
80 |
|
|
fa3a: full_adder port map (r1(9), r2(9), rc1(8), rc1(9), r4(9));
|
81 |
|
|
fa3b: full_adder port map (r1(10), r2(10), rc1(9), rc1(10), r4(10));
|
82 |
|
|
r4(11) <= (r1(11) xor r2(11)) xor rc1(10);
|
83 |
|
|
|
84 |
|
|
fa41: full_adder port map (r4(0), r3(0), '0', rc2(0), c(0));
|
85 |
|
|
fa42: full_adder port map (r4(1), r3(1), rc2(0), rc2(1), c(1));
|
86 |
|
|
fa43: full_adder port map (r4(2), r3(2), rc2(1), rc2(2), c(2));
|
87 |
|
|
fa44: full_adder port map (r4(3), r3(3), rc2(2), rc2(3), c(3));
|
88 |
|
|
fa45: full_adder port map (r4(4), r3(4), rc2(3), rc2(4), c(4));
|
89 |
|
|
fa46: full_adder port map (r4(5), r3(5), rc2(4), rc2(5), c(5));
|
90 |
|
|
fa47: full_adder port map (r4(6), r3(6), rc2(5), rc2(6), c(6));
|
91 |
|
|
fa48: full_adder port map (r4(7), r3(7), rc2(6), rc2(7), c(7));
|
92 |
|
|
fa49: full_adder port map (r4(8), r3(8), rc2(7), rc2(8), c(8));
|
93 |
|
|
fa4a: full_adder port map (r4(9), r3(9), rc2(8), rc2(9), c(9));
|
94 |
|
|
fa4b: full_adder port map (r4(10), r3(10), rc2(9), rc2(10), c(10));
|
95 |
|
|
c(11) <= (r4(11) xor r3(11)) xor rc2(10);
|
96 |
|
|
|
97 |
|
|
end Behavioral;
|
98 |
|
|
|