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[/] [altor32/] [trunk/] [rtl/] [soc/] [soc_pif8.v] - Blame information for rev 27

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1 27 ultra_embe 
 
2 
//-----------------------------------------------------------------
3 
// Module:
4 
//-----------------------------------------------------------------
5 
module soc_pif8
6 
(
7 
    // General - Clocking & Reset
8 
    clk_i,
9 
    rst_i,
10 
 
11 
    // Peripherals
12 
    periph0_addr_o,
13 
    periph0_data_o,
14 
    periph0_data_i,
15 
    periph0_wr_o,
16 
    periph0_rd_o,
17 
    periph1_addr_o,
18 
    periph1_data_o,
19 
    periph1_data_i,
20 
    periph1_wr_o,
21 
    periph1_rd_o,
22 
    periph2_addr_o,
23 
    periph2_data_o,
24 
    periph2_data_i,
25 
    periph2_wr_o,
26 
    periph2_rd_o,
27 
    periph3_addr_o,
28 
    periph3_data_o,
29 
    periph3_data_i,
30 
    periph3_wr_o,
31 
    periph3_rd_o,
32 
    periph4_addr_o,
33 
    periph4_data_o,
34 
    periph4_data_i,
35 
    periph4_wr_o,
36 
    periph4_rd_o,
37 
    periph5_addr_o,
38 
    periph5_data_o,
39 
    periph5_data_i,
40 
    periph5_wr_o,
41 
    periph5_rd_o,
42 
    periph6_addr_o,
43 
    periph6_data_o,
44 
    periph6_data_i,
45 
    periph6_wr_o,
46 
    periph6_rd_o,
47 
    periph7_addr_o,
48 
    periph7_data_o,
49 
    periph7_data_i,
50 
    periph7_wr_o,
51 
    periph7_rd_o,
52 
 
53 
    // I/O bus
54 
    io_addr_i,
55 
    io_data_i,
56 
    io_data_o,
57 
    io_wr_i,
58 
    io_rd_i
59 
);
60 
 
61 
//-----------------------------------------------------------------
62 
// I/O
63 
//-----------------------------------------------------------------
64 
input               clk_i /*verilator public*/;
65 
input               rst_i /*verilator public*/;
66 
 
67 
input [31:0]        io_addr_i /*verilator public*/;
68 
output [31:0]       io_data_o /*verilator public*/;
69 
input [31:0]        io_data_i /*verilator public*/;
70 
input [3:0]         io_wr_i /*verilator public*/;
71 
input               io_rd_i /*verilator public*/;
72 
 
73 
output [7:0]        periph0_addr_o /*verilator public*/;
74 
output [31:0]       periph0_data_o /*verilator public*/;
75 
input [31:0]        periph0_data_i /*verilator public*/;
76 
output [3:0]        periph0_wr_o /*verilator public*/;
77 
output              periph0_rd_o /*verilator public*/;
78 
output [7:0]        periph1_addr_o /*verilator public*/;
79 
output [31:0]       periph1_data_o /*verilator public*/;
80 
input [31:0]        periph1_data_i /*verilator public*/;
81 
output [3:0]        periph1_wr_o /*verilator public*/;
82 
output              periph1_rd_o /*verilator public*/;
83 
output [7:0]        periph2_addr_o /*verilator public*/;
84 
output [31:0]       periph2_data_o /*verilator public*/;
85 
input [31:0]        periph2_data_i /*verilator public*/;
86 
output [3:0]        periph2_wr_o /*verilator public*/;
87 
output              periph2_rd_o /*verilator public*/;
88 
output [7:0]        periph3_addr_o /*verilator public*/;
89 
output [31:0]       periph3_data_o /*verilator public*/;
90 
input [31:0]        periph3_data_i /*verilator public*/;
91 
output [3:0]        periph3_wr_o /*verilator public*/;
92 
output              periph3_rd_o /*verilator public*/;
93 
output [7:0]        periph4_addr_o /*verilator public*/;
94 
output [31:0]       periph4_data_o /*verilator public*/;
95 
input [31:0]        periph4_data_i /*verilator public*/;
96 
output [3:0]        periph4_wr_o /*verilator public*/;
97 
output              periph4_rd_o /*verilator public*/;
98 
output [7:0]        periph5_addr_o /*verilator public*/;
99 
output [31:0]       periph5_data_o /*verilator public*/;
100 
input [31:0]        periph5_data_i /*verilator public*/;
101 
output [3:0]        periph5_wr_o /*verilator public*/;
102 
output              periph5_rd_o /*verilator public*/;
103 
output [7:0]        periph6_addr_o /*verilator public*/;
104 
output [31:0]       periph6_data_o /*verilator public*/;
105 
input [31:0]        periph6_data_i /*verilator public*/;
106 
output [3:0]        periph6_wr_o /*verilator public*/;
107 
output              periph6_rd_o /*verilator public*/;
108 
output [7:0]        periph7_addr_o /*verilator public*/;
109 
output [31:0]       periph7_data_o /*verilator public*/;
110 
input [31:0]        periph7_data_i /*verilator public*/;
111 
output [3:0]        periph7_wr_o /*verilator public*/;
112 
output              periph7_rd_o /*verilator public*/;
113 
 
114 
//-----------------------------------------------------------------
115 
// Registers
116 
//-----------------------------------------------------------------
117 
reg [3:0]           r_mem_sel;
118 
 
119 
reg [31:0]          io_data_o;
120 
 
121 
reg [7:0]           periph0_addr_o;
122 
reg [31:0]          periph0_data_o;
123 
reg [3:0]           periph0_wr_o;
124 
reg                 periph0_rd_o;
125 
reg [7:0]           periph1_addr_o;
126 
reg [31:0]          periph1_data_o;
127 
reg [3:0]           periph1_wr_o;
128 
reg                 periph1_rd_o;
129 
reg [7:0]           periph2_addr_o;
130 
reg [31:0]          periph2_data_o;
131 
reg [3:0]           periph2_wr_o;
132 
reg                 periph2_rd_o;
133 
reg [7:0]           periph3_addr_o;
134 
reg [31:0]          periph3_data_o;
135 
reg [3:0]           periph3_wr_o;
136 
reg                 periph3_rd_o;
137 
reg [7:0]           periph4_addr_o;
138 
reg [31:0]          periph4_data_o;
139 
reg [3:0]           periph4_wr_o;
140 
reg                 periph4_rd_o;
141 
reg [7:0]           periph5_addr_o;
142 
reg [31:0]          periph5_data_o;
143 
reg [3:0]           periph5_wr_o;
144 
reg                 periph5_rd_o;
145 
reg [7:0]           periph6_addr_o;
146 
reg [31:0]          periph6_data_o;
147 
reg [3:0]           periph6_wr_o;
148 
reg                 periph6_rd_o;
149 
reg [7:0]           periph7_addr_o;
150 
reg [31:0]          periph7_data_o;
151 
reg [3:0]           periph7_wr_o;
152 
reg                 periph7_rd_o;
153 
 
154 
//-----------------------------------------------------------------
155 
// Memory Map
156 
//-----------------------------------------------------------------
157 
always @ (io_addr_i or io_wr_i or io_rd_i or io_data_i)
158 
begin
159 
 
160 
   periph0_addr_o       = 8'h00;
161 
   periph0_wr_o         = 4'b0000;
162 
   periph0_rd_o         = 1'b0;
163 
   periph0_data_o       = 32'h00000000;
164 
   periph1_addr_o       = 8'h00;
165 
   periph1_wr_o         = 4'b0000;
166 
   periph1_rd_o         = 1'b0;
167 
   periph1_data_o       = 32'h00000000;
168 
   periph2_addr_o       = 8'h00;
169 
   periph2_wr_o         = 4'b0000;
170 
   periph2_rd_o         = 1'b0;
171 
   periph2_data_o       = 32'h00000000;
172 
   periph3_addr_o       = 8'h00;
173 
   periph3_wr_o         = 4'b0000;
174 
   periph3_rd_o         = 1'b0;
175 
   periph3_data_o       = 32'h00000000;
176 
   periph4_addr_o       = 8'h00;
177 
   periph4_wr_o         = 4'b0000;
178 
   periph4_rd_o         = 1'b0;
179 
   periph4_data_o       = 32'h00000000;
180 
   periph5_addr_o       = 8'h00;
181 
   periph5_wr_o         = 4'b0000;
182 
   periph5_rd_o         = 1'b0;
183 
   periph5_data_o       = 32'h00000000;
184 
   periph6_addr_o       = 8'h00;
185 
   periph6_wr_o         = 4'b0000;
186 
   periph6_rd_o         = 1'b0;
187 
   periph6_data_o       = 32'h00000000;
188 
   periph7_addr_o       = 8'h00;
189 
   periph7_wr_o         = 4'b0000;
190 
   periph7_rd_o         = 1'b0;
191 
   periph7_data_o       = 32'h00000000;
192 
 
193 
   // Decode 4-bit peripheral select
194 
   case (io_addr_i[11:8])
195 
 
196 
   // Peripheral 0
197 
   4'd 0 :
198 
   begin
199 
       periph0_addr_o       = io_addr_i[7:0];
200 
       periph0_wr_o         = io_wr_i;
201 
       periph0_rd_o         = io_rd_i;
202 
       periph0_data_o       = io_data_i;
203 
   end
204 
   // Peripheral 1
205 
   4'd 1 :
206 
   begin
207 
       periph1_addr_o       = io_addr_i[7:0];
208 
       periph1_wr_o         = io_wr_i;
209 
       periph1_rd_o         = io_rd_i;
210 
       periph1_data_o       = io_data_i;
211 
   end
212 
   // Peripheral 2
213 
   4'd 2 :
214 
   begin
215 
       periph2_addr_o       = io_addr_i[7:0];
216 
       periph2_wr_o         = io_wr_i;
217 
       periph2_rd_o         = io_rd_i;
218 
       periph2_data_o       = io_data_i;
219 
   end
220 
   // Peripheral 3
221 
   4'd 3 :
222 
   begin
223 
       periph3_addr_o       = io_addr_i[7:0];
224 
       periph3_wr_o         = io_wr_i;
225 
       periph3_rd_o         = io_rd_i;
226 
       periph3_data_o       = io_data_i;
227 
   end
228 
   // Peripheral 4
229 
   4'd 4 :
230 
   begin
231 
       periph4_addr_o       = io_addr_i[7:0];
232 
       periph4_wr_o         = io_wr_i;
233 
       periph4_rd_o         = io_rd_i;
234 
       periph4_data_o       = io_data_i;
235 
   end
236 
   // Peripheral 5
237 
   4'd 5 :
238 
   begin
239 
       periph5_addr_o       = io_addr_i[7:0];
240 
       periph5_wr_o         = io_wr_i;
241 
       periph5_rd_o         = io_rd_i;
242 
       periph5_data_o       = io_data_i;
243 
   end
244 
   // Peripheral 6
245 
   4'd 6 :
246 
   begin
247 
       periph6_addr_o       = io_addr_i[7:0];
248 
       periph6_wr_o         = io_wr_i;
249 
       periph6_rd_o         = io_rd_i;
250 
       periph6_data_o       = io_data_i;
251 
   end
252 
   // Peripheral 7
253 
   4'd 7 :
254 
   begin
255 
       periph7_addr_o       = io_addr_i[7:0];
256 
       periph7_wr_o         = io_wr_i;
257 
       periph7_rd_o         = io_rd_i;
258 
       periph7_data_o       = io_data_i;
259 
   end
260 
 
261 
   default :
262 
      ;
263 
   endcase
264 
end
265 
 
266 
//-----------------------------------------------------------------
267 
// Read Port
268 
//-----------------------------------------------------------------
269 
always @ *
270 
begin
271 
   case (r_mem_sel)
272 
 
273 
   // Peripheral 0
274 
   4'd 0 :
275 
   begin
276 
       io_data_o   = periph0_data_i;
277 
   end
278 
   // Peripheral 1
279 
   4'd 1 :
280 
   begin
281 
       io_data_o   = periph1_data_i;
282 
   end
283 
   // Peripheral 2
284 
   4'd 2 :
285 
   begin
286 
       io_data_o   = periph2_data_i;
287 
   end
288 
   // Peripheral 3
289 
   4'd 3 :
290 
   begin
291 
       io_data_o   = periph3_data_i;
292 
   end
293 
   // Peripheral 4
294 
   4'd 4 :
295 
   begin
296 
       io_data_o   = periph4_data_i;
297 
   end
298 
   // Peripheral 5
299 
   4'd 5 :
300 
   begin
301 
       io_data_o   = periph5_data_i;
302 
   end
303 
   // Peripheral 6
304 
   4'd 6 :
305 
   begin
306 
       io_data_o   = periph6_data_i;
307 
   end
308 
   // Peripheral 7
309 
   4'd 7 :
310 
   begin
311 
       io_data_o   = periph7_data_i;
312 
   end
313 
 
314 
   default :
315 
   begin
316 
       io_data_o   = 32'h00000000;
317 
   end
318 
   endcase
319 
end
320 
 
321 
//-----------------------------------------------------------------
322 
// Registered peripheral select
323 
//-----------------------------------------------------------------
324 
always @ (posedge clk_i or posedge rst_i)
325 
begin
326 
   if (rst_i == 1'b1)
327 
       r_mem_sel <= 4'h0;
328 
   else
329 
       r_mem_sel <= io_addr_i[11:8];
330 
end
331 
 
332 
endmodule

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