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[/] [amber/] [trunk/] [hw/] [tests/] [stm1.S] - Blame information for rev 2

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/*****************************************************************
//                                                              //
//  Amber 2 Core Instruction Test                               //
//                                                              //
//  This file is part of the Amber project                      //
//  http://www.opencores.org/project,amber                      //
//                                                              //
//  Description                                                 //
//  Tests stm                                                   //
//                                                              //
//  Author(s):                                                  //
//      - Conor Santifort, csantifort.amber@gmail.com           //
//                                                              //
//////////////////////////////////////////////////////////////////
//                                                              //
// Copyright (C) 2010 Authors and OPENCORES.ORG                 //
//                                                              //
// This source file may be used and distributed without         //
// restriction provided that this copyright statement is not    //
// removed from the file and that any derivative work contains  //
// the original copyright notice and the associated disclaimer. //
//                                                              //
// This source file is free software; you can redistribute it   //
// and/or modify it under the terms of the GNU Lesser General   //
// Public License as published by the Free Software Foundation; //
// either version 2.1 of the License, or (at your option) any   //
// later version.                                               //
//                                                              //
// This source is distributed in the hope that it will be       //
// useful, but WITHOUT ANY WARRANTY; without even the implied   //
// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      //
// PURPOSE.  See the GNU Lesser General Public License for more //
// details.                                                     //
//                                                              //
// You should have received a copy of the GNU Lesser General    //
// Public License along with this source; if not, download it   //
// from http://www.opencores.org/lgpl.shtml                     //
//                                                              //
*****************************************************************/
 
#include "amber_registers.h"
 
        .section .text
        .globl  main
main:
 
@ ------------------------------------------
@ 1. stmia   r14!, {r0-r13}
@ ------------------------------------------
 
        mov     r0,  #0
        mov     r1,  #1
        mov     r2,  #2
        mov     r3,  #3
        mov     r4,  #4
        mov     r5,  #5
        mov     r6,  #6
        mov     r7,  #7
        mov     r8,  #8
        mov     r9,  #9
        mov     r10, #10
        mov     r11, #11
        mov     r12, #12
        mov     r13, #13
        ldr     r14, StoreBase
        stmia   r14!, {r0-r13}
 
 
        @ Check that r14 was updated correctly
        ldr     r0, StoreBase
        add     r0, r0, #56  @ 14 x 4
        cmp     r14, r0
        movne   r10, #20
        bne     testfail
 
        @ Check that all values were saved to memory correctly
        mov     r2, #0
        ldr     r0, StoreBase
loop1:  ldr     r1, [r0], #4
        cmp     r1, r2
        movne   r10, #30
        bne     testfail
        cmp     r2, #13
        beq     start2
        add     r2, r2, #1
        b       loop1
 
 
@ ------------------------------------------
@ 2. stmib   r14!, {r0-r13}
@ ------------------------------------------
start2:
        mov     r0,  #0
        mov     r1,  #1
        mov     r2,  #2
        mov     r3,  #3
        mov     r4,  #4
        mov     r5,  #5
        mov     r6,  #6
        mov     r7,  #7
        mov     r8,  #8
        mov     r9,  #9
        mov     r10, #10
        mov     r11, #11
        mov     r12, #12
        mov     r13, #13
        ldr     r14, StoreBase
        stmib   r14!, {r0-r13}
 
        @ Check that r14 was updated correctly
        ldr     r0, StoreBase
        add     r0, r0, #56  @ 14 x 4
        cmp     r14, r0
        movne   r10, #40
        bne     testfail
 
        @ Check that all values were saved to memory correctly
        mov     r2, #0
        ldr     r0, StoreBase
        add     r0, r0, #4
loop2:  ldr     r1, [r0], #4
        cmp     r1, r2
        movne   r10, #50
        bne     testfail
        cmp     r2, #13
        beq     start3
        add     r2, r2, #1
        b       loop2
 
 
@ ------------------------------------------
@ 3. stmib   r14!, {r14}
@ Test that the starting value of r14 is stored
@ Test that storing a single register works correctly
@ ------------------------------------------
start3:
        ldr     r14, StoreBase
        stmib   r14!, {r14}
 
        @ check that r14 got updated with a new value
        ldr     r0, StoreBase
        add     r1, r0, #4
        cmp     r14, r1
        movne   r10, #60
        bne     testfail
 
        @ check that the old value in r14 was stored
        ldr     r2, [r1]
        cmp     r2, r0
        movne   r10, #70
        bne     testfail
 
 
 
@ ------------------------------------------
@ 4. stmda   r0, {r14, pc}
@ Test that r0 is not updated
@ Test that the correct pc value is stored
@ Test that Descending works
@ ------------------------------------------
start4:
        mov     r14, #97
        ldr     r0, StoreBase
        mov     r2, pc  @ NB this must be immediately before
                        @ the stm instruction to capture the
                        @ correct pc value for checking below
        stmda   r0, {lr, pc}
 
        @ check that r0 did not get updated
        ldr     r1, StoreBase
        cmp     r0, r1
        movne   r10, #70
        bne     testfail
 
        @ check that the correct pc value was stored
        @ The value of the pc is 12 bytes after the address of the stm instruction
        add     r2, r2, #8
        ldr     r3, [r1]
        cmp     r2, r3
        movne   r10, #80
        bne     testfail
 
        @ check that r14 was stored in the correct place
        ldr     r1, StoreBase
        sub     r1, r1, #4
        ldr     r4, [r1]
        cmp     r4, #97
        movne   r10, #90
        bne     testfail
 
 
@ ------------------------------------------
@ 5. stmdb   r9!, {r0, r9, r10}
@ Test non-continuous range of registers
@ Test that r9 is updated correctly
@ ------------------------------------------
        mov     r0,  #17
        ldr     r9,  StoreBase
        mov     r10, #18
        stmdb   r9!, {r0, r9, r10}
 
        ldr     r3,  StoreBase
        sub     r3,  r3, #12
        ldr     r4,  [r3], #4
        cmp     r4,  #17
        movne   r10, #100
        bne     testfail
 
        @ r9 is the second register on the list, so the updated
        @ value gets stored in StoreBase - 8
        ldr     r4,  [r3]       @ r3 points to StoreBase - 8
        ldr     r3,  StoreBase
        sub     r3,  r3, #12
        cmp     r3,  r4
        movne   r10, #110
        bne     testfail
 
        ldr     r3,  StoreBase
        sub     r3,  r3, #4
        ldr     r4,  [r3]
        cmp     r4,  #18
        movne   r10, #120
        bne     testfail
 
@ ------------------------------------------
@ ------------------------------------------
 
        b       testpass
 
testfail:
        ldr     r11, AdrTestStatus
        str     r10, [r11]
        b       testfail
 
testpass:
        ldr     r11, AdrTestStatus
        mov     r10, #17
        str     r10, [r11]
        b       testpass
 
 
 
/* Write 17 to this address to generate a Test Passed message */
AdrTestStatus:  .word  ADR_AMBER_TEST_STATUS
AdrData1:       .word  Data1
AdrData2:       .word  Data2
StoreBase:      .word  0x800
Data1:          .word  0x12345678
Data2:          .word  0xffccbbaa
Data3:          .word  0x12345600
 
/* ========================================================================= */
/* ========================================================================= */
 
 

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[/] [amber/] [trunk/] [hw/] [tests/] [stm1.S] - Blame information for rev 2

Line No.	Rev	Author	Line
1	2	csantifort	`/*****************************************************************`
2			`// //`
3			`// Amber 2 Core Instruction Test //`
4			`// //`
5			`// This file is part of the Amber project //`
6			`// http://www.opencores.org/project,amber //`
7			`// //`
8			`// Description //`
9			`// Tests stm //`
10			`// //`
11			`// Author(s): //`
12			`// - Conor Santifort, csantifort.amber@gmail.com //`
13			`// //`
14			`//////////////////////////////////////////////////////////////////`
15			`// //`
16			`// Copyright (C) 2010 Authors and OPENCORES.ORG //`
17			`// //`
18			`// This source file may be used and distributed without //`
19			`// restriction provided that this copyright statement is not //`
20			`// removed from the file and that any derivative work contains //`
21			`// the original copyright notice and the associated disclaimer. //`
22			`// //`
23			`// This source file is free software; you can redistribute it //`
24			`// and/or modify it under the terms of the GNU Lesser General //`
25			`// Public License as published by the Free Software Foundation; //`
26			`// either version 2.1 of the License, or (at your option) any //`
27			`// later version. //`
28			`// //`
29			`// This source is distributed in the hope that it will be //`
30			`// useful, but WITHOUT ANY WARRANTY; without even the implied //`
31			`// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //`
32			`// PURPOSE. See the GNU Lesser General Public License for more //`
33			`// details. //`
34			`// //`
35			`// You should have received a copy of the GNU Lesser General //`
36			`// Public License along with this source; if not, download it //`
37			`// from http://www.opencores.org/lgpl.shtml //`
38			`// //`
39			`*****************************************************************/`
40
41			`#include "amber_registers.h"`
42
43			`.section .text`
44			`.globl main`
45			`main:`
46
47			`@ ------------------------------------------`
48			`@ 1. stmia r14!, {r0-r13}`
49			`@ ------------------------------------------`
50
51			`mov r0, #0`
52			`mov r1, #1`
53			`mov r2, #2`
54			`mov r3, #3`
55			`mov r4, #4`
56			`mov r5, #5`
57			`mov r6, #6`
58			`mov r7, #7`
59			`mov r8, #8`
60			`mov r9, #9`
61			`mov r10, #10`
62			`mov r11, #11`
63			`mov r12, #12`
64			`mov r13, #13`
65			`ldr r14, StoreBase`
66			`stmia r14!, {r0-r13}`
67
68
69			`@ Check that r14 was updated correctly`
70			`ldr r0, StoreBase`
71			`add r0, r0, #56 @ 14 x 4`
72			`cmp r14, r0`
73			`movne r10, #20`
74			`bne testfail`
75
76			`@ Check that all values were saved to memory correctly`
77			`mov r2, #0`
78			`ldr r0, StoreBase`
79			`loop1: ldr r1, [r0], #4`
80			`cmp r1, r2`
81			`movne r10, #30`
82			`bne testfail`
83			`cmp r2, #13`
84			`beq start2`
85			`add r2, r2, #1`
86			`b loop1`
87
88
89			`@ ------------------------------------------`
90			`@ 2. stmib r14!, {r0-r13}`
91			`@ ------------------------------------------`
92			`start2:`
93			`mov r0, #0`
94			`mov r1, #1`
95			`mov r2, #2`
96			`mov r3, #3`
97			`mov r4, #4`
98			`mov r5, #5`
99			`mov r6, #6`
100			`mov r7, #7`
101			`mov r8, #8`
102			`mov r9, #9`
103			`mov r10, #10`
104			`mov r11, #11`
105			`mov r12, #12`
106			`mov r13, #13`
107			`ldr r14, StoreBase`
108			`stmib r14!, {r0-r13}`
109
110			`@ Check that r14 was updated correctly`
111			`ldr r0, StoreBase`
112			`add r0, r0, #56 @ 14 x 4`
113			`cmp r14, r0`
114			`movne r10, #40`
115			`bne testfail`
116
117			`@ Check that all values were saved to memory correctly`
118			`mov r2, #0`
119			`ldr r0, StoreBase`
120			`add r0, r0, #4`
121			`loop2: ldr r1, [r0], #4`
122			`cmp r1, r2`
123			`movne r10, #50`
124			`bne testfail`
125			`cmp r2, #13`
126			`beq start3`
127			`add r2, r2, #1`
128			`b loop2`
129
130
131			`@ ------------------------------------------`
132			`@ 3. stmib r14!, {r14}`
133			`@ Test that the starting value of r14 is stored`
134			`@ Test that storing a single register works correctly`
135			`@ ------------------------------------------`
136			`start3:`
137			`ldr r14, StoreBase`
138			`stmib r14!, {r14}`
139
140			`@ check that r14 got updated with a new value`
141			`ldr r0, StoreBase`
142			`add r1, r0, #4`
143			`cmp r14, r1`
144			`movne r10, #60`
145			`bne testfail`
146
147			`@ check that the old value in r14 was stored`
148			`ldr r2, [r1]`
149			`cmp r2, r0`
150			`movne r10, #70`
151			`bne testfail`
152
153
154
155			`@ ------------------------------------------`
156			`@ 4. stmda r0, {r14, pc}`
157			`@ Test that r0 is not updated`
158			`@ Test that the correct pc value is stored`
159			`@ Test that Descending works`
160			`@ ------------------------------------------`
161			`start4:`
162			`mov r14, #97`
163			`ldr r0, StoreBase`
164			`mov r2, pc @ NB this must be immediately before`
165			`@ the stm instruction to capture the`
166			`@ correct pc value for checking below`
167			`stmda r0, {lr, pc}`
168
169			`@ check that r0 did not get updated`
170			`ldr r1, StoreBase`
171			`cmp r0, r1`
172			`movne r10, #70`
173			`bne testfail`
174
175			`@ check that the correct pc value was stored`
176			`@ The value of the pc is 12 bytes after the address of the stm instruction`
177			`add r2, r2, #8`
178			`ldr r3, [r1]`
179			`cmp r2, r3`
180			`movne r10, #80`
181			`bne testfail`
182
183			`@ check that r14 was stored in the correct place`
184			`ldr r1, StoreBase`
185			`sub r1, r1, #4`
186			`ldr r4, [r1]`
187			`cmp r4, #97`
188			`movne r10, #90`
189			`bne testfail`
190
191
192			`@ ------------------------------------------`
193			`@ 5. stmdb r9!, {r0, r9, r10}`
194			`@ Test non-continuous range of registers`
195			`@ Test that r9 is updated correctly`
196			`@ ------------------------------------------`
197			`mov r0, #17`
198			`ldr r9, StoreBase`
199			`mov r10, #18`
200			`stmdb r9!, {r0, r9, r10}`
201
202			`ldr r3, StoreBase`
203			`sub r3, r3, #12`
204			`ldr r4, [r3], #4`
205			`cmp r4, #17`
206			`movne r10, #100`
207			`bne testfail`
208
209			`@ r9 is the second register on the list, so the updated`
210			`@ value gets stored in StoreBase - 8`
211			`ldr r4, [r3] @ r3 points to StoreBase - 8`
212			`ldr r3, StoreBase`
213			`sub r3, r3, #12`
214			`cmp r3, r4`
215			`movne r10, #110`
216			`bne testfail`
217
218			`ldr r3, StoreBase`
219			`sub r3, r3, #4`
220			`ldr r4, [r3]`
221			`cmp r4, #18`
222			`movne r10, #120`
223			`bne testfail`
224
225			`@ ------------------------------------------`
226			`@ ------------------------------------------`
227
228			`b testpass`
229
230			`testfail:`
231			`ldr r11, AdrTestStatus`
232			`str r10, [r11]`
233			`b testfail`
234
235			`testpass:`
236			`ldr r11, AdrTestStatus`
237			`mov r10, #17`
238			`str r10, [r11]`
239			`b testpass`
240
241
242
243			`/* Write 17 to this address to generate a Test Passed message */`
244			`AdrTestStatus: .word ADR_AMBER_TEST_STATUS`
245			`AdrData1: .word Data1`
246			`AdrData2: .word Data2`
247			`StoreBase: .word 0x800`
248			`Data1: .word 0x12345678`
249			`Data2: .word 0xffccbbaa`
250			`Data3: .word 0x12345600`
251
252			`/* ========================================================================= */`
253			`/* ========================================================================= */`
254
255