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[/] [amber/] [trunk/] [hw/] [vlog/] [amber25/] [a25_coprocessor.v] - Blame information for rev 16

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1 16 csantifort 
//////////////////////////////////////////////////////////////////
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//                                                              //
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//  Co-processor module for Amber 25 Core                       //
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//                                                              //
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//  This file is part of the Amber project                      //
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//  http://www.opencores.org/project,amber                      //
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//                                                              //
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//  Description                                                 //
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//  Co_processor 15 registers and control signals               //
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//  Author(s):                                                  //
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//      - Conor Santifort, csantifort.amber@gmail.com           //
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//                                                              //
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//////////////////////////////////////////////////////////////////
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//                                                              //
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// Copyright (C) 2011 Authors and OPENCORES.ORG                 //
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//                                                              //
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// This source file may be used and distributed without         //
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// restriction provided that this copyright statement is not    //
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// removed from the file and that any derivative work contains  //
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// the original copyright notice and the associated disclaimer. //
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//                                                              //
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// This source file is free software; you can redistribute it   //
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// and/or modify it under the terms of the GNU Lesser General   //
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// Public License as published by the Free Software Foundation; //
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// either version 2.1 of the License, or (at your option) any   //
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// later version.                                               //
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//                                                              //
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// This source is distributed in the hope that it will be       //
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// useful, but WITHOUT ANY WARRANTY; without even the implied   //
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// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      //
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// PURPOSE.  See the GNU Lesser General Public License for more //
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// details.                                                     //
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//                                                              //
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// You should have received a copy of the GNU Lesser General    //
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// Public License along with this source; if not, download it   //
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// from http://www.opencores.org/lgpl.shtml                     //
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//                                                              //
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//////////////////////////////////////////////////////////////////
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module a25_coprocessor
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(
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input                       i_clk,
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input                       i_access_stall,   // stall all stages of the cpu at the same time
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input       [2:0]           i_copro_opcode1,
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input       [2:0]           i_copro_opcode2,
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input       [3:0]           i_copro_crn,      // Register Number
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input       [3:0]           i_copro_crm,
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input       [3:0]           i_copro_num,
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input       [1:0]           i_copro_operation,
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input       [31:0]          i_copro_write_data,
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input                       i_fault,          // high to latch the fault address and status
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input       [7:0]           i_fault_status,
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input       [31:0]          i_fault_address,  // the address that caused the fault
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output reg  [31:0]          o_copro_read_data,
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output                      o_cache_enable,
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output                      o_cache_flush,
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output      [31:0]          o_cacheable_area
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);
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// Bit 0 - Cache on(1)/off
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// Bit 1 - Shared (1) or seperate User/Supervisor address space
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// Bit 2 - address monitor mode(1)
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reg [2:0]  cache_control = 3'b000;
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// Bit 0 - 2MB memory from 0 to 0x01fffff cacheable(1)/not cachable
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// Bit 1 - next 2MB region etc.
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reg [31:0] cacheable_area = 32'h0;
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// Marks memory regions as read only so writes are ignored by the cache
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// Bit 0 - 2MB memory from 0 to 0x01fffff updateable(1)/not updateable
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// Bit 1 - next 2MB region etc.
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reg [31:0] updateable_area = 32'h0;
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// Accesses to a region with a flag set in this register cause the
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// cache to flush
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// Bit 0 - 2MB memory from 0 to 0x01fffff
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// Bit 1 - next 2MB region etc.
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reg [31:0] disruptive_area = 32'h0;
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reg [7:0]  fault_status  = 'd0;
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reg [31:0] fault_address = 'd0;  // the address that caused the fault
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wire       copro15_reg1_write;
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// ---------------------------
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// Outputs
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// ---------------------------
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assign o_cache_enable   = cache_control[0];
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assign o_cache_flush    = copro15_reg1_write;
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assign o_cacheable_area = cacheable_area;
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// ---------------------------
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// Capture an access fault address and status
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// ---------------------------
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always @ ( posedge i_clk )
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    if ( !i_access_stall )
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        begin
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        if ( i_fault )
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            begin
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            `ifdef A25_COPRO15_DEBUG
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            $display ("Fault status  set to 0x%08x", i_fault_status);
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            $display ("Fault address set to 0x%08x", i_fault_address);
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            `endif
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            fault_status    <= i_fault_status;
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            fault_address   <= i_fault_address;
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            end
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        end
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// ---------------------------
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// Register Writes
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// ---------------------------
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always @ ( posedge i_clk )
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    if ( !i_access_stall )
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        begin
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        if ( i_copro_operation == 2'd2 )
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            case ( i_copro_crn )
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                4'd2: cache_control   <= i_copro_write_data[2:0];
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                4'd3: cacheable_area  <= i_copro_write_data[31:0];
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                4'd4: updateable_area <= i_copro_write_data[31:0];
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                4'd5: disruptive_area <= i_copro_write_data[31:0];
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            endcase
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        end
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// Flush the cache
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assign copro15_reg1_write = !i_access_stall && i_copro_operation == 2'd2 && i_copro_crn == 4'd1;
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// ---------------------------
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// Register Reads
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// ---------------------------
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always @ ( posedge i_clk )
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    if ( !i_access_stall )
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        case ( i_copro_crn )
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            // ID Register - [31:24] Company id, [23:16] Manuf id, [15:8] Part type, [7:0] revision
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            4'd0:    o_copro_read_data <= 32'h4156_0300;
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            4'd2:    o_copro_read_data <= {29'd0, cache_control};
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            4'd3:    o_copro_read_data <= cacheable_area;
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            4'd4:    o_copro_read_data <= updateable_area;
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            4'd5:    o_copro_read_data <= disruptive_area;
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            4'd6:    o_copro_read_data <= {24'd0, fault_status };
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            4'd7:    o_copro_read_data <= fault_address;
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            default: o_copro_read_data <= 32'd0;
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        endcase
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// ========================================================
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// Debug code - not synthesizable
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// ========================================================
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`ifdef A25_COPRO15_DEBUG
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//synopsys translate_off
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reg [1:0]  copro_operation_d1;
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reg [3:0]  copro_crn_d1;
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always @( posedge i_clk )
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    if ( !i_access_stall )
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        begin
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        copro_operation_d1  <= i_copro_operation;
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        copro_crn_d1        <= i_copro_crn;
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        end
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always @( posedge i_clk )
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    if ( !i_access_stall )
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        begin
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        if ( i_copro_operation == 2'd2 )  // mcr
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            case ( i_copro_crn )
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                4'd 1: begin `TB_DEBUG_MESSAGE $display ("Write 0x%08h to   Co-Pro 15 #1, Flush Cache", i_copro_write_data); end
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                4'd 2: begin `TB_DEBUG_MESSAGE $display ("Write 0x%08h to   Co-Pro 15 #2, Cache Control", i_copro_write_data); end
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                4'd 3: begin `TB_DEBUG_MESSAGE $display ("Write 0x%08h to   Co-Pro 15 #3, Cacheable area", i_copro_write_data); end
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                4'd 4: begin `TB_DEBUG_MESSAGE $display ("Write 0x%08h to   Co-Pro 15 #4, Updateable area", i_copro_write_data); end
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                4'd 5: begin `TB_DEBUG_MESSAGE $display ("Write 0x%08h to   Co-Pro 15 #5, Disruptive area", i_copro_write_data); end
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            endcase
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        if ( copro_operation_d1 == 2'd1 ) // mrc
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            case ( copro_crn_d1 )
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                4'd 0: begin `TB_DEBUG_MESSAGE $display ("Read  0x%08h from Co-Pro 15 #0, ID Register", o_copro_read_data); end
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                4'd 2: begin `TB_DEBUG_MESSAGE $display ("Read  0x%08h from Co-Pro 15 #2, Cache control", o_copro_read_data); end
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                4'd 3: begin `TB_DEBUG_MESSAGE $display ("Read  0x%08h from Co-Pro 15 #3, Cacheable area", o_copro_read_data); end
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                4'd 4: begin `TB_DEBUG_MESSAGE $display ("Read  0x%08h from Co-Pro 15 #4, Updateable area", o_copro_read_data); end
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                4'd 5: begin `TB_DEBUG_MESSAGE $display ("Read  0x%08h from Co-Pro 15 #4, Disruptive area", o_copro_read_data); end
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                4'd 6: begin `TB_DEBUG_MESSAGE $display ("Read  0x%08h from Co-Pro 15 #6, Fault Status Register", o_copro_read_data); end
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                4'd 7: begin `TB_DEBUG_MESSAGE $display ("Read  0x%08h from Co-Pro 15 #7, Fault Address Register", o_copro_read_data); end
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            endcase
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    end
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//synopsys translate_on
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`endif
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endmodule
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