| 1 |
16 |
csantifort |
//////////////////////////////////////////////////////////////////
|
| 2 |
|
|
// //
|
| 3 |
|
|
// Amber 25 Core top-Level module //
|
| 4 |
|
|
// //
|
| 5 |
|
|
// This file is part of the Amber project //
|
| 6 |
|
|
// http://www.opencores.org/project,amber //
|
| 7 |
|
|
// //
|
| 8 |
|
|
// Description //
|
| 9 |
|
|
// Instantiates the core consisting of fetch, instruction //
|
| 10 |
17 |
csantifort |
// decode, execute, memory access and write back. The //
|
| 11 |
|
|
// Wishbone interface and Co-Processor modules are also //
|
| 12 |
|
|
// instantiated here. //
|
| 13 |
16 |
csantifort |
// //
|
| 14 |
|
|
// Author(s): //
|
| 15 |
|
|
// - Conor Santifort, csantifort.amber@gmail.com //
|
| 16 |
|
|
// //
|
| 17 |
|
|
//////////////////////////////////////////////////////////////////
|
| 18 |
|
|
// //
|
| 19 |
|
|
// Copyright (C) 2011 Authors and OPENCORES.ORG //
|
| 20 |
|
|
// //
|
| 21 |
|
|
// This source file may be used and distributed without //
|
| 22 |
|
|
// restriction provided that this copyright statement is not //
|
| 23 |
|
|
// removed from the file and that any derivative work contains //
|
| 24 |
|
|
// the original copyright notice and the associated disclaimer. //
|
| 25 |
|
|
// //
|
| 26 |
|
|
// This source file is free software; you can redistribute it //
|
| 27 |
|
|
// and/or modify it under the terms of the GNU Lesser General //
|
| 28 |
|
|
// Public License as published by the Free Software Foundation; //
|
| 29 |
|
|
// either version 2.1 of the License, or (at your option) any //
|
| 30 |
|
|
// later version. //
|
| 31 |
|
|
// //
|
| 32 |
|
|
// This source is distributed in the hope that it will be //
|
| 33 |
|
|
// useful, but WITHOUT ANY WARRANTY; without even the implied //
|
| 34 |
|
|
// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //
|
| 35 |
|
|
// PURPOSE. See the GNU Lesser General Public License for more //
|
| 36 |
|
|
// details. //
|
| 37 |
|
|
// //
|
| 38 |
|
|
// You should have received a copy of the GNU Lesser General //
|
| 39 |
|
|
// Public License along with this source; if not, download it //
|
| 40 |
|
|
// from http://www.opencores.org/lgpl.shtml //
|
| 41 |
|
|
// //
|
| 42 |
|
|
//////////////////////////////////////////////////////////////////
|
| 43 |
|
|
|
| 44 |
|
|
|
| 45 |
|
|
module a25_core
|
| 46 |
|
|
(
|
| 47 |
|
|
input i_clk,
|
| 48 |
|
|
|
| 49 |
|
|
input i_irq, // Interrupt request, active high
|
| 50 |
|
|
input i_firq, // Fast Interrupt request, active high
|
| 51 |
|
|
|
| 52 |
|
|
input i_system_rdy, // Amber is stalled when this is low
|
| 53 |
|
|
|
| 54 |
|
|
// Wishbone Master I/F
|
| 55 |
|
|
output [31:0] o_wb_adr,
|
| 56 |
|
|
output [3:0] o_wb_sel,
|
| 57 |
|
|
output o_wb_we,
|
| 58 |
|
|
input [31:0] i_wb_dat,
|
| 59 |
|
|
output [31:0] o_wb_dat,
|
| 60 |
|
|
output o_wb_cyc,
|
| 61 |
|
|
output o_wb_stb,
|
| 62 |
|
|
input i_wb_ack,
|
| 63 |
|
|
input i_wb_err
|
| 64 |
|
|
|
| 65 |
|
|
);
|
| 66 |
|
|
|
| 67 |
|
|
wire [31:0] execute_iaddress;
|
| 68 |
|
|
wire execute_iaddress_valid;
|
| 69 |
|
|
wire [31:0] execute_iaddress_nxt; // un-registered version of execute_address
|
| 70 |
|
|
// to the instruction cache rams
|
| 71 |
|
|
wire [31:0] execute_daddress;
|
| 72 |
|
|
wire execute_daddress_valid;
|
| 73 |
|
|
wire [31:0] execute_daddress_nxt; // un-registered version of execute_daddress
|
| 74 |
|
|
// to the data cache rams
|
| 75 |
|
|
wire [31:0] write_data;
|
| 76 |
|
|
wire write_enable;
|
| 77 |
|
|
wire [31:0] fetch_instruction;
|
| 78 |
|
|
wire decode_exclusive;
|
| 79 |
|
|
wire decode_iaccess;
|
| 80 |
|
|
wire decode_daccess;
|
| 81 |
|
|
wire [3:0] byte_enable;
|
| 82 |
|
|
wire exclusive; // swap access
|
| 83 |
|
|
wire cache_enable; // Enabel the cache
|
| 84 |
|
|
wire cache_flush; // Flush the cache
|
| 85 |
|
|
wire [31:0] cacheable_area;
|
| 86 |
|
|
|
| 87 |
|
|
wire fetch_stall;
|
| 88 |
|
|
wire mem_stall;
|
| 89 |
|
|
wire access_stall;
|
| 90 |
|
|
|
| 91 |
|
|
wire [1:0] status_bits_mode;
|
| 92 |
|
|
wire status_bits_irq_mask;
|
| 93 |
|
|
wire status_bits_firq_mask;
|
| 94 |
|
|
wire status_bits_flags_wen;
|
| 95 |
|
|
wire status_bits_mode_wen;
|
| 96 |
|
|
wire status_bits_irq_mask_wen;
|
| 97 |
|
|
wire status_bits_firq_mask_wen;
|
| 98 |
|
|
wire [31:0] execute_status_bits;
|
| 99 |
|
|
|
| 100 |
|
|
wire [31:0] imm32;
|
| 101 |
|
|
wire [4:0] imm_shift_amount;
|
| 102 |
|
|
wire shift_imm_zero;
|
| 103 |
|
|
wire [3:0] condition;
|
| 104 |
|
|
|
| 105 |
|
|
wire [3:0] rm_sel;
|
| 106 |
|
|
wire [3:0] rs_sel;
|
| 107 |
|
|
wire [7:0] decode_load_rd;
|
| 108 |
|
|
wire [7:0] exec_load_rd;
|
| 109 |
|
|
wire [3:0] rn_sel;
|
| 110 |
|
|
wire [1:0] barrel_shift_amount_sel;
|
| 111 |
|
|
wire [1:0] barrel_shift_data_sel;
|
| 112 |
|
|
wire [1:0] barrel_shift_function;
|
| 113 |
|
|
wire [8:0] alu_function;
|
| 114 |
|
|
wire [1:0] multiply_function;
|
| 115 |
|
|
wire [2:0] interrupt_vector_sel;
|
| 116 |
|
|
wire [3:0] iaddress_sel;
|
| 117 |
|
|
wire [3:0] daddress_sel;
|
| 118 |
|
|
wire [2:0] pc_sel;
|
| 119 |
|
|
wire [1:0] byte_enable_sel;
|
| 120 |
|
|
wire [2:0] status_bits_sel;
|
| 121 |
|
|
wire [2:0] reg_write_sel;
|
| 122 |
|
|
wire user_mode_regs_store_nxt;
|
| 123 |
|
|
wire firq_not_user_mode;
|
| 124 |
|
|
|
| 125 |
|
|
wire write_data_wen;
|
| 126 |
|
|
wire copro_write_data_wen;
|
| 127 |
|
|
wire base_address_wen;
|
| 128 |
|
|
wire pc_wen;
|
| 129 |
|
|
wire [14:0] reg_bank_wen;
|
| 130 |
|
|
|
| 131 |
|
|
wire [2:0] copro_opcode1;
|
| 132 |
|
|
wire [2:0] copro_opcode2;
|
| 133 |
|
|
wire [3:0] copro_crn;
|
| 134 |
|
|
wire [3:0] copro_crm;
|
| 135 |
|
|
wire [3:0] copro_num;
|
| 136 |
|
|
wire [1:0] copro_operation;
|
| 137 |
|
|
wire [31:0] copro_read_data;
|
| 138 |
|
|
wire [31:0] copro_write_data;
|
| 139 |
|
|
wire multiply_done;
|
| 140 |
|
|
|
| 141 |
|
|
wire decode_fault;
|
| 142 |
|
|
wire iabt_trigger;
|
| 143 |
|
|
wire dabt_trigger;
|
| 144 |
|
|
|
| 145 |
|
|
wire [7:0] decode_fault_status;
|
| 146 |
|
|
wire [7:0] iabt_fault_status;
|
| 147 |
|
|
wire [7:0] dabt_fault_status;
|
| 148 |
|
|
|
| 149 |
|
|
wire [31:0] decode_fault_address;
|
| 150 |
|
|
wire [31:0] iabt_fault_address;
|
| 151 |
|
|
wire [31:0] dabt_fault_address;
|
| 152 |
|
|
|
| 153 |
|
|
wire adex;
|
| 154 |
|
|
|
| 155 |
|
|
wire [31:0] mem_read_data;
|
| 156 |
|
|
wire mem_read_data_valid;
|
| 157 |
|
|
wire [9:0] mem_load_rd;
|
| 158 |
|
|
|
| 159 |
|
|
wire [31:0] wb_read_data;
|
| 160 |
|
|
wire wb_read_data_valid;
|
| 161 |
|
|
wire [9:0] wb_load_rd;
|
| 162 |
|
|
|
| 163 |
|
|
wire dcache_wb_cached_req;
|
| 164 |
|
|
wire dcache_wb_uncached_req;
|
| 165 |
|
|
wire dcache_wb_qword;
|
| 166 |
|
|
wire dcache_wb_write;
|
| 167 |
|
|
wire [3:0] dcache_wb_byte_enable;
|
| 168 |
|
|
wire [31:0] dcache_wb_address;
|
| 169 |
|
|
wire [31:0] dcache_wb_read_data;
|
| 170 |
|
|
wire [31:0] dcache_wb_write_data;
|
| 171 |
|
|
wire dcache_wb_cached_ready;
|
| 172 |
|
|
wire dcache_wb_uncached_ready;
|
| 173 |
|
|
wire [31:0] icache_wb_address;
|
| 174 |
|
|
wire icache_wb_req;
|
| 175 |
|
|
wire icache_wb_qword;
|
| 176 |
|
|
wire [31:0] icache_wb_adr;
|
| 177 |
|
|
wire [31:0] icache_wb_read_data;
|
| 178 |
|
|
wire icache_wb_ready;
|
| 179 |
|
|
|
| 180 |
|
|
wire conflict;
|
| 181 |
|
|
|
| 182 |
|
|
|
| 183 |
|
|
// data abort has priority
|
| 184 |
|
|
assign decode_fault_status = dabt_trigger ? dabt_fault_status : iabt_fault_status;
|
| 185 |
|
|
assign decode_fault_address = dabt_trigger ? dabt_fault_address : iabt_fault_address;
|
| 186 |
|
|
assign decode_fault = dabt_trigger | iabt_trigger;
|
| 187 |
|
|
|
| 188 |
|
|
assign access_stall = fetch_stall || mem_stall;
|
| 189 |
|
|
|
| 190 |
|
|
// ======================================
|
| 191 |
|
|
// Fetch Stage
|
| 192 |
|
|
// ======================================
|
| 193 |
|
|
a25_fetch u_fetch (
|
| 194 |
|
|
.i_clk ( i_clk ),
|
| 195 |
|
|
.i_mem_stall ( mem_stall ),
|
| 196 |
|
|
.i_conflict ( conflict ),
|
| 197 |
|
|
.i_system_rdy ( i_system_rdy ),
|
| 198 |
|
|
.o_fetch_stall ( fetch_stall ),
|
| 199 |
|
|
|
| 200 |
|
|
.i_iaddress ( {execute_iaddress[31:2], 2'd0} ),
|
| 201 |
|
|
.i_iaddress_valid ( execute_iaddress_valid ),
|
| 202 |
|
|
.i_iaddress_nxt ( execute_iaddress_nxt ),
|
| 203 |
|
|
.o_fetch_instruction ( fetch_instruction ),
|
| 204 |
|
|
.i_cache_enable ( cache_enable ),
|
| 205 |
|
|
.i_cache_flush ( cache_flush ),
|
| 206 |
|
|
.i_cacheable_area ( cacheable_area ),
|
| 207 |
|
|
|
| 208 |
|
|
|
| 209 |
|
|
.o_wb_req ( icache_wb_req ),
|
| 210 |
|
|
.o_wb_qword ( icache_wb_qword ),
|
| 211 |
|
|
.o_wb_address ( icache_wb_address ),
|
| 212 |
|
|
.i_wb_read_data ( icache_wb_read_data ),
|
| 213 |
|
|
.i_wb_ready ( icache_wb_ready )
|
| 214 |
|
|
);
|
| 215 |
|
|
|
| 216 |
|
|
|
| 217 |
|
|
// ======================================
|
| 218 |
|
|
// Decode Stage
|
| 219 |
|
|
// ======================================
|
| 220 |
|
|
a25_decode u_decode (
|
| 221 |
|
|
.i_clk ( i_clk ),
|
| 222 |
|
|
.i_access_stall ( access_stall ),
|
| 223 |
|
|
|
| 224 |
|
|
// Instruction fetch or data read signals
|
| 225 |
|
|
.i_fetch_instruction ( fetch_instruction ),
|
| 226 |
|
|
.i_execute_iaddress ( execute_iaddress ),
|
| 227 |
|
|
.i_execute_daddress ( execute_daddress ),
|
| 228 |
|
|
.i_adex ( adex ),
|
| 229 |
|
|
.i_iabt ( 1'd0 ),
|
| 230 |
|
|
.i_dabt ( 1'd0 ),
|
| 231 |
|
|
.i_abt_status ( 8'd0 ),
|
| 232 |
|
|
|
| 233 |
|
|
.i_irq ( i_irq ),
|
| 234 |
|
|
.i_firq ( i_firq ),
|
| 235 |
|
|
.i_execute_status_bits ( execute_status_bits ),
|
| 236 |
|
|
.i_multiply_done ( multiply_done ),
|
| 237 |
|
|
|
| 238 |
|
|
.o_status_bits_mode ( status_bits_mode ),
|
| 239 |
|
|
.o_status_bits_irq_mask ( status_bits_irq_mask ),
|
| 240 |
|
|
.o_status_bits_firq_mask ( status_bits_firq_mask ),
|
| 241 |
|
|
.o_imm32 ( imm32 ),
|
| 242 |
|
|
.o_imm_shift_amount ( imm_shift_amount ),
|
| 243 |
|
|
.o_shift_imm_zero ( shift_imm_zero ),
|
| 244 |
|
|
.o_condition ( condition ),
|
| 245 |
|
|
.o_decode_exclusive ( decode_exclusive ),
|
| 246 |
|
|
.o_decode_iaccess ( decode_iaccess ),
|
| 247 |
|
|
.o_decode_daccess ( decode_daccess ),
|
| 248 |
|
|
.o_rm_sel ( rm_sel ),
|
| 249 |
|
|
.o_rs_sel ( rs_sel ),
|
| 250 |
|
|
.o_load_rd ( decode_load_rd ),
|
| 251 |
|
|
.o_rn_sel ( rn_sel ),
|
| 252 |
|
|
.o_barrel_shift_amount_sel ( barrel_shift_amount_sel ),
|
| 253 |
|
|
.o_barrel_shift_data_sel ( barrel_shift_data_sel ),
|
| 254 |
|
|
.o_barrel_shift_function ( barrel_shift_function ),
|
| 255 |
|
|
.o_alu_function ( alu_function ),
|
| 256 |
|
|
.o_multiply_function ( multiply_function ),
|
| 257 |
|
|
.o_interrupt_vector_sel ( interrupt_vector_sel ),
|
| 258 |
|
|
.o_iaddress_sel ( iaddress_sel ),
|
| 259 |
|
|
.o_daddress_sel ( daddress_sel ),
|
| 260 |
|
|
.o_pc_sel ( pc_sel ),
|
| 261 |
|
|
.o_byte_enable_sel ( byte_enable_sel ),
|
| 262 |
|
|
.o_status_bits_sel ( status_bits_sel ),
|
| 263 |
|
|
.o_reg_write_sel ( reg_write_sel ),
|
| 264 |
|
|
.o_user_mode_regs_store_nxt ( user_mode_regs_store_nxt ),
|
| 265 |
|
|
.o_firq_not_user_mode ( firq_not_user_mode ),
|
| 266 |
|
|
.o_write_data_wen ( write_data_wen ),
|
| 267 |
|
|
.o_base_address_wen ( base_address_wen ),
|
| 268 |
|
|
.o_pc_wen ( pc_wen ),
|
| 269 |
|
|
.o_reg_bank_wen ( reg_bank_wen ),
|
| 270 |
|
|
.o_status_bits_flags_wen ( status_bits_flags_wen ),
|
| 271 |
|
|
.o_status_bits_mode_wen ( status_bits_mode_wen ),
|
| 272 |
|
|
.o_status_bits_irq_mask_wen ( status_bits_irq_mask_wen ),
|
| 273 |
|
|
.o_status_bits_firq_mask_wen ( status_bits_firq_mask_wen ),
|
| 274 |
|
|
|
| 275 |
|
|
.o_copro_opcode1 ( copro_opcode1 ),
|
| 276 |
|
|
.o_copro_opcode2 ( copro_opcode2 ),
|
| 277 |
|
|
.o_copro_crn ( copro_crn ),
|
| 278 |
|
|
.o_copro_crm ( copro_crm ),
|
| 279 |
|
|
.o_copro_num ( copro_num ),
|
| 280 |
|
|
.o_copro_operation ( copro_operation ),
|
| 281 |
|
|
.o_copro_write_data_wen ( copro_write_data_wen ),
|
| 282 |
|
|
|
| 283 |
|
|
.o_iabt_trigger ( iabt_trigger ),
|
| 284 |
|
|
.o_iabt_address ( iabt_fault_address ),
|
| 285 |
|
|
.o_iabt_status ( iabt_fault_status ),
|
| 286 |
|
|
.o_dabt_trigger ( dabt_trigger ),
|
| 287 |
|
|
.o_dabt_address ( dabt_fault_address ),
|
| 288 |
|
|
.o_dabt_status ( dabt_fault_status ),
|
| 289 |
|
|
|
| 290 |
|
|
.o_conflict ( conflict )
|
| 291 |
|
|
);
|
| 292 |
|
|
|
| 293 |
|
|
|
| 294 |
|
|
// ======================================
|
| 295 |
|
|
// Execute Stage
|
| 296 |
|
|
// ======================================
|
| 297 |
|
|
a25_execute u_execute (
|
| 298 |
|
|
.i_clk ( i_clk ),
|
| 299 |
|
|
.i_access_stall ( access_stall ),
|
| 300 |
|
|
.i_mem_stall ( mem_stall ),
|
| 301 |
|
|
|
| 302 |
|
|
.i_wb_read_data ( wb_read_data ),
|
| 303 |
|
|
.i_wb_read_data_valid ( wb_read_data_valid ),
|
| 304 |
|
|
.i_wb_load_rd ( wb_load_rd ),
|
| 305 |
|
|
|
| 306 |
|
|
.i_copro_read_data ( copro_read_data ),
|
| 307 |
|
|
|
| 308 |
|
|
.o_write_data ( write_data ),
|
| 309 |
|
|
.o_copro_write_data ( copro_write_data ),
|
| 310 |
|
|
.o_iaddress ( execute_iaddress ),
|
| 311 |
|
|
.o_iaddress_valid ( execute_iaddress_valid ),
|
| 312 |
|
|
.o_iaddress_nxt ( execute_iaddress_nxt ),
|
| 313 |
|
|
.o_daddress ( execute_daddress ),
|
| 314 |
|
|
.o_daddress_nxt ( execute_daddress_nxt ),
|
| 315 |
|
|
.o_daddress_valid ( execute_daddress_valid ),
|
| 316 |
|
|
.o_byte_enable ( byte_enable ),
|
| 317 |
|
|
.o_write_enable ( write_enable ),
|
| 318 |
|
|
.o_exclusive ( exclusive ),
|
| 319 |
|
|
.o_priviledged ( ),
|
| 320 |
|
|
.o_exec_load_rd ( exec_load_rd ),
|
| 321 |
|
|
|
| 322 |
|
|
.o_adex ( adex ),
|
| 323 |
|
|
.o_status_bits ( execute_status_bits ),
|
| 324 |
|
|
.o_multiply_done ( multiply_done ),
|
| 325 |
|
|
|
| 326 |
|
|
.i_status_bits_mode ( status_bits_mode ),
|
| 327 |
|
|
.i_status_bits_irq_mask ( status_bits_irq_mask ),
|
| 328 |
|
|
.i_status_bits_firq_mask ( status_bits_firq_mask ),
|
| 329 |
|
|
.i_imm32 ( imm32 ),
|
| 330 |
|
|
.i_imm_shift_amount ( imm_shift_amount ),
|
| 331 |
|
|
.i_shift_imm_zero ( shift_imm_zero ),
|
| 332 |
|
|
.i_condition ( condition ),
|
| 333 |
|
|
.i_decode_exclusive ( decode_exclusive ),
|
| 334 |
|
|
.i_decode_iaccess ( decode_iaccess ),
|
| 335 |
|
|
.i_decode_daccess ( decode_daccess ),
|
| 336 |
|
|
.i_rm_sel ( rm_sel ),
|
| 337 |
|
|
.i_rs_sel ( rs_sel ),
|
| 338 |
|
|
.i_decode_load_rd ( decode_load_rd ),
|
| 339 |
|
|
.i_rn_sel ( rn_sel ),
|
| 340 |
|
|
.i_barrel_shift_amount_sel ( barrel_shift_amount_sel ),
|
| 341 |
|
|
.i_barrel_shift_data_sel ( barrel_shift_data_sel ),
|
| 342 |
|
|
.i_barrel_shift_function ( barrel_shift_function ),
|
| 343 |
|
|
.i_alu_function ( alu_function ),
|
| 344 |
|
|
.i_multiply_function ( multiply_function ),
|
| 345 |
|
|
.i_interrupt_vector_sel ( interrupt_vector_sel ),
|
| 346 |
|
|
.i_iaddress_sel ( iaddress_sel ),
|
| 347 |
|
|
.i_daddress_sel ( daddress_sel ),
|
| 348 |
|
|
.i_pc_sel ( pc_sel ),
|
| 349 |
|
|
.i_byte_enable_sel ( byte_enable_sel ),
|
| 350 |
|
|
.i_status_bits_sel ( status_bits_sel ),
|
| 351 |
|
|
.i_reg_write_sel ( reg_write_sel ),
|
| 352 |
|
|
.i_user_mode_regs_store_nxt ( user_mode_regs_store_nxt ),
|
| 353 |
|
|
.i_firq_not_user_mode ( firq_not_user_mode ),
|
| 354 |
|
|
.i_write_data_wen ( write_data_wen ),
|
| 355 |
|
|
.i_base_address_wen ( base_address_wen ),
|
| 356 |
|
|
.i_pc_wen ( pc_wen ),
|
| 357 |
|
|
.i_reg_bank_wen ( reg_bank_wen ),
|
| 358 |
|
|
.i_status_bits_flags_wen ( status_bits_flags_wen ),
|
| 359 |
|
|
.i_status_bits_mode_wen ( status_bits_mode_wen ),
|
| 360 |
|
|
.i_status_bits_irq_mask_wen ( status_bits_irq_mask_wen ),
|
| 361 |
|
|
.i_status_bits_firq_mask_wen ( status_bits_firq_mask_wen ),
|
| 362 |
|
|
.i_copro_write_data_wen ( copro_write_data_wen ),
|
| 363 |
|
|
.i_conflict ( conflict )
|
| 364 |
|
|
);
|
| 365 |
|
|
|
| 366 |
|
|
|
| 367 |
|
|
// ======================================
|
| 368 |
|
|
// Memory access stage with data cache
|
| 369 |
|
|
// ======================================
|
| 370 |
|
|
a25_mem u_mem (
|
| 371 |
|
|
.i_clk ( i_clk ),
|
| 372 |
|
|
.i_fetch_stall ( fetch_stall ),
|
| 373 |
|
|
.o_mem_stall ( mem_stall ),
|
| 374 |
|
|
|
| 375 |
|
|
.i_daddress ( execute_daddress ),
|
| 376 |
|
|
.i_daddress_valid ( execute_daddress_valid ),
|
| 377 |
|
|
.i_daddress_nxt ( execute_daddress_nxt ),
|
| 378 |
|
|
.i_write_data ( write_data ),
|
| 379 |
|
|
.i_write_enable ( write_enable ),
|
| 380 |
|
|
.i_byte_enable ( byte_enable ),
|
| 381 |
|
|
.i_exclusive ( exclusive ),
|
| 382 |
|
|
.i_exec_load_rd ( exec_load_rd ),
|
| 383 |
|
|
|
| 384 |
|
|
.o_mem_read_data ( mem_read_data ),
|
| 385 |
|
|
.o_mem_read_data_valid ( mem_read_data_valid ),
|
| 386 |
|
|
.o_mem_load_rd ( mem_load_rd ),
|
| 387 |
|
|
|
| 388 |
|
|
.i_cache_enable ( cache_enable ),
|
| 389 |
|
|
.i_cache_flush ( cache_flush ),
|
| 390 |
|
|
.i_cacheable_area ( cacheable_area ),
|
| 391 |
|
|
|
| 392 |
|
|
.o_wb_cached_req ( dcache_wb_cached_req ),
|
| 393 |
|
|
.o_wb_uncached_req ( dcache_wb_uncached_req ),
|
| 394 |
|
|
.o_wb_qword ( dcache_wb_qword ),
|
| 395 |
|
|
.o_wb_write ( dcache_wb_write ),
|
| 396 |
|
|
.o_wb_write_data ( dcache_wb_write_data ),
|
| 397 |
|
|
.o_wb_byte_enable ( dcache_wb_byte_enable ),
|
| 398 |
|
|
.o_wb_address ( dcache_wb_address ),
|
| 399 |
|
|
.i_wb_read_data ( dcache_wb_read_data ),
|
| 400 |
|
|
.i_wb_cached_ready ( dcache_wb_cached_ready ),
|
| 401 |
|
|
.i_wb_uncached_ready ( dcache_wb_uncached_ready )
|
| 402 |
|
|
);
|
| 403 |
|
|
|
| 404 |
|
|
|
| 405 |
|
|
// ======================================
|
| 406 |
|
|
// Write back stage with data cache
|
| 407 |
|
|
// ======================================
|
| 408 |
|
|
a25_write_back u_write_back (
|
| 409 |
|
|
.i_clk ( i_clk ),
|
| 410 |
|
|
.i_mem_stall ( mem_stall ),
|
| 411 |
|
|
|
| 412 |
|
|
.i_daddress ( execute_daddress ),
|
| 413 |
|
|
.i_daddress_valid ( execute_daddress_valid ),
|
| 414 |
|
|
|
| 415 |
|
|
.i_mem_read_data ( mem_read_data ),
|
| 416 |
|
|
.i_mem_read_data_valid ( mem_read_data_valid ),
|
| 417 |
|
|
.i_mem_load_rd ( mem_load_rd ),
|
| 418 |
|
|
|
| 419 |
|
|
.o_wb_read_data ( wb_read_data ),
|
| 420 |
|
|
.o_wb_read_data_valid ( wb_read_data_valid ),
|
| 421 |
|
|
.o_wb_load_rd ( wb_load_rd )
|
| 422 |
|
|
);
|
| 423 |
|
|
|
| 424 |
|
|
|
| 425 |
|
|
|
| 426 |
|
|
// ======================================
|
| 427 |
|
|
// Wishbone Master I/F
|
| 428 |
|
|
// ======================================
|
| 429 |
|
|
a25_wishbone u_wishbone (
|
| 430 |
|
|
// CPU Side
|
| 431 |
|
|
.i_clk ( i_clk ),
|
| 432 |
|
|
|
| 433 |
|
|
// Instruction Cache Accesses
|
| 434 |
|
|
.i_icache_req ( icache_wb_req ),
|
| 435 |
|
|
.i_icache_qword ( icache_wb_qword ),
|
| 436 |
|
|
.i_icache_address ( icache_wb_address ),
|
| 437 |
|
|
.o_icache_read_data ( icache_wb_read_data ),
|
| 438 |
|
|
.o_icache_ready ( icache_wb_ready ),
|
| 439 |
|
|
|
| 440 |
|
|
// Data Cache Accesses
|
| 441 |
|
|
.i_exclusive ( exclusive ),
|
| 442 |
|
|
.i_dcache_cached_req ( dcache_wb_cached_req ),
|
| 443 |
|
|
.i_dcache_uncached_req ( dcache_wb_uncached_req ),
|
| 444 |
|
|
.i_dcache_qword ( dcache_wb_qword ),
|
| 445 |
|
|
.i_dcache_write ( dcache_wb_write ),
|
| 446 |
|
|
.i_dcache_write_data ( dcache_wb_write_data ),
|
| 447 |
|
|
.i_dcache_byte_enable ( dcache_wb_byte_enable ),
|
| 448 |
|
|
.i_dcache_address ( dcache_wb_address ),
|
| 449 |
|
|
.o_dcache_read_data ( dcache_wb_read_data ),
|
| 450 |
|
|
.o_dcache_cached_ready ( dcache_wb_cached_ready ),
|
| 451 |
|
|
.o_dcache_uncached_ready ( dcache_wb_uncached_ready ),
|
| 452 |
|
|
|
| 453 |
|
|
.o_wb_adr ( o_wb_adr ),
|
| 454 |
|
|
.o_wb_sel ( o_wb_sel ),
|
| 455 |
|
|
.o_wb_we ( o_wb_we ),
|
| 456 |
|
|
.i_wb_dat ( i_wb_dat ),
|
| 457 |
|
|
.o_wb_dat ( o_wb_dat ),
|
| 458 |
|
|
.o_wb_cyc ( o_wb_cyc ),
|
| 459 |
|
|
.o_wb_stb ( o_wb_stb ),
|
| 460 |
|
|
.i_wb_ack ( i_wb_ack ),
|
| 461 |
|
|
.i_wb_err ( i_wb_err )
|
| 462 |
|
|
);
|
| 463 |
|
|
|
| 464 |
|
|
|
| 465 |
|
|
|
| 466 |
|
|
// ======================================
|
| 467 |
|
|
// Co-Processor #15
|
| 468 |
|
|
// ======================================
|
| 469 |
|
|
a25_coprocessor u_coprocessor (
|
| 470 |
|
|
.i_clk ( i_clk ),
|
| 471 |
|
|
.i_access_stall ( access_stall ),
|
| 472 |
|
|
|
| 473 |
|
|
.i_copro_opcode1 ( copro_opcode1 ),
|
| 474 |
|
|
.i_copro_opcode2 ( copro_opcode2 ),
|
| 475 |
|
|
.i_copro_crn ( copro_crn ),
|
| 476 |
|
|
.i_copro_crm ( copro_crm ),
|
| 477 |
|
|
.i_copro_num ( copro_num ),
|
| 478 |
|
|
.i_copro_operation ( copro_operation ),
|
| 479 |
|
|
.i_copro_write_data ( copro_write_data ),
|
| 480 |
|
|
|
| 481 |
|
|
.i_fault ( decode_fault ),
|
| 482 |
|
|
.i_fault_status ( decode_fault_status ),
|
| 483 |
|
|
.i_fault_address ( decode_fault_address ),
|
| 484 |
|
|
|
| 485 |
|
|
.o_copro_read_data ( copro_read_data ),
|
| 486 |
|
|
.o_cache_enable ( cache_enable ),
|
| 487 |
|
|
.o_cache_flush ( cache_flush ),
|
| 488 |
|
|
.o_cacheable_area ( cacheable_area )
|
| 489 |
|
|
);
|
| 490 |
|
|
|
| 491 |
|
|
|
| 492 |
|
|
endmodule
|
| 493 |
|
|
|
