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//////////////////////////////////////////////////////////////////

//                                                              //

//  Decode stage of Amber 25 Core                               //

//                                                              //

//  This file is part of the Amber project                      //

//  http://www.opencores.org/project,amber                      //

//                                                              //

//  Description                                                 //

//  This module is the most complex part of the Amber core      //

//  It decodes and sequences all instructions and handles all   //

//  interrupts                                                  //

//                                                              //

//  Author(s):                                                  //

//      - Conor Santifort, csantifort.amber@gmail.com           //

//                                                              //

//////////////////////////////////////////////////////////////////

//                                                              //

// Copyright (C) 2011 Authors and OPENCORES.ORG                 //

//                                                              //

// This source file may be used and distributed without         //

// restriction provided that this copyright statement is not    //

// removed from the file and that any derivative work contains  //

// the original copyright notice and the associated disclaimer. //

//                                                              //

// This source file is free software; you can redistribute it   //

// and/or modify it under the terms of the GNU Lesser General   //

// Public License as published by the Free Software Foundation; //

// either version 2.1 of the License, or (at your option) any   //

// later version.                                               //

//                                                              //

// This source is distributed in the hope that it will be       //

// useful, but WITHOUT ANY WARRANTY; without even the implied   //

// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      //

// PURPOSE.  See the GNU Lesser General Public License for more //

// details.                                                     //

//                                                              //

// You should have received a copy of the GNU Lesser General    //

// Public License along with this source; if not, download it   //

// from http://www.opencores.org/lgpl.shtml                     //

//                                                              //

//////////////////////////////////////////////////////////////////

module a25_decode

(

input                       i_clk,

input       [31:0]          i_fetch_instruction,

input                       i_access_stall,                 // stall all stages of the cpu at the same time

input                       i_irq,                          // interrupt request

input                       i_firq,                         // Fast interrupt request

input                       i_dabt,                         // data abort interrupt request

input                       i_iabt,                         // instruction pre-fetch abort flag

input                       i_adex,                         // Address Exception

input       [31:0]          i_execute_iaddress,             // Registered instruction address output by execute stage

input       [31:0]          i_execute_daddress,             // Registered instruction address output by execute stage

input       [7:0]           i_abt_status,                   // Abort status

input       [31:0]          i_execute_status_bits,          // current status bits values in execute stage

input                       i_multiply_done,                // multiply unit is nearly done

// --------------------------------------------------

// Control signals to execute stage

// --------------------------------------------------

// output reg  [4:0]           o_read_data_alignment = 1'd0,  // 2 LSBs of read address used for calculating shift in ldrb ops

output reg  [31:0]          o_imm32 = 'd0,

output reg  [4:0]           o_imm_shift_amount = 'd0,

output reg                  o_shift_imm_zero = 'd0,

output reg  [3:0]           o_condition = 4'he,             // 4'he = al

output reg                  o_decode_exclusive = 'd0,       // exclusive access request ( swap instruction )

output reg                  o_decode_iaccess = 1'd1,        // Indicates an instruction access

output reg                  o_decode_daccess = 'd0,         // Indicates a data access

output reg  [1:0]           o_status_bits_mode = 2'b11,     // SVC

output reg                  o_status_bits_irq_mask = 1'd1,

output reg                  o_status_bits_firq_mask = 1'd1,

output reg  [3:0]           o_rm_sel  = 'd0,

output reg  [3:0]           o_rs_sel  = 'd0,

output reg  [7:0]           o_load_rd = 'd0,                // [7] load flags with PC

                                                            // [6] load status bits with PC

                                                            // [5] Write into User Mode register

                                                            // [4] zero-extend load

                                                            // [3:0] destination register, Rd

output reg  [3:0]           o_rn_sel  = 'd0,

output reg  [1:0]           o_barrel_shift_amount_sel = 'd0,

output reg  [1:0]           o_barrel_shift_data_sel = 'd0,

output reg  [1:0]           o_barrel_shift_function = 'd0,

output reg  [8:0]           o_alu_function = 'd0,

output reg  [1:0]           o_multiply_function = 'd0,

output reg  [2:0]           o_interrupt_vector_sel = 'd0,

output reg  [3:0]           o_iaddress_sel = 4'd2,

output reg  [3:0]           o_daddress_sel = 4'd2,

output reg  [2:0]           o_pc_sel = 3'd2,

output reg  [1:0]           o_byte_enable_sel = 'd0,        // byte, halfword or word write

output reg  [2:0]           o_status_bits_sel = 'd0,

output reg  [2:0]           o_reg_write_sel,

output reg                  o_user_mode_regs_store_nxt,

output reg                  o_firq_not_user_mode,

output reg                  o_write_data_wen = 'd0,

output reg                  o_base_address_wen = 'd0,       // save ldm base address register

                                                            // in case of data abort

output reg                  o_pc_wen = 1'd1,

output reg  [14:0]          o_reg_bank_wen = 'd0,

output reg                  o_status_bits_flags_wen = 'd0,

output reg                  o_status_bits_mode_wen = 'd0,

output reg                  o_status_bits_irq_mask_wen = 'd0,

output reg                  o_status_bits_firq_mask_wen = 'd0,

// --------------------------------------------------

// Co-Processor interface

// --------------------------------------------------

output reg  [2:0]           o_copro_opcode1 = 'd0,

output reg  [2:0]           o_copro_opcode2 = 'd0,

output reg  [3:0]           o_copro_crn = 'd0,

output reg  [3:0]           o_copro_crm = 'd0,

output reg  [3:0]           o_copro_num = 'd0,

output reg  [1:0]           o_copro_operation = 'd0, // 0 = no operation, 

                                                     // 1 = Move to Amber Core Register from Coprocessor

                                                     // 2 = Move to Coprocessor from Amber Core Register

output reg                  o_copro_write_data_wen = 'd0,

output                      o_iabt_trigger,

output      [31:0]          o_iabt_address,

output      [7:0]           o_iabt_status,

output                      o_dabt_trigger,

output      [31:0]          o_dabt_address,

output      [7:0]           o_dabt_status,

output                      o_conflict

);

`include "a25_localparams.v"

`include "a25_functions.v"

localparam [4:0] RST_WAIT1      = 5'd0,

                 RST_WAIT2      = 5'd1,

                 INT_WAIT1      = 5'd2,

                 INT_WAIT2      = 5'd3,

                 EXECUTE        = 5'd4,

                 PRE_FETCH_EXEC = 5'd5,  // Execute the Pre-Fetched Instruction

                 MEM_WAIT1      = 5'd6,  // conditionally decode current instruction, in case

                                         // previous instruction does not execute in S2

                 MEM_WAIT2      = 5'd7,

                 PC_STALL1      = 5'd8,  // Program Counter altered

                                         // conditionally decude current instruction, in case

                                         // previous instruction does not execute in S2

                 PC_STALL2      = 5'd9,

                 MTRANS_EXEC1   = 5'd10,

                 MTRANS_EXEC2   = 5'd11,

                 MTRANS_ABORT   = 5'd12,

                 MULT_PROC1     = 5'd13,  // first cycle, save pre fetch instruction

                 MULT_PROC2     = 5'd14,  // do multiplication

                 MULT_STORE     = 5'd15,  // save RdLo

                 MULT_ACCUMU    = 5'd16,  // Accumulate add lower 32 bits

                 SWAP_WRITE     = 5'd17,

                 SWAP_WAIT1     = 5'd18,

                 SWAP_WAIT2     = 5'd19,

                 COPRO_WAIT     = 5'd20;

// ========================================================

// Internal signals

// ========================================================

wire    [31:0]         instruction;

wire                   instruction_iabt;        // abort flag, follows the instruction

wire                   instruction_adex;        // address exception flag, follows the instruction

wire    [31:0]         instruction_address;     // instruction virtual address, follows 

                                                // the instruction

wire    [7:0]          instruction_iabt_status; // abort status, follows the instruction

wire    [1:0]          instruction_sel;

reg     [3:0]          type;

wire    [3:0]          opcode;

wire    [7:0]          imm8;

wire    [31:0]         offset12;

wire    [31:0]         offset24;

wire    [4:0]          shift_imm;

wire                   opcode_compare;

wire                   mem_op;

wire                   load_op;

wire                   store_op;

wire                   write_pc;

wire                   current_write_pc;

reg                    load_pc_nxt;

reg                    load_pc_r = 'd0;

wire                   immediate_shift_op;

wire                   rds_use_rs;

wire                   branch;

wire                   mem_op_pre_indexed;

wire                   mem_op_post_indexed;

// Flop inputs

wire    [31:0]         imm32_nxt;

wire    [4:0]          imm_shift_amount_nxt;

wire                   shift_imm_zero_nxt;

wire    [3:0]          condition_nxt;

reg                    decode_exclusive_nxt;

reg                    decode_iaccess_nxt;

reg                    decode_daccess_nxt;

reg     [1:0]          barrel_shift_function_nxt;

wire    [8:0]          alu_function_nxt;

reg     [1:0]          multiply_function_nxt;

reg     [1:0]          status_bits_mode_nxt;

reg                    status_bits_irq_mask_nxt;

reg                    status_bits_firq_mask_nxt;

wire    [3:0]          rm_sel_nxt;

wire    [3:0]          rs_sel_nxt;

wire    [3:0]          rn_sel_nxt;

reg     [1:0]          barrel_shift_amount_sel_nxt;

reg     [1:0]          barrel_shift_data_sel_nxt;

reg     [3:0]          iaddress_sel_nxt;

reg     [3:0]          daddress_sel_nxt;

reg     [2:0]          pc_sel_nxt;

reg     [1:0]          byte_enable_sel_nxt;

reg     [2:0]          status_bits_sel_nxt;

reg     [2:0]          reg_write_sel_nxt;

wire                   firq_not_user_mode_nxt;

// ALU Function signals

reg                    alu_swap_sel_nxt;

reg                    alu_not_sel_nxt;

reg     [1:0]          alu_cin_sel_nxt;

reg                    alu_cout_sel_nxt;

reg     [3:0]          alu_out_sel_nxt;

reg                    write_data_wen_nxt;

reg                    copro_write_data_wen_nxt;

reg                    base_address_wen_nxt;

reg                    pc_wen_nxt;

reg     [14:0]         reg_bank_wen_nxt;

reg                    status_bits_flags_wen_nxt;

reg                    status_bits_mode_wen_nxt;

reg                    status_bits_irq_mask_wen_nxt;

reg                    status_bits_firq_mask_wen_nxt;

reg                    saved_current_instruction_wen;   // saved load instruction

reg                    pre_fetch_instruction_wen;       // pre-fetch instruction

reg     [4:0]          control_state = RST_WAIT1;

reg     [4:0]          control_state_nxt;

wire                   dabt;

reg                    dabt_reg = 'd0;

reg                    dabt_reg_d1;

reg                    iabt_reg = 'd0;

reg                    adex_reg = 'd0;

reg     [31:0]         fetch_address_r = 'd0;

reg     [7:0]          abt_status_reg = 'd0;

reg     [31:0]         fetch_instruction_r = 'd0;

reg     [31:0]         saved_current_instruction = 'd0;

reg                    saved_current_instruction_iabt = 'd0;          // access abort flag

reg                    saved_current_instruction_adex = 'd0;          // address exception

reg     [31:0]         saved_current_instruction_address = 'd0;       // virtual address of abort instruction

reg     [7:0]          saved_current_instruction_iabt_status = 'd0;   // status of abort instruction

reg     [31:0]         pre_fetch_instruction = 'd0;

reg                    pre_fetch_instruction_iabt = 'd0;              // access abort flag

reg                    pre_fetch_instruction_adex = 'd0;              // address exception

reg     [31:0]         pre_fetch_instruction_address = 'd0;           // virtual address of abort instruction

reg     [7:0]          pre_fetch_instruction_iabt_status = 'd0;       // status of abort instruction

reg     [31:0]         hold_instruction = 'd0;

reg                    hold_instruction_iabt = 'd0;                   // access abort flag

reg                    hold_instruction_adex = 'd0;                   // address exception

reg     [31:0]         hold_instruction_address = 'd0;                // virtual address of abort instruction

reg     [7:0]          hold_instruction_iabt_status = 'd0;            // status of abort instruction

wire                   instruction_valid;

wire                   instruction_execute;

reg     [3:0]          mtrans_reg1;             // the current register being accessed as part of stm/ldm

reg     [3:0]          mtrans_reg2;             // the next register being accessed as part of stm/ldm

reg     [31:0]         mtrans_instruction_nxt;

wire    [15:0]         mtrans_reg2_mask;

wire   [31:0]          mtrans_base_reg_change;

wire   [4:0]           mtrans_num_registers;

wire                   use_saved_current_instruction;

wire                   use_hold_instruction;

wire                   use_pre_fetch_instruction;

wire                   interrupt;

wire   [1:0]           interrupt_mode;

wire   [2:0]           next_interrupt;

reg                    irq = 'd0;

reg                    firq = 'd0;

wire                   firq_request;

wire                   irq_request;

wire                   swi_request;

wire                   und_request;

wire                   dabt_request;

reg    [1:0]           copro_operation_nxt;

reg                    mtrans_r15 = 'd0;

reg                    mtrans_r15_nxt;

reg                    restore_base_address = 'd0;

reg                    restore_base_address_nxt;

wire                   regop_set_flags;

wire    [7:0]          load_rd_nxt;

wire                   load_rd_byte;

wire                   ldm_user_mode;

wire                   ldm_status_bits;

wire                   ldm_flags;

wire    [6:0]          load_rd_d1_nxt;

reg     [6:0]          load_rd_d1 = 'd0;  // MSB is the valid bit

wire                   rn_valid;

wire                   rm_valid;

wire                   rs_valid;

wire                   rd_valid;

wire                   stm_valid;

wire                   rn_conflict1;

wire                   rn_conflict2;

wire                   rm_conflict1;

wire                   rm_conflict2;

wire                   rs_conflict1;

wire                   rs_conflict2;

wire                   rd_conflict1;

wire                   rd_conflict2;

wire                   stm_conflict1a;

wire                   stm_conflict1b;

wire                   stm_conflict2a;

wire                   stm_conflict2b;

wire                   conflict1;          // Register conflict1 with ldr operation

wire                   conflict2;          // Register conflict1 with ldr operation

wire                   conflict;          // Register conflict1 with ldr operation

reg                    conflict_r = 'd0;

// ========================================================

// Instruction Abort and Data Abort outputs

// ========================================================

assign o_iabt_trigger     = instruction_iabt && o_status_bits_mode == SVC && control_state == INT_WAIT1;

assign o_iabt_address     = instruction_address;

assign o_iabt_status      = instruction_iabt_status;

assign o_dabt_trigger     = dabt_reg && !dabt_reg_d1;

assign o_dabt_address     = fetch_address_r;

assign o_dabt_status      = abt_status_reg;

// ========================================================

// Instruction Decode

// ========================================================

// for instructions that take more than one cycle

// the instruction is saved in the 'saved_mem_instruction'

// register and then that register is used for the rest of

// the execution of the instruction.

// But if the instruction does not execute because of the

// condition, then need to select the next instruction to

// decode

assign use_saved_current_instruction = instruction_execute &&

                          ( control_state == MEM_WAIT1     ||

                            control_state == MEM_WAIT2     ||

                            control_state == MTRANS_EXEC1  ||

                            control_state == MTRANS_EXEC2  ||

                            control_state == MTRANS_ABORT  ||

                            control_state == MULT_PROC1    ||

                            control_state == MULT_PROC2    ||

                            control_state == MULT_ACCUMU   ||

                            control_state == MULT_STORE    ||

                            control_state == INT_WAIT1     ||

                            control_state == INT_WAIT2     ||

                            control_state == SWAP_WRITE    ||

                            control_state == SWAP_WAIT1    ||

                            control_state == SWAP_WAIT2    ||

                            control_state == COPRO_WAIT     );

assign use_hold_instruction = conflict_r;

assign use_pre_fetch_instruction = control_state == PRE_FETCH_EXEC;

assign instruction_sel  =         use_hold_instruction           ? 2'd3 :  // hold_instruction

                                  use_saved_current_instruction  ? 2'd1 :  // saved_current_instruction 

                                  use_pre_fetch_instruction      ? 2'd2 :  // pre_fetch_instruction     

                                                                   2'd0 ;  // fetch_instruction_r               

assign instruction      =         instruction_sel == 2'd0 ? fetch_instruction_r       :

                                  instruction_sel == 2'd1 ? saved_current_instruction :

                                  instruction_sel == 2'd3 ? hold_instruction          :

                                                            pre_fetch_instruction     ;

// abort flag

assign instruction_iabt =         instruction_sel == 2'd0 ? iabt_reg                       :

                                  instruction_sel == 2'd1 ? saved_current_instruction_iabt :

                                  instruction_sel == 2'd3 ? hold_instruction_iabt          :

                                                            pre_fetch_instruction_iabt     ;

assign instruction_address =      instruction_sel == 2'd0 ? fetch_address_r                   :

                                  instruction_sel == 2'd1 ? saved_current_instruction_address :

                                  instruction_sel == 2'd3 ? hold_instruction_address          :

                                                            pre_fetch_instruction_address     ;

assign instruction_iabt_status =  instruction_sel == 2'd0 ? abt_status_reg                        :

                                  instruction_sel == 2'd1 ? saved_current_instruction_iabt_status :

                                  instruction_sel == 2'd3 ? hold_instruction_iabt_status          :

                                                            pre_fetch_instruction_iabt_status     ;

// instruction address exception

assign instruction_adex =         instruction_sel == 2'd0 ? adex_reg                       :

                                  instruction_sel == 2'd1 ? saved_current_instruction_adex :

                                  instruction_sel == 2'd3 ? hold_instruction_adex          :

                                                            pre_fetch_instruction_adex     ;

// Instruction Decode - Order is important!

always @*

    casez ({instruction[27:20], instruction[7:4]})

        12'b00010?001001 : type = SWAP;

        12'b000000??1001 : type = MULT;

        12'b00?????????? : type = REGOP;

        12'b01?????????? : type = TRANS;

        12'b100????????? : type = MTRANS;

        12'b101????????? : type = BRANCH;

        12'b110????????? : type = CODTRANS;

        12'b1110???????0 : type = COREGOP;

        12'b1110???????1 : type = CORTRANS;

        default:           type = SWI;

    endcase

// ========================================================

// Fixed fields within the instruction

// ========================================================

assign opcode               = instruction[24:21];

assign condition_nxt        = instruction[31:28];

assign rm_sel_nxt           = instruction[3:0];

assign rn_sel_nxt           = branch ? 4'd15 : instruction[19:16]; // Use PC to calculate branch destination

assign rs_sel_nxt           = control_state == SWAP_WRITE  ? instruction[3:0]   : // Rm gets written out to memory

                              type == MTRANS               ? mtrans_reg1         :

                              branch                       ? 4'd15              : // Update the PC

                              rds_use_rs                   ? instruction[11:8]  :

                                                             instruction[15:12] ;

// Load from memory into registers

assign ldm_user_mode        = type == MTRANS && {instruction[22:20],instruction[15]} == 4'b1010;

assign ldm_flags            = type == MTRANS && rs_sel_nxt == 4'd15 && instruction[20] && instruction[22];

assign ldm_status_bits      = type == MTRANS && rs_sel_nxt == 4'd15 && instruction[20] && instruction[22] && i_execute_status_bits[1:0] != USR;

assign load_rd_byte         = (type == TRANS || type == SWAP) && instruction[22];

assign load_rd_nxt          = {ldm_flags, ldm_status_bits, ldm_user_mode, load_rd_byte, rs_sel_nxt};

                            // MSB indicates valid dirty target register

assign load_rd_d1_nxt       = {o_decode_daccess && !o_write_data_wen, o_load_rd[3:0]};

assign shift_imm            = instruction[11:7];

assign offset12             = { 20'h0, instruction[11:0]};

assign offset24             = {{6{instruction[23]}}, instruction[23:0], 2'd0 }; // sign extend

assign imm8                 = instruction[7:0];

assign immediate_shift_op   = instruction[25];

assign rds_use_rs           = (type == REGOP && !instruction[25] && instruction[4]) ||

                              (type == MULT &&

                               (control_state == MULT_PROC1  ||

                                control_state == MULT_PROC2  ||

                                instruction_valid && !interrupt )) ;

assign branch               = type == BRANCH;

assign opcode_compare       = opcode == CMP || opcode == CMN || opcode == TEQ || opcode == TST ;

assign mem_op               = type == TRANS;

assign load_op              = mem_op && instruction[20];

assign store_op             = mem_op && !instruction[20];

assign write_pc             = (pc_wen_nxt && pc_sel_nxt != 3'd0) || load_pc_r || load_pc_nxt;

assign current_write_pc     = (pc_wen_nxt && pc_sel_nxt != 3'd0) || load_pc_nxt;

assign regop_set_flags      = type == REGOP && instruction[20];

assign mem_op_pre_indexed   =  instruction[24] && instruction[21];

assign mem_op_post_indexed  = !instruction[24];

assign imm32_nxt            =  // add 0 to Rm

                               type == MULT               ? {  32'd0                      } :

                               // 4 x number of registers

                               type == MTRANS             ? {  mtrans_base_reg_change     } :

                               type == BRANCH             ? {  offset24                   } :

                               type == TRANS              ? {  offset12                   } :

                               instruction[11:8] == 4'h0  ? {            24'h0, imm8[7:0] } :

                               instruction[11:8] == 4'h1  ? { imm8[1:0], 24'h0, imm8[7:2] } :

                               instruction[11:8] == 4'h2  ? { imm8[3:0], 24'h0, imm8[7:4] } :

                               instruction[11:8] == 4'h3  ? { imm8[5:0], 24'h0, imm8[7:6] } :

                               instruction[11:8] == 4'h4  ? { imm8[7:0], 24'h0            } :

                               instruction[11:8] == 4'h5  ? { 2'h0,  imm8[7:0], 22'h0     } :

                               instruction[11:8] == 4'h6  ? { 4'h0,  imm8[7:0], 20'h0     } :

                               instruction[11:8] == 4'h7  ? { 6'h0,  imm8[7:0], 18'h0     } :

                               instruction[11:8] == 4'h8  ? { 8'h0,  imm8[7:0], 16'h0     } :

                               instruction[11:8] == 4'h9  ? { 10'h0, imm8[7:0], 14'h0     } :

                               instruction[11:8] == 4'ha  ? { 12'h0, imm8[7:0], 12'h0     } :

                               instruction[11:8] == 4'hb  ? { 14'h0, imm8[7:0], 10'h0     } :

                               instruction[11:8] == 4'hc  ? { 16'h0, imm8[7:0], 8'h0      } :

                               instruction[11:8] == 4'hd  ? { 18'h0, imm8[7:0], 6'h0      } :

                               instruction[11:8] == 4'he  ? { 20'h0, imm8[7:0], 4'h0      } :

                                                            { 22'h0, imm8[7:0], 2'h0      } ;

assign imm_shift_amount_nxt = shift_imm ;

       // This signal is encoded in the decode stage because 

       // it is on the critical path in the execute stage

assign shift_imm_zero_nxt   = imm_shift_amount_nxt == 5'd0 &&       // immediate amount = 0

                              barrel_shift_amount_sel_nxt == 2'd2;  // shift immediate amount

assign alu_function_nxt     = { alu_swap_sel_nxt,

                                alu_not_sel_nxt,

                                alu_cin_sel_nxt,

                                alu_cout_sel_nxt,

                                alu_out_sel_nxt  };

// ========================================================

// Register Conflict Detection

// ========================================================

assign rn_valid      = type == REGOP || type == MULT || type == SWAP || type == TRANS || type == MTRANS || type == CODTRANS;

assign rm_valid      = type == REGOP || type == MULT || type == SWAP || (type == TRANS && immediate_shift_op);

assign rs_valid      = rds_use_rs;

assign rd_valid      = type == TRANS  && store_op;           // str instruction

assign stm_valid     = type == MTRANS && !instruction[20];   // stm instruction

assign rn_conflict1   = rn_valid  && ( load_rd_d1_nxt[4] && rn_sel_nxt         == load_rd_d1_nxt[3:0] );

assign rn_conflict2   = rn_valid  && ( load_rd_d1    [4] && rn_sel_nxt         == load_rd_d1    [3:0] );

assign rm_conflict1   = rm_valid  && ( load_rd_d1_nxt[4] && rm_sel_nxt         == load_rd_d1_nxt[3:0] );

assign rm_conflict2   = rm_valid  && ( load_rd_d1    [4] && rm_sel_nxt         == load_rd_d1    [3:0] );

assign rs_conflict1   = rs_valid  && ( load_rd_d1_nxt[4] && rs_sel_nxt         == load_rd_d1_nxt[3:0] );

assign rs_conflict2   = rs_valid  && ( load_rd_d1    [4] && rs_sel_nxt         == load_rd_d1    [3:0] );

assign rd_conflict1   = rd_valid  && ( load_rd_d1_nxt[4] && instruction[15:12] == load_rd_d1_nxt[3:0] );

assign rd_conflict2   = rd_valid  && ( load_rd_d1    [4] && instruction[15:12] == load_rd_d1    [3:0] );

assign stm_conflict1a = stm_valid && ( load_rd_d1_nxt[4] && mtrans_reg1        == load_rd_d1_nxt[3:0] );

assign stm_conflict1b = stm_valid && ( load_rd_d1_nxt[4] && mtrans_reg2        == load_rd_d1_nxt[3:0] );

assign stm_conflict2a = stm_valid && ( load_rd_d1    [4] && mtrans_reg1        == load_rd_d1    [3:0] );

assign stm_conflict2b = stm_valid && ( load_rd_d1    [4] && mtrans_reg2        == load_rd_d1    [3:0] );

assign conflict1      = instruction_valid &&

                        (rn_conflict1 || rm_conflict1 || rs_conflict1 || rd_conflict1 ||

                         stm_conflict1a || stm_conflict1b);

assign conflict2      = instruction_valid &&

                        (rn_conflict2 || rm_conflict2 || rs_conflict2 || rd_conflict2 ||

                         stm_conflict2a || stm_conflict2b);

assign conflict       = conflict1 || conflict2;

always @( posedge i_clk )

    if ( !i_access_stall )

        begin

        conflict_r <= conflict;

        end

assign o_conflict = conflict;

// ========================================================

// MTRANS Operations

// ========================================================

   // Bit 15 = r15

   // Bit 0  = r0

   // In ldm and stm instructions r0 is loaded or stored first 

always @*

    casez ( instruction[15:0] )

    16'b???????????????1 : mtrans_reg1 = 4'h0 ;

    16'b??????????????10 : mtrans_reg1 = 4'h1 ;

    16'b?????????????100 : mtrans_reg1 = 4'h2 ;

    16'b????????????1000 : mtrans_reg1 = 4'h3 ;