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csantifort |
//////////////////////////////////////////////////////////////////
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// //
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// L1 Instruction Cache for Amber 25 Core //
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// //
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// This file is part of the Amber project //
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// http://www.opencores.org/project,amber //
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// //
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// Description //
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csantifort |
// Synthesizable L1 Instruction Cache. //
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// Cache is 2,3,4 or 8 way, 256 line and 16 bytes per line. //
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// a total of 16KB. The cache is read only. Writes from //
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// the core to through the data cache. //
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csantifort |
// //
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// Author(s): //
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// - Conor Santifort, csantifort.amber@gmail.com //
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// //
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//////////////////////////////////////////////////////////////////
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// //
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// Copyright (C) 2011 Authors and OPENCORES.ORG //
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// //
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// This source file may be used and distributed without //
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// restriction provided that this copyright statement is not //
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// removed from the file and that any derivative work contains //
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// the original copyright notice and the associated disclaimer. //
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// //
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// This source file is free software; you can redistribute it //
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// and/or modify it under the terms of the GNU Lesser General //
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// Public License as published by the Free Software Foundation; //
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// either version 2.1 of the License, or (at your option) any //
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// later version. //
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// //
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// This source is distributed in the hope that it will be //
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// useful, but WITHOUT ANY WARRANTY; without even the implied //
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// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //
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// PURPOSE. See the GNU Lesser General Public License for more //
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// details. //
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// //
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// You should have received a copy of the GNU Lesser General //
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// Public License along with this source; if not, download it //
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// from http://www.opencores.org/lgpl.shtml //
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// //
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//////////////////////////////////////////////////////////////////
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csantifort |
`include "global_defines.v"
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csantifort |
`include "a25_config_defines.v"
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module a25_icache
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#(
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// ---------------------------------------------------------
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// Cache Configuration
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// Limited to Linux 4k page sizes -> 256 lines
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parameter CACHE_LINES = 256,
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// This cannot be changed without some major surgeory on
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// this module
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parameter CACHE_WORDS_PER_LINE = 4,
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// Changing this parameter is the recommended
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// way to change the overall cache size; 2, 4 and 8 ways are supported.
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// 2 ways -> 8KB cache
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// 4 ways -> 16KB cache
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// 8 ways -> 32KB cache
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parameter WAYS = `A25_ICACHE_WAYS ,
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// derived configuration parameters
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parameter CACHE_ADDR_WIDTH = log2 ( CACHE_LINES ), // = 8
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parameter WORD_SEL_WIDTH = log2 ( CACHE_WORDS_PER_LINE ), // = 2
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parameter TAG_ADDR_WIDTH = 32 - CACHE_ADDR_WIDTH - WORD_SEL_WIDTH - 2, // = 20
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parameter TAG_WIDTH = TAG_ADDR_WIDTH + 1, // = 21, including Valid flag
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parameter CACHE_LINE_WIDTH = CACHE_WORDS_PER_LINE * 32, // = 128
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parameter TAG_ADDR32_LSB = CACHE_ADDR_WIDTH + WORD_SEL_WIDTH + 2, // = 12
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parameter CACHE_ADDR32_MSB = CACHE_ADDR_WIDTH + WORD_SEL_WIDTH + 2 - 1, // = 11
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parameter CACHE_ADDR32_LSB = WORD_SEL_WIDTH + 2 , // = 4
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parameter WORD_SEL_MSB = WORD_SEL_WIDTH + 2 - 1, // = 3
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parameter WORD_SEL_LSB = 2 // = 2
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// ---------------------------------------------------------
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)
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(
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input i_clk,
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input i_core_stall,
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output o_stall,
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// Read / Write requests from core
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input i_select,
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input [31:0] i_address, // registered address from execute
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input [31:0] i_address_nxt, // un-registered version of address from execute stage
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input i_cache_enable, // from co-processor 15 configuration register
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input i_cache_flush, // from co-processor 15 register
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csantifort |
output [127:0] o_read_data,
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csantifort |
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// WB Read Request
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output o_wb_req, // Read Request
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csantifort |
input [127:0] i_wb_read_data,
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csantifort |
input i_wb_ready
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);
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`include "a25_localparams.v"
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`include "a25_functions.v"
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// One-hot encoded
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localparam C_INIT = 0,
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C_CORE = 1,
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C_FILL = 2,
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C_INVA = 3,
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C_STATES = 4;
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localparam [3:0] CS_INIT = 4'd0,
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CS_IDLE = 4'd1,
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CS_FILL0 = 4'd2,
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CS_FILL1 = 4'd3,
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CS_FILL2 = 4'd4,
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CS_FILL3 = 4'd5,
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CS_FILL4 = 4'd6,
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CS_FILL_COMPLETE = 4'd7,
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CS_TURN_AROUND = 4'd8,
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CS_WRITE_HIT1 = 4'd9,
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CS_EX_DELETE = 4'd10;
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reg [3:0] c_state = CS_IDLE;
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reg [C_STATES-1:0] source_sel = 1'd1 << C_CORE;
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reg [CACHE_ADDR_WIDTH:0] init_count = 'd0;
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wire [TAG_WIDTH-1:0] tag_rdata_way [WAYS-1:0];
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wire [CACHE_LINE_WIDTH-1:0] data_rdata_way[WAYS-1:0];
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wire [WAYS-1:0] data_wenable_way;
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wire [WAYS-1:0] data_hit_way;
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wire [WAYS-1:0] tag_wenable_way;
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reg [WAYS-1:0] select_way = 'd0;
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wire [WAYS-1:0] next_way;
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reg [WAYS-1:0] valid_bits_r = 'd0;
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reg [3:0] random_num = 4'hf;
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wire [CACHE_ADDR_WIDTH-1:0] tag_address;
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wire [TAG_WIDTH-1:0] tag_wdata;
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wire tag_wenable;
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wire [CACHE_ADDR_WIDTH-1:0] data_address;
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wire [31:0] write_data_word;
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wire idle_hit;
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wire read_miss;
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wire read_miss_fill;
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wire invalid_read;
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wire fill_state;
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reg [31:0] miss_address = 'd0;
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wire [CACHE_LINE_WIDTH-1:0] hit_rdata;
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wire cache_busy_stall;
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wire read_stall;
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wire enable;
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wire [CACHE_ADDR_WIDTH-1:0] address;
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wire [31:0] address_c;
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reg [31:0] address_r = 'd0;
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reg [31:0] wb_address = 'd0;
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wire wb_hit;
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csantifort |
wire read_buf_hit;
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reg [127:0] read_buf_data_r;
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reg [31:0] read_buf_addr_r;
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reg read_buf_valid_r;
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csantifort |
genvar i;
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// ======================================
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// Address to use for cache access
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// ======================================
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// If currently stalled then the address for the next
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// cycle will be the same as it is in the current cycle
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//
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csantifort |
assign address_c = i_core_stall ? i_address :
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i_address_nxt;
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csantifort |
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assign address = address_c[CACHE_ADDR32_MSB:CACHE_ADDR32_LSB];
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csantifort |
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csantifort |
// ======================================
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// Outputs
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// ======================================
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csantifort |
assign o_read_data = wb_hit ? i_wb_read_data :
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read_buf_hit ? read_buf_data_r :
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hit_rdata ;
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csantifort |
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csantifort |
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csantifort |
// Don't allow the cache to stall the wb i/f for an exclusive access
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// The cache needs a couple of cycles to flush a potential copy of the exclusive
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// address, but the wb can do the access in parallel. So there is no
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// stall in the state CS_EX_DELETE, even though the cache is out of action.
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// This works fine as long as the wb is stalling the core
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assign o_stall = read_stall || cache_busy_stall;
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assign o_wb_req = read_miss && c_state == CS_IDLE;
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35 |
csantifort |
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// ======================================
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// Read Buffer
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// ======================================
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always@(posedge i_clk)
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if ( i_cache_flush )
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read_buf_valid_r <= 1'd0;
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else if (i_wb_ready && c_state == CS_FILL3)
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begin
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read_buf_data_r <= i_wb_read_data;
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read_buf_addr_r <= miss_address;
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read_buf_valid_r <= 1'd1;
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end
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else if (o_wb_req)
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read_buf_valid_r <= 1'd0;
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assign read_buf_hit = read_buf_valid_r && i_address[31:4] == read_buf_addr_r[31:4];
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csantifort |
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// ======================================
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// Cache State Machine
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// ======================================
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// Little State Machine to Flush Tag RAMS
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always @ ( posedge i_clk )
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if ( i_cache_flush )
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begin
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c_state <= CS_INIT;
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source_sel <= 1'd1 << C_INIT;
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init_count <= 'd0;
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`ifdef A25_CACHE_DEBUG
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`TB_DEBUG_MESSAGE
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$display("Cache Flush");
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`endif
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end
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else
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case ( c_state )
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CS_INIT :
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if ( init_count < CACHE_LINES [CACHE_ADDR_WIDTH:0] )
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begin
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init_count <= init_count + 1'd1;
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source_sel <= 1'd1 << C_INIT;
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end
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else
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begin
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source_sel <= 1'd1 << C_CORE;
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c_state <= CS_TURN_AROUND;
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end
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CS_IDLE :
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begin
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source_sel <= 1'd1 << C_CORE;
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if ( read_miss )
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35 |
csantifort |
c_state <= CS_FILL3;
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16 |
csantifort |
end
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CS_FILL3 :
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begin
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| 260 |
35 |
csantifort |
// Pick a way to write the cache update into
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// Either pick one of the invalid caches, or if all are valid, then pick
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// one randomly
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csantifort |
select_way <= next_way;
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random_num <= {random_num[2], random_num[1], random_num[0],
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random_num[3]^random_num[2]};
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// third read of burst of 4
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// wb read request asserted, wait for ack
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if ( i_wb_ready )
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begin
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| 271 |
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c_state <= CS_FILL_COMPLETE;
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end
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| 273 |
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end
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// Write the read fetch data in this cycle
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CS_FILL_COMPLETE :
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begin
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| 279 |
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// Back to normal cache operations, but
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// use physical address for first read as
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// address moved before the stall was asserted for the read_miss
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| 282 |
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// However don't use it if its a non-cached address!
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| 283 |
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source_sel <= 1'd1 << C_CORE;
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c_state <= CS_TURN_AROUND;
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end
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| 286 |
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| 287 |
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| 288 |
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// Ignore the tag read data in this cycle
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| 289 |
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// Wait 1 cycle to pre-read the cache and return to normal operation
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| 290 |
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CS_TURN_AROUND :
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| 291 |
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begin
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| 292 |
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c_state <= CS_IDLE;
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| 293 |
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end
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| 294 |
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| 295 |
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endcase
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| 296 |
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| 297 |
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| 298 |
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// ======================================
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| 299 |
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// Miss Address
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| 300 |
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// ======================================
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| 301 |
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always @ ( posedge i_clk )
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| 302 |
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if ( c_state == CS_IDLE )
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miss_address <= i_address;
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| 304 |
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| 305 |
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| 306 |
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always @ ( posedge i_clk )
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| 307 |
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address_r <= address_c;
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| 308 |
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| 309 |
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assign invalid_read = address_r != i_address;
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| 310 |
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| 311 |
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| 312 |
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always @(posedge i_clk)
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| 313 |
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if ( o_wb_req )
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| 314 |
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wb_address <= i_address;
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| 315 |
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else if ( i_wb_ready && fill_state )
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| 316 |
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wb_address <= {wb_address[31:4], wb_address[3:2] + 1'd1, 2'd0};
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| 317 |
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| 318 |
35 |
csantifort |
assign fill_state = c_state == CS_FILL3;
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| 319 |
16 |
csantifort |
assign wb_hit = i_address == wb_address && i_wb_ready && fill_state;
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| 320 |
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| 321 |
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assign tag_address = read_miss_fill ? miss_address [CACHE_ADDR32_MSB:CACHE_ADDR32_LSB] :
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| 322 |
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source_sel[C_INIT] ? init_count[CACHE_ADDR_WIDTH-1:0] :
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| 323 |
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address ;
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| 324 |
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| 325 |
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| 326 |
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assign data_address = read_miss_fill ? miss_address[CACHE_ADDR32_MSB:CACHE_ADDR32_LSB] :
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| 327 |
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address ;
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| 328 |
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| 329 |
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| 330 |
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assign tag_wdata = read_miss_fill ? {1'd1, miss_address[31:TAG_ADDR32_LSB]} :
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| 331 |
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{TAG_WIDTH{1'd0}} ;
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| 332 |
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| 333 |
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| 334 |
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assign read_miss_fill = c_state == CS_FILL3 && i_wb_ready;
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| 335 |
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| 336 |
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| 337 |
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| 338 |
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assign tag_wenable = read_miss_fill ? 1'd1 :
|
| 339 |
|
|
source_sel[C_INVA] ? 1'd1 :
|
| 340 |
|
|
source_sel[C_FILL] ? 1'd1 :
|
| 341 |
|
|
source_sel[C_INIT] ? 1'd1 :
|
| 342 |
|
|
source_sel[C_CORE] ? 1'd0 :
|
| 343 |
|
|
1'd0 ;
|
| 344 |
|
|
|
| 345 |
|
|
|
| 346 |
|
|
assign enable = i_select && i_cache_enable;
|
| 347 |
|
|
|
| 348 |
|
|
assign idle_hit = |data_hit_way;
|
| 349 |
|
|
|
| 350 |
|
|
assign read_miss = enable && !idle_hit && !invalid_read;
|
| 351 |
|
|
|
| 352 |
35 |
csantifort |
assign read_stall = enable && !idle_hit && !wb_hit && !read_buf_hit;
|
| 353 |
16 |
csantifort |
|
| 354 |
35 |
csantifort |
assign cache_busy_stall = (c_state == CS_TURN_AROUND && enable && !read_buf_hit) || c_state == CS_INIT;
|
| 355 |
16 |
csantifort |
|
| 356 |
|
|
|
| 357 |
|
|
// ======================================
|
| 358 |
|
|
// Instantiate RAMS
|
| 359 |
|
|
// ======================================
|
| 360 |
|
|
|
| 361 |
|
|
generate
|
| 362 |
|
|
for ( i=0; i<WAYS;i=i+1 ) begin : rams
|
| 363 |
|
|
|
| 364 |
|
|
// Tag RAMs
|
| 365 |
|
|
`ifdef XILINX_SPARTAN6_FPGA
|
| 366 |
|
|
xs6_sram_256x21_line_en
|
| 367 |
|
|
`endif
|
| 368 |
|
|
|
| 369 |
|
|
`ifdef XILINX_VIRTEX6_FPGA
|
| 370 |
|
|
xv6_sram_256x21_line_en
|
| 371 |
|
|
`endif
|
| 372 |
|
|
|
| 373 |
|
|
`ifndef XILINX_FPGA
|
| 374 |
|
|
generic_sram_line_en
|
| 375 |
|
|
`endif
|
| 376 |
|
|
|
| 377 |
|
|
#(
|
| 378 |
|
|
.DATA_WIDTH ( TAG_WIDTH ),
|
| 379 |
|
|
.INITIALIZE_TO_ZERO ( 1 ),
|
| 380 |
|
|
.ADDRESS_WIDTH ( CACHE_ADDR_WIDTH ))
|
| 381 |
|
|
u_tag (
|
| 382 |
|
|
.i_clk ( i_clk ),
|
| 383 |
|
|
.i_write_data ( tag_wdata ),
|
| 384 |
|
|
.i_write_enable ( tag_wenable_way[i] ),
|
| 385 |
|
|
.i_address ( tag_address ),
|
| 386 |
|
|
|
| 387 |
|
|
.o_read_data ( tag_rdata_way[i] )
|
| 388 |
|
|
);
|
| 389 |
|
|
|
| 390 |
|
|
// Data RAMs
|
| 391 |
|
|
`ifdef XILINX_SPARTAN6_FPGA
|
| 392 |
|
|
xs6_sram_256x128_byte_en
|
| 393 |
|
|
`endif
|
| 394 |
|
|
|
| 395 |
|
|
`ifdef XILINX_VIRTEX6_FPGA
|
| 396 |
|
|
xv6_sram_256x128_byte_en
|
| 397 |
|
|
`endif
|
| 398 |
|
|
|
| 399 |
|
|
`ifndef XILINX_FPGA
|
| 400 |
|
|
generic_sram_byte_en
|
| 401 |
|
|
`endif
|
| 402 |
|
|
|
| 403 |
|
|
#(
|
| 404 |
|
|
.DATA_WIDTH ( CACHE_LINE_WIDTH) ,
|
| 405 |
|
|
.ADDRESS_WIDTH ( CACHE_ADDR_WIDTH) )
|
| 406 |
|
|
u_data (
|
| 407 |
|
|
.i_clk ( i_clk ),
|
| 408 |
35 |
csantifort |
.i_write_data ( i_wb_read_data ),
|
| 409 |
16 |
csantifort |
.i_write_enable ( data_wenable_way[i] ),
|
| 410 |
|
|
.i_address ( data_address ),
|
| 411 |
|
|
.i_byte_enable ( {CACHE_LINE_WIDTH/8{1'd1}} ),
|
| 412 |
|
|
.o_read_data ( data_rdata_way[i] )
|
| 413 |
|
|
);
|
| 414 |
|
|
|
| 415 |
|
|
|
| 416 |
|
|
// Per tag-ram write-enable
|
| 417 |
|
|
assign tag_wenable_way[i] = tag_wenable && ( select_way[i] || source_sel[C_INIT] );
|
| 418 |
|
|
|
| 419 |
|
|
// Per data-ram write-enable
|
| 420 |
|
|
assign data_wenable_way[i] = ( source_sel[C_FILL] || read_miss_fill ) && select_way[i];
|
| 421 |
|
|
|
| 422 |
|
|
// Per data-ram idle_hit flag
|
| 423 |
|
|
assign data_hit_way[i] = tag_rdata_way[i][TAG_WIDTH-1] &&
|
| 424 |
|
|
tag_rdata_way[i][TAG_ADDR_WIDTH-1:0] == i_address[31:TAG_ADDR32_LSB] &&
|
| 425 |
|
|
c_state == CS_IDLE;
|
| 426 |
|
|
end
|
| 427 |
|
|
endgenerate
|
| 428 |
|
|
|
| 429 |
|
|
|
| 430 |
|
|
// ======================================
|
| 431 |
|
|
// Register Valid Bits
|
| 432 |
|
|
// ======================================
|
| 433 |
|
|
generate
|
| 434 |
|
|
if ( WAYS == 2 ) begin : valid_bits_2ways
|
| 435 |
|
|
|
| 436 |
|
|
always @ ( posedge i_clk )
|
| 437 |
|
|
if ( c_state == CS_IDLE )
|
| 438 |
|
|
valid_bits_r <= {tag_rdata_way[1][TAG_WIDTH-1],
|
| 439 |
|
|
tag_rdata_way[0][TAG_WIDTH-1]};
|
| 440 |
|
|
|
| 441 |
|
|
end
|
| 442 |
|
|
else if ( WAYS == 3 ) begin : valid_bits_3ways
|
| 443 |
|
|
|
| 444 |
|
|
always @ ( posedge i_clk )
|
| 445 |
|
|
if ( c_state == CS_IDLE )
|
| 446 |
|
|
valid_bits_r <= {tag_rdata_way[2][TAG_WIDTH-1],
|
| 447 |
|
|
tag_rdata_way[1][TAG_WIDTH-1],
|
| 448 |
|
|
tag_rdata_way[0][TAG_WIDTH-1]};
|
| 449 |
|
|
|
| 450 |
|
|
end
|
| 451 |
|
|
else if ( WAYS == 4 ) begin : valid_bits_4ways
|
| 452 |
|
|
|
| 453 |
|
|
always @ ( posedge i_clk )
|
| 454 |
|
|
if ( c_state == CS_IDLE )
|
| 455 |
|
|
valid_bits_r <= {tag_rdata_way[3][TAG_WIDTH-1],
|
| 456 |
|
|
tag_rdata_way[2][TAG_WIDTH-1],
|
| 457 |
|
|
tag_rdata_way[1][TAG_WIDTH-1],
|
| 458 |
|
|
tag_rdata_way[0][TAG_WIDTH-1]};
|
| 459 |
|
|
|
| 460 |
|
|
end
|
| 461 |
|
|
else begin : valid_bits_8ways
|
| 462 |
|
|
|
| 463 |
|
|
always @ ( posedge i_clk )
|
| 464 |
|
|
if ( c_state == CS_IDLE )
|
| 465 |
|
|
valid_bits_r <= {tag_rdata_way[7][TAG_WIDTH-1],
|
| 466 |
|
|
tag_rdata_way[6][TAG_WIDTH-1],
|
| 467 |
|
|
tag_rdata_way[5][TAG_WIDTH-1],
|
| 468 |
|
|
tag_rdata_way[4][TAG_WIDTH-1],
|
| 469 |
|
|
tag_rdata_way[3][TAG_WIDTH-1],
|
| 470 |
|
|
tag_rdata_way[2][TAG_WIDTH-1],
|
| 471 |
|
|
tag_rdata_way[1][TAG_WIDTH-1],
|
| 472 |
|
|
tag_rdata_way[0][TAG_WIDTH-1]};
|
| 473 |
|
|
|
| 474 |
|
|
end
|
| 475 |
|
|
endgenerate
|
| 476 |
|
|
|
| 477 |
|
|
|
| 478 |
|
|
// ======================================
|
| 479 |
|
|
// Select read hit data
|
| 480 |
|
|
// ======================================
|
| 481 |
|
|
generate
|
| 482 |
|
|
if ( WAYS == 2 ) begin : read_data_2ways
|
| 483 |
|
|
|
| 484 |
|
|
assign hit_rdata = data_hit_way[0] ? data_rdata_way[0] :
|
| 485 |
|
|
data_hit_way[1] ? data_rdata_way[1] :
|
| 486 |
|
|
{CACHE_LINE_WIDTH{1'd1}} ; // all 1's for debug
|
| 487 |
|
|
|
| 488 |
|
|
end
|
| 489 |
|
|
else if ( WAYS == 3 ) begin : read_data_3ways
|
| 490 |
|
|
|
| 491 |
|
|
assign hit_rdata = data_hit_way[0] ? data_rdata_way[0] :
|
| 492 |
|
|
data_hit_way[1] ? data_rdata_way[1] :
|
| 493 |
|
|
data_hit_way[2] ? data_rdata_way[2] :
|
| 494 |
|
|
{CACHE_LINE_WIDTH{1'd1}} ; // all 1's for debug
|
| 495 |
|
|
|
| 496 |
|
|
end
|
| 497 |
|
|
else if ( WAYS == 4 ) begin : read_data_4ways
|
| 498 |
|
|
|
| 499 |
|
|
assign hit_rdata = data_hit_way[0] ? data_rdata_way[0] :
|
| 500 |
|
|
data_hit_way[1] ? data_rdata_way[1] :
|
| 501 |
|
|
data_hit_way[2] ? data_rdata_way[2] :
|
| 502 |
|
|
data_hit_way[3] ? data_rdata_way[3] :
|
| 503 |
|
|
{CACHE_LINE_WIDTH{1'd1}} ; // all 1's for debug
|
| 504 |
|
|
|
| 505 |
|
|
end
|
| 506 |
|
|
else begin : read_data_8ways
|
| 507 |
|
|
|
| 508 |
|
|
assign hit_rdata = data_hit_way[0] ? data_rdata_way[0] :
|
| 509 |
|
|
data_hit_way[1] ? data_rdata_way[1] :
|
| 510 |
|
|
data_hit_way[2] ? data_rdata_way[2] :
|
| 511 |
|
|
data_hit_way[3] ? data_rdata_way[3] :
|
| 512 |
|
|
data_hit_way[4] ? data_rdata_way[4] :
|
| 513 |
|
|
data_hit_way[5] ? data_rdata_way[5] :
|
| 514 |
|
|
data_hit_way[6] ? data_rdata_way[6] :
|
| 515 |
|
|
data_hit_way[7] ? data_rdata_way[7] :
|
| 516 |
|
|
{CACHE_LINE_WIDTH{1'd1}} ; // all 1's for debug
|
| 517 |
|
|
|
| 518 |
|
|
end
|
| 519 |
|
|
endgenerate
|
| 520 |
|
|
|
| 521 |
|
|
|
| 522 |
|
|
// ======================================
|
| 523 |
|
|
// Function to select the way to use
|
| 524 |
|
|
// for fills
|
| 525 |
|
|
// ======================================
|
| 526 |
|
|
generate
|
| 527 |
|
|
if ( WAYS == 2 ) begin : pick_way_2ways
|
| 528 |
|
|
|
| 529 |
|
|
assign next_way = pick_way ( valid_bits_r, random_num );
|
| 530 |
|
|
|
| 531 |
|
|
function [WAYS-1:0] pick_way;
|
| 532 |
|
|
input [WAYS-1:0] valid_bits;
|
| 533 |
|
|
input [3:0] random_num;
|
| 534 |
|
|
begin
|
| 535 |
|
|
if ( valid_bits[0] == 1'd0 )
|
| 536 |
|
|
// way 0 not occupied so use it
|
| 537 |
|
|
pick_way = 2'b01;
|
| 538 |
|
|
else if ( valid_bits[1] == 1'd0 )
|
| 539 |
|
|
// way 1 not occupied so use it
|
| 540 |
|
|
pick_way = 2'b10;
|
| 541 |
|
|
else
|
| 542 |
|
|
begin
|
| 543 |
|
|
// All ways occupied so pick one randomly
|
| 544 |
|
|
case (random_num[3:1])
|
| 545 |
|
|
3'd0, 3'd3,
|
| 546 |
|
|
3'd5, 3'd6: pick_way = 2'b10;
|
| 547 |
|
|
default: pick_way = 2'b01;
|
| 548 |
|
|
endcase
|
| 549 |
|
|
end
|
| 550 |
|
|
end
|
| 551 |
|
|
endfunction
|
| 552 |
|
|
|
| 553 |
|
|
end
|
| 554 |
|
|
else if ( WAYS == 3 ) begin : pick_way_3ways
|
| 555 |
|
|
|
| 556 |
|
|
assign next_way = pick_way ( valid_bits_r, random_num );
|
| 557 |
|
|
|
| 558 |
|
|
function [WAYS-1:0] pick_way;
|
| 559 |
|
|
input [WAYS-1:0] valid_bits;
|
| 560 |
|
|
input [3:0] random_num;
|
| 561 |
|
|
begin
|
| 562 |
|
|
if ( valid_bits[0] == 1'd0 )
|
| 563 |
|
|
// way 0 not occupied so use it
|
| 564 |
|
|
pick_way = 3'b001;
|
| 565 |
|
|
else if ( valid_bits[1] == 1'd0 )
|
| 566 |
|
|
// way 1 not occupied so use it
|
| 567 |
|
|
pick_way = 3'b010;
|
| 568 |
|
|
else if ( valid_bits[2] == 1'd0 )
|
| 569 |
|
|
// way 2 not occupied so use it
|
| 570 |
|
|
pick_way = 3'b100;
|
| 571 |
|
|
else
|
| 572 |
|
|
begin
|
| 573 |
|
|
// All ways occupied so pick one randomly
|
| 574 |
|
|
case (random_num[3:1])
|
| 575 |
|
|
3'd0, 3'd1, 3'd2: pick_way = 3'b010;
|
| 576 |
|
|
3'd2, 3'd3, 3'd4: pick_way = 3'b100;
|
| 577 |
|
|
default: pick_way = 3'b001;
|
| 578 |
|
|
endcase
|
| 579 |
|
|
end
|
| 580 |
|
|
end
|
| 581 |
|
|
endfunction
|
| 582 |
|
|
|
| 583 |
|
|
end
|
| 584 |
|
|
else if ( WAYS == 4 ) begin : pick_way_4ways
|
| 585 |
|
|
|
| 586 |
|
|
assign next_way = pick_way ( valid_bits_r, random_num );
|
| 587 |
|
|
|
| 588 |
|
|
function [WAYS-1:0] pick_way;
|
| 589 |
|
|
input [WAYS-1:0] valid_bits;
|
| 590 |
|
|
input [3:0] random_num;
|
| 591 |
|
|
begin
|
| 592 |
|
|
if ( valid_bits[0] == 1'd0 )
|
| 593 |
|
|
// way 0 not occupied so use it
|
| 594 |
|
|
pick_way = 4'b0001;
|
| 595 |
|
|
else if ( valid_bits[1] == 1'd0 )
|
| 596 |
|
|
// way 1 not occupied so use it
|
| 597 |
|
|
pick_way = 4'b0010;
|
| 598 |
|
|
else if ( valid_bits[2] == 1'd0 )
|
| 599 |
|
|
// way 2 not occupied so use it
|
| 600 |
|
|
pick_way = 4'b0100;
|
| 601 |
|
|
else if ( valid_bits[3] == 1'd0 )
|
| 602 |
|
|
// way 3 not occupied so use it
|
| 603 |
|
|
pick_way = 4'b1000;
|
| 604 |
|
|
else
|
| 605 |
|
|
begin
|
| 606 |
|
|
// All ways occupied so pick one randomly
|
| 607 |
|
|
case (random_num[3:1])
|
| 608 |
|
|
3'd0, 3'd1: pick_way = 4'b0100;
|
| 609 |
|
|
3'd2, 3'd3: pick_way = 4'b1000;
|
| 610 |
|
|
3'd4, 3'd5: pick_way = 4'b0001;
|
| 611 |
|
|
default: pick_way = 4'b0010;
|
| 612 |
|
|
endcase
|
| 613 |
|
|
end
|
| 614 |
|
|
end
|
| 615 |
|
|
endfunction
|
| 616 |
|
|
|
| 617 |
|
|
end
|
| 618 |
|
|
else begin : pick_way_8ways
|
| 619 |
|
|
|
| 620 |
|
|
assign next_way = pick_way ( valid_bits_r, random_num );
|
| 621 |
|
|
|
| 622 |
|
|
function [WAYS-1:0] pick_way;
|
| 623 |
|
|
input [WAYS-1:0] valid_bits;
|
| 624 |
|
|
input [3:0] random_num;
|
| 625 |
|
|
begin
|
| 626 |
|
|
if ( valid_bits[0] == 1'd0 )
|
| 627 |
|
|
// way 0 not occupied so use it
|
| 628 |
|
|
pick_way = 8'b00000001;
|
| 629 |
|
|
else if ( valid_bits[1] == 1'd0 )
|
| 630 |
|
|
// way 1 not occupied so use it
|
| 631 |
|
|
pick_way = 8'b00000010;
|
| 632 |
|
|
else if ( valid_bits[2] == 1'd0 )
|
| 633 |
|
|
// way 2 not occupied so use it
|
| 634 |
|
|
pick_way = 8'b00000100;
|
| 635 |
|
|
else if ( valid_bits[3] == 1'd0 )
|
| 636 |
|
|
// way 3 not occupied so use it
|
| 637 |
|
|
pick_way = 8'b00001000;
|
| 638 |
|
|
else if ( valid_bits[4] == 1'd0 )
|
| 639 |
|
|
// way 3 not occupied so use it
|
| 640 |
|
|
pick_way = 8'b00010000;
|
| 641 |
|
|
else if ( valid_bits[5] == 1'd0 )
|
| 642 |
|
|
// way 3 not occupied so use it
|
| 643 |
|
|
pick_way = 8'b00100000;
|
| 644 |
|
|
else if ( valid_bits[6] == 1'd0 )
|
| 645 |
|
|
// way 3 not occupied so use it
|
| 646 |
|
|
pick_way = 8'b01000000;
|
| 647 |
|
|
else if ( valid_bits[7] == 1'd0 )
|
| 648 |
|
|
// way 3 not occupied so use it
|
| 649 |
|
|
pick_way = 8'b10000000;
|
| 650 |
|
|
else
|
| 651 |
|
|
begin
|
| 652 |
|
|
// All ways occupied so pick one randomly
|
| 653 |
|
|
case (random_num[3:1])
|
| 654 |
|
|
3'd0: pick_way = 8'b00010000;
|
| 655 |
|
|
3'd1: pick_way = 8'b00100000;
|
| 656 |
|
|
3'd2: pick_way = 8'b01000000;
|
| 657 |
|
|
3'd3: pick_way = 8'b10000000;
|
| 658 |
|
|
3'd4: pick_way = 8'b00000001;
|
| 659 |
|
|
3'd5: pick_way = 8'b00000010;
|
| 660 |
|
|
3'd6: pick_way = 8'b00000100;
|
| 661 |
|
|
default: pick_way = 8'b00001000;
|
| 662 |
|
|
endcase
|
| 663 |
|
|
end
|
| 664 |
|
|
end
|
| 665 |
|
|
endfunction
|
| 666 |
|
|
|
| 667 |
|
|
end
|
| 668 |
|
|
endgenerate
|
| 669 |
|
|
|
| 670 |
|
|
|
| 671 |
|
|
// ========================================================
|
| 672 |
|
|
// Debug WB bus - not synthesizable
|
| 673 |
|
|
// ========================================================
|
| 674 |
|
|
//synopsys translate_off
|
| 675 |
|
|
wire [(6*8)-1:0] xSOURCE_SEL;
|
| 676 |
|
|
wire [(20*8)-1:0] xC_STATE;
|
| 677 |
|
|
|
| 678 |
|
|
assign xSOURCE_SEL = source_sel[C_CORE] ? "C_CORE" :
|
| 679 |
|
|
source_sel[C_INIT] ? "C_INIT" :
|
| 680 |
|
|
source_sel[C_FILL] ? "C_FILL" :
|
| 681 |
|
|
source_sel[C_INVA] ? "C_INVA" :
|
| 682 |
|
|
"UNKNON" ;
|
| 683 |
|
|
|
| 684 |
|
|
assign xC_STATE = c_state == CS_INIT ? "CS_INIT" :
|
| 685 |
|
|
c_state == CS_IDLE ? "CS_IDLE" :
|
| 686 |
|
|
c_state == CS_FILL0 ? "CS_FILL0" :
|
| 687 |
|
|
c_state == CS_FILL1 ? "CS_FILL1" :
|
| 688 |
|
|
c_state == CS_FILL2 ? "CS_FILL2" :
|
| 689 |
|
|
c_state == CS_FILL3 ? "CS_FILL3" :
|
| 690 |
|
|
c_state == CS_FILL4 ? "CS_FILL4" :
|
| 691 |
|
|
c_state == CS_FILL_COMPLETE ? "CS_FILL_COMPLETE" :
|
| 692 |
|
|
c_state == CS_EX_DELETE ? "CS_EX_DELETE" :
|
| 693 |
|
|
c_state == CS_TURN_AROUND ? "CS_TURN_AROUND" :
|
| 694 |
|
|
c_state == CS_WRITE_HIT1 ? "CS_WRITE_HIT1" :
|
| 695 |
|
|
"UNKNOWN" ;
|
| 696 |
|
|
|
| 697 |
|
|
|
| 698 |
|
|
generate
|
| 699 |
|
|
if ( WAYS == 2 ) begin : check_hit_2ways
|
| 700 |
|
|
|
| 701 |
|
|
always @( posedge i_clk )
|
| 702 |
|
|
if ( (data_hit_way[0] + data_hit_way[1] ) > 4'd1 )
|
| 703 |
|
|
begin
|
| 704 |
|
|
`TB_ERROR_MESSAGE
|
| 705 |
|
|
$display("Hit in more than one cache ways!");
|
| 706 |
|
|
end
|
| 707 |
|
|
|
| 708 |
|
|
end
|
| 709 |
|
|
else if ( WAYS == 3 ) begin : check_hit_3ways
|
| 710 |
|
|
|
| 711 |
|
|
always @( posedge i_clk )
|
| 712 |
|
|
if ( (data_hit_way[0] + data_hit_way[1] + data_hit_way[2] ) > 4'd1 )
|
| 713 |
|
|
begin
|
| 714 |
|
|
`TB_ERROR_MESSAGE
|
| 715 |
|
|
$display("Hit in more than one cache ways!");
|
| 716 |
|
|
end
|
| 717 |
|
|
|
| 718 |
|
|
end
|
| 719 |
|
|
else if ( WAYS == 4 ) begin : check_hit_4ways
|
| 720 |
|
|
|
| 721 |
|
|
always @( posedge i_clk )
|
| 722 |
|
|
if ( (data_hit_way[0] + data_hit_way[1] +
|
| 723 |
|
|
data_hit_way[2] + data_hit_way[3] ) > 4'd1 )
|
| 724 |
|
|
begin
|
| 725 |
|
|
`TB_ERROR_MESSAGE
|
| 726 |
|
|
$display("Hit in more than one cache ways!");
|
| 727 |
|
|
end
|
| 728 |
|
|
|
| 729 |
|
|
end
|
| 730 |
|
|
else if ( WAYS == 8 ) begin : check_hit_8ways
|
| 731 |
|
|
|
| 732 |
|
|
always @( posedge i_clk )
|
| 733 |
|
|
if ( (data_hit_way[0] + data_hit_way[1] +
|
| 734 |
|
|
data_hit_way[2] + data_hit_way[3] +
|
| 735 |
|
|
data_hit_way[4] + data_hit_way[5] +
|
| 736 |
|
|
data_hit_way[6] + data_hit_way[7] ) > 4'd1 )
|
| 737 |
|
|
begin
|
| 738 |
|
|
`TB_ERROR_MESSAGE
|
| 739 |
|
|
$display("Hit in more than one cache ways!");
|
| 740 |
|
|
end
|
| 741 |
|
|
|
| 742 |
|
|
end
|
| 743 |
|
|
else begin : check_hit_nways
|
| 744 |
|
|
|
| 745 |
|
|
initial
|
| 746 |
|
|
begin
|
| 747 |
|
|
`TB_ERROR_MESSAGE
|
| 748 |
|
|
$display("Unsupported number of ways %0d", WAYS);
|
| 749 |
|
|
$display("Set A25_ICACHE_WAYS in a25_config_defines.v to either 2,3,4 or 8");
|
| 750 |
|
|
end
|
| 751 |
|
|
|
| 752 |
|
|
end
|
| 753 |
|
|
endgenerate
|
| 754 |
|
|
|
| 755 |
|
|
//synopsys translate_on
|
| 756 |
|
|
|
| 757 |
|
|
endmodule
|
| 758 |
|
|
|
