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1 16 csantifort
//////////////////////////////////////////////////////////////////
2
//                                                              //
3
//  Wishbone master interface for the Amber 25 core             //
4
//                                                              //
5
//  This file is part of the Amber project                      //
6
//  http://www.opencores.org/project,amber                      //
7
//                                                              //
8
//  Description                                                 //
9
//  Turns memory access requests from the execute stage and     //
10 17 csantifort
//  instruction and data caches into wishbone bus cycles.       //
11
//  For 4-word read requests from either cache and swap         //
12
//  accesses ( read followed by write to the same address)      //
13
//  from the execute stage, a block transfer is done.           //
14
//  All other requests result in single word transfers.         //
15 16 csantifort
//                                                              //
16
//  Write accesses can be done in a single clock cycle on       //
17
//  the wishbone bus, is the destination allows it. The         //
18
//  next transfer will begin immediately on the                 //
19
//  next cycle on the bus. This looks like a block transfer     //
20
//  and does hold ownership of the wishbone bus, preventing     //
21
//  the other master ( the ethernet MAC) from gaining           //
22
//  ownership between those two cycles. But otherwise it would  //
23
//  be necessary to insert a wait cycle after every write,      //
24
//  slowing down the performance of the core by around 5 to     //
25
//  10%.                                                        //
26
//                                                              //
27
//  Author(s):                                                  //
28
//      - Conor Santifort, csantifort.amber@gmail.com           //
29
//                                                              //
30
//////////////////////////////////////////////////////////////////
31
//                                                              //
32
// Copyright (C) 2011 Authors and OPENCORES.ORG                 //
33
//                                                              //
34
// This source file may be used and distributed without         //
35
// restriction provided that this copyright statement is not    //
36
// removed from the file and that any derivative work contains  //
37
// the original copyright notice and the associated disclaimer. //
38
//                                                              //
39
// This source file is free software; you can redistribute it   //
40
// and/or modify it under the terms of the GNU Lesser General   //
41
// Public License as published by the Free Software Foundation; //
42
// either version 2.1 of the License, or (at your option) any   //
43
// later version.                                               //
44
//                                                              //
45
// This source is distributed in the hope that it will be       //
46
// useful, but WITHOUT ANY WARRANTY; without even the implied   //
47
// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      //
48
// PURPOSE.  See the GNU Lesser General Public License for more //
49
// details.                                                     //
50
//                                                              //
51
// You should have received a copy of the GNU Lesser General    //
52
// Public License along with this source; if not, download it   //
53
// from http://www.opencores.org/lgpl.shtml                     //
54
//                                                              //
55
//////////////////////////////////////////////////////////////////
56
 
57
 
58
module a25_wishbone
59
(
60
input                       i_clk,
61
 
62
    // Instruction Cache Accesses
63
input                       i_icache_req,
64
input                       i_icache_qword,
65
input       [31:0]          i_icache_address,
66
output      [31:0]          o_icache_read_data,
67
output                      o_icache_ready,
68
 
69
    // Data Cache Accesses
70
input                       i_exclusive,      // high for read part of swap access
71
input                       i_dcache_cached_req,
72
input                       i_dcache_uncached_req,
73
input                       i_dcache_qword,
74
input                       i_dcache_write,
75
input       [31:0]          i_dcache_write_data,
76
input       [3:0]           i_dcache_byte_enable,    // valid for writes only
77
input       [31:0]          i_dcache_address,
78
output      [31:0]          o_dcache_read_data,
79
output                      o_dcache_cached_ready,
80
output                      o_dcache_uncached_ready,
81
 
82
// Wishbone Bus
83
output reg  [31:0]          o_wb_adr = 'd0,
84
output reg  [3:0]           o_wb_sel = 'd0,
85
output reg                  o_wb_we  = 'd0,
86
input       [31:0]          i_wb_dat,
87
output reg  [31:0]          o_wb_dat = 'd0,
88
output reg                  o_wb_cyc = 'd0,
89
output reg                  o_wb_stb = 'd0,
90
input                       i_wb_ack,
91
input                       i_wb_err
92
 
93
);
94
 
95
 
96
localparam [3:0] WB_IDLE            = 3'd0,
97
                 WB_BURST1          = 3'd1,
98
                 WB_BURST2          = 3'd2,
99
                 WB_BURST3          = 3'd3,
100
                 WB_WAIT_ACK        = 3'd4;
101
 
102
reg     [2:0]               wishbone_st = WB_IDLE;
103
 
104
wire                        icache_read_req_c;
105
wire                        icache_read_qword_c;
106
wire    [31:0]              icache_read_addr_c;
107
wire                        dcache_read_qword_c;
108
 
109
wire                        dcache_req_c;
110
wire                        write_req_c;
111
wire                        dcache_cached_rreq_c;
112
wire                        dcache_cached_wreq_c;
113
wire                        dcache_uncached_rreq_c;
114
wire                        dcache_uncached_wreq_c;
115
 
116
wire                        dcache_cached_rreq_in;
117
wire                        dcache_cached_wreq_in;
118
wire                        dcache_uncached_rreq_in;
119
wire                        dcache_uncached_wreq_in;
120
 
121
reg                         dcache_cached_rreq_r   = 'd0;
122
reg                         dcache_cached_wreq_r   = 'd0;
123
reg                         dcache_uncached_rreq_r = 'd0;
124
reg                         dcache_uncached_wreq_r = 'd0;
125
 
126
wire                        dcache_cached_wready;
127
wire                        dcache_uncached_wready;
128
wire                        dcache_cached_rready;
129
wire                        dcache_uncached_rready;
130
 
131
wire                        start_access;
132
wire    [3:0]               byte_enable;
133
reg                         exclusive_access = 'd0;
134
wire                        read_ack;
135
wire                        wait_write_ack;
136
reg                         icache_read_req_r  = 'd0;
137
reg                         icache_read_qword_r  = 'd0;
138
reg     [31:0]              icache_read_addr_r  = 'd0;
139
reg                         dcache_read_qword_r  = 'd0;
140
wire                        icache_read_req_in;
141
wire                        icache_read_ready;
142
reg                         servicing_dcache_cached_read_r = 'd0;
143
reg                         servicing_dcache_uncached_read_r = 'd0;
144
reg                         servicing_icache_r = 'd0;
145
wire                        extra_write;
146
reg                         extra_write_r = 'd0;
147
reg     [31:0]              extra_write_data_r;
148
reg     [31:0]              extra_write_address_r;
149
reg     [3:0]               extra_write_be_r;
150
 
151
assign read_ack                 = !o_wb_we && i_wb_ack;
152
 
153
assign dcache_cached_rready     = dcache_cached_rreq_r   && servicing_dcache_cached_read_r   && read_ack;
154
assign dcache_uncached_rready   = dcache_uncached_rreq_r && servicing_dcache_uncached_read_r && read_ack;
155
 
156
 
157
assign o_dcache_cached_ready    = dcache_cached_rready   || dcache_cached_wready;
158
assign o_dcache_uncached_ready  = dcache_uncached_rready || dcache_uncached_wready;
159
assign o_dcache_read_data       = i_wb_dat;
160
 
161
assign icache_read_ready        = servicing_icache_r && read_ack;
162
assign o_icache_ready           = icache_read_ready;
163
assign o_icache_read_data       = i_wb_dat;
164
 
165
 
166
assign dcache_cached_rreq_in    = i_dcache_cached_req   && !i_dcache_write;
167
assign dcache_cached_wreq_in    = i_dcache_cached_req   &&  i_dcache_write;
168
assign dcache_uncached_rreq_in  = i_dcache_uncached_req && !i_dcache_write;
169
assign dcache_uncached_wreq_in  = i_dcache_uncached_req &&  i_dcache_write;
170
assign icache_read_req_in       = i_icache_req && !o_icache_ready;
171
 
172
assign dcache_cached_rreq_c     = ( dcache_cached_rreq_in   || dcache_cached_rreq_r   ) && !(servicing_dcache_cached_read_r   && read_ack);
173
assign dcache_uncached_rreq_c   = ( dcache_uncached_rreq_in || dcache_uncached_rreq_r ) && !(servicing_dcache_uncached_read_r && read_ack);
174
 
175
assign dcache_read_qword_c      = ( i_dcache_qword       || dcache_read_qword_r ) && !(servicing_dcache_cached_read_r && read_ack);
176
 
177
assign icache_read_req_c        = ( icache_read_req_in   || icache_read_req_r   ) && !(servicing_icache_r && read_ack);
178
assign icache_read_qword_c      = ( i_icache_qword       || icache_read_qword_r ) && !(servicing_icache_r && read_ack);
179
assign icache_read_addr_c       = i_icache_req ?  i_icache_address : icache_read_addr_r;
180
 
181
assign dcache_req_c             = dcache_cached_rreq_c || dcache_cached_wreq_c || dcache_uncached_rreq_c || dcache_uncached_wreq_c;
182
assign write_req_c              = dcache_cached_wreq_c || dcache_uncached_wreq_c;
183
 
184
assign start_access             = !wait_write_ack && (dcache_req_c || icache_read_req_c);
185
 
186
// For writes the byte enable is always 4'hf
187
assign byte_enable              = write_req_c ? i_dcache_byte_enable : 4'hf;
188
 
189
 
190
assign dcache_cached_wready     = (dcache_cached_wreq_c && wishbone_st == WB_IDLE);
191
assign dcache_uncached_wready   = (dcache_uncached_wreq_c && wishbone_st == WB_IDLE);
192
assign dcache_cached_wreq_c     = dcache_cached_wreq_in   || dcache_cached_wreq_r;
193
assign dcache_uncached_wreq_c   = dcache_uncached_wreq_in || dcache_uncached_wreq_r;
194
 
195
 
196
// ======================================
197
// Register Accesses
198
// ======================================
199
 
200
assign extra_write =  wishbone_st == WB_IDLE && !i_wb_ack && ((dcache_cached_wreq_c && dcache_cached_wready)||
201
                                                              (dcache_uncached_wreq_c && dcache_uncached_wready));
202
 
203
always @( posedge i_clk )
204
    if ( wishbone_st == WB_WAIT_ACK && i_wb_ack && extra_write_r )
205
        o_wb_dat <= extra_write_data_r;
206
    else if ( start_access )
207
        o_wb_dat <= i_dcache_write_data;
208
 
209
 
210
 
211
always @( posedge i_clk )
212
    begin
213
    icache_read_req_r   <= icache_read_req_in  || icache_read_req_c;
214
    icache_read_qword_r <= i_icache_qword      || icache_read_qword_c;
215
    if ( i_icache_req ) icache_read_addr_r  <= i_icache_address;
216
 
217
    dcache_read_qword_r    <= i_dcache_qword      || dcache_read_qword_c;
218
    dcache_cached_wreq_r   <= dcache_cached_wreq_c   && (wishbone_st != WB_IDLE || (o_wb_stb && !i_wb_ack));
219
    dcache_uncached_wreq_r <= dcache_uncached_wreq_c && (wishbone_st != WB_IDLE || (o_wb_stb && !i_wb_ack));
220
 
221
 
222
    // A buffer to hold a second write while on eis in progress
223
    if ( extra_write )
224
        begin
225
        extra_write_data_r      <= i_dcache_write_data;
226
        extra_write_address_r   <= i_dcache_address;
227
        extra_write_be_r        <= i_dcache_byte_enable;
228
        end
229
 
230
 
231
    // The flag can be set during any state but only cleared during WB_IDLE or WB_WAIT_ACK
232
    if ( dcache_cached_rreq_r )
233
        begin
234
        if ( wishbone_st == WB_IDLE || wishbone_st == WB_WAIT_ACK )
235
            dcache_cached_rreq_r <= dcache_cached_rreq_c && !o_dcache_cached_ready;
236
        end
237
    else
238
        dcache_cached_rreq_r <= dcache_cached_rreq_c && !o_dcache_cached_ready;
239
    if ( dcache_uncached_rreq_r )
240
        begin
241
        if ( wishbone_st == WB_IDLE || wishbone_st == WB_WAIT_ACK )
242
            dcache_uncached_rreq_r <= dcache_uncached_rreq_c && !o_dcache_uncached_ready;
243
        end
244
    else
245
        dcache_uncached_rreq_r <= dcache_uncached_rreq_c && !o_dcache_uncached_ready;
246
    end
247
 
248
assign wait_write_ack = o_wb_stb && o_wb_we && !i_wb_ack;
249
 
250
 
251
always @( posedge i_clk )
252
    case ( wishbone_st )
253
        WB_IDLE :
254
            begin
255
            extra_write_r <= extra_write;
256
 
257
            if ( start_access )
258
                begin
259
                o_wb_stb            <= 1'd1;
260
                o_wb_cyc            <= 1'd1;
261
                o_wb_sel            <= byte_enable;
262
                end
263
            else if ( !wait_write_ack )
264
                begin
265
                o_wb_stb            <= 1'd0;
266
 
267
                // Hold cyc high after an exclusive access
268
                // to hold ownership of the wishbone bus
269
                o_wb_cyc            <= exclusive_access;
270
                end
271
 
272
            if ( wait_write_ack )
273
                begin
274
                // still waiting for last (write) access to complete
275
                wishbone_st                      <= WB_WAIT_ACK;
276
                servicing_dcache_cached_read_r   <= dcache_cached_rreq_c;
277
                servicing_dcache_uncached_read_r <= dcache_uncached_rreq_c;
278
                end
279
            // dcache accesses have priority over icache     
280
            else if ( dcache_cached_rreq_c || dcache_uncached_rreq_c )
281
                begin
282
                if ( dcache_cached_rreq_c )
283
                    servicing_dcache_cached_read_r <= 1'd1;
284
                else if ( dcache_uncached_rreq_c )
285
                    servicing_dcache_uncached_read_r <= 1'd1;
286
 
287
                if ( dcache_read_qword_c )
288
                    wishbone_st         <= WB_BURST1;
289
                else
290
                    wishbone_st         <= WB_WAIT_ACK;
291
                exclusive_access    <= i_exclusive;
292
                end
293
           // The core does not currently issue exclusive write requests
294
           // but there's no reason why this might not be added some
295
           // time in the future so allow for it here
296
            else if ( write_req_c )
297
                begin
298
                exclusive_access            <= i_exclusive;
299
                end
300
            // do a burst of 4 read to fill a cache line                   
301
            else if ( icache_read_req_c && icache_read_qword_c )
302
                begin
303
                wishbone_st                 <= WB_BURST1;
304
                exclusive_access            <= 1'd0;
305
                servicing_icache_r          <= 1'd1;
306
                end
307
            // single word read request from fetch stage                   
308
            else if ( icache_read_req_c )
309
                begin
310
                wishbone_st                 <= WB_WAIT_ACK;
311
                exclusive_access            <= 1'd0;
312
                servicing_icache_r          <= 1'd1;
313
                end
314
 
315
 
316
            if ( start_access )
317
                begin
318
                if ( dcache_req_c )
319
                    begin
320
                    o_wb_we              <= write_req_c;
321
                    // only update these on new wb access to make debug easier
322
                    o_wb_adr[31:2]       <= i_dcache_address[31:2];
323
                    o_wb_adr[1:0]        <= byte_enable == 4'b0001 ? 2'd0 :
324
                                            byte_enable == 4'b0010 ? 2'd1 :
325
                                            byte_enable == 4'b0100 ? 2'd2 :
326
                                            byte_enable == 4'b1000 ? 2'd3 :
327
 
328
                                            byte_enable == 4'b0011 ? 2'd0 :
329
                                            byte_enable == 4'b1100 ? 2'd2 :
330
 
331
                                                                     2'd0 ;
332
                    end
333
                else
334
                    begin
335
                    o_wb_we              <= 1'd0;
336
                    o_wb_adr[31:0]       <= {icache_read_addr_c[31:2], 2'd0};
337
                    end
338
                end
339
            end
340
 
341
 
342
        // Read burst, wait for first ack
343
        WB_BURST1:
344
            if ( i_wb_ack )
345
                begin
346
                // burst of 4 that wraps
347
                o_wb_adr[3:2]   <= o_wb_adr[3:2] + 1'd1;
348
                wishbone_st     <= WB_BURST2;
349
                end
350
 
351
 
352
        // Read burst, wait for second ack
353
        WB_BURST2:
354
            if ( i_wb_ack )
355
                begin
356
                // burst of 4 that wraps
357
                o_wb_adr[3:2]   <= o_wb_adr[3:2] + 1'd1;
358
                wishbone_st     <= WB_BURST3;
359
                end
360
 
361
 
362
        // Read burst, wait for third ack
363
        WB_BURST3:
364
            if ( i_wb_ack )
365
                begin
366
                // burst of 4 that wraps
367
                o_wb_adr[3:2]   <= o_wb_adr[3:2] + 1'd1;
368
                wishbone_st     <= WB_WAIT_ACK;
369
                end
370
 
371
 
372
        // Wait for the wishbone ack to be asserted
373
        WB_WAIT_ACK:
374
            if ( i_wb_ack )
375
                // Another write that was acked and needs to be sent before returning to IDLE ?
376
                if ( extra_write_r )
377
                    begin
378
                    extra_write_r                       <= 'd0;
379
                    o_wb_stb                            <= 1'd1;
380
                    o_wb_cyc                            <= exclusive_access;
381
                    o_wb_sel                            <= extra_write_be_r;
382
                    o_wb_we                             <= 1'd1;
383
                    o_wb_adr[31:0]                      <= extra_write_address_r;
384
                    end
385
                else
386
                    begin
387
                    wishbone_st                         <= WB_IDLE;
388
                    o_wb_stb                            <= 1'd0;
389
                    o_wb_cyc                            <= exclusive_access;
390
                    o_wb_we                             <= 1'd0;
391
                    servicing_dcache_cached_read_r      <= 1'd0;
392
                    servicing_dcache_uncached_read_r    <= 1'd0;
393
                    servicing_icache_r                  <= 1'd0;
394
                    end
395
 
396
 
397
    endcase
398
 
399
// ========================================================
400
// Debug Wishbone bus - not synthesizable
401
// ========================================================
402
//synopsys translate_off
403
wire    [(14*8)-1:0]   xWB_STATE;
404
 
405
 
406
assign xWB_STATE  = wishbone_st == WB_IDLE       ? "WB_IDLE"       :
407
                    wishbone_st == WB_BURST1     ? "WB_BURST1"     :
408
                    wishbone_st == WB_BURST2     ? "WB_BURST2"     :
409
                    wishbone_st == WB_BURST3     ? "WB_BURST3"     :
410
                    wishbone_st == WB_WAIT_ACK   ? "WB_WAIT_ACK"   :
411
                                                   "UNKNOWN"       ;
412
 
413
//synopsys translate_on
414
 
415
endmodule
416
 

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