OpenCores
URL https://opencores.org/ocsvn/amber/amber/trunk

Subversion Repositories amber

[/] [amber/] [trunk/] [hw/] [vlog/] [ethmac/] [eth_maccontrol.v] - Blame information for rev 2

Details | Compare with Previous | View Log

Line No. Rev Author Line
1 2 csantifort
//////////////////////////////////////////////////////////////////////
2
////                                                              ////
3
////  eth_maccontrol.v                                            ////
4
////                                                              ////
5
////  This file is part of the Ethernet IP core project           ////
6
////  http://www.opencores.org/projects/ethmac/                   ////
7
////                                                              ////
8
////  Author(s):                                                  ////
9
////      - Igor Mohor (igorM@opencores.org)                      ////
10
////                                                              ////
11
////  All additional information is avaliable in the Readme.txt   ////
12
////  file.                                                       ////
13
////                                                              ////
14
//////////////////////////////////////////////////////////////////////
15
////                                                              ////
16
//// Copyright (C) 2001 Authors                                   ////
17
////                                                              ////
18
//// This source file may be used and distributed without         ////
19
//// restriction provided that this copyright statement is not    ////
20
//// removed from the file and that any derivative work contains  ////
21
//// the original copyright notice and the associated disclaimer. ////
22
////                                                              ////
23
//// This source file is free software; you can redistribute it   ////
24
//// and/or modify it under the terms of the GNU Lesser General   ////
25
//// Public License as published by the Free Software Foundation; ////
26
//// either version 2.1 of the License, or (at your option) any   ////
27
//// later version.                                               ////
28
////                                                              ////
29
//// This source is distributed in the hope that it will be       ////
30
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
31
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
32
//// PURPOSE.  See the GNU Lesser General Public License for more ////
33
//// details.                                                     ////
34
////                                                              ////
35
//// You should have received a copy of the GNU Lesser General    ////
36
//// Public License along with this source; if not, download it   ////
37
//// from http://www.opencores.org/lgpl.shtml                     ////
38
////                                                              ////
39
//////////////////////////////////////////////////////////////////////
40
//
41
// CVS Revision History
42
//
43
// $Log: not supported by cvs2svn $
44
// Revision 1.6  2002/11/22 01:57:06  mohor
45
// Rx Flow control fixed. CF flag added to the RX buffer descriptor. RxAbort
46
// synchronized.
47
//
48
// Revision 1.5  2002/11/21 00:14:39  mohor
49
// TxDone and TxAbort changed so they're not propagated to the wishbone
50
// module when control frame is transmitted.
51
//
52
// Revision 1.4  2002/11/19 17:37:32  mohor
53
// When control frame (PAUSE) was sent, status was written in the
54
// eth_wishbone module and both TXB and TXC interrupts were set. Fixed.
55
// Only TXC interrupt is set.
56
//
57
// Revision 1.3  2002/01/23 10:28:16  mohor
58
// Link in the header changed.
59
//
60
// Revision 1.2  2001/10/19 08:43:51  mohor
61
// eth_timescale.v changed to timescale.v This is done because of the
62
// simulation of the few cores in a one joined project.
63
//
64
// Revision 1.1  2001/08/06 14:44:29  mohor
65
// A define FPGA added to select between Artisan RAM (for ASIC) and Block Ram (For Virtex).
66
// Include files fixed to contain no path.
67
// File names and module names changed ta have a eth_ prologue in the name.
68
// File eth_timescale.v is used to define timescale
69
// All pin names on the top module are changed to contain _I, _O or _OE at the end.
70
// Bidirectional signal MDIO is changed to three signals (Mdc_O, Mdi_I, Mdo_O
71
// and Mdo_OE. The bidirectional signal must be created on the top level. This
72
// is done due to the ASIC tools.
73
//
74
// Revision 1.1  2001/07/30 21:23:42  mohor
75
// Directory structure changed. Files checked and joind together.
76
//
77
// Revision 1.1  2001/07/03 12:51:54  mohor
78
// Initial release of the MAC Control module.
79
//
80
//
81
//
82
//
83
 
84
 
85
`include "timescale.v"
86
 
87
 
88
module eth_maccontrol (MTxClk, MRxClk, TxReset, RxReset, TPauseRq, TxDataIn, TxStartFrmIn, TxUsedDataIn,
89
                       TxEndFrmIn, TxDoneIn, TxAbortIn, RxData, RxValid, RxStartFrm, RxEndFrm, ReceiveEnd,
90
                       ReceivedPacketGood, ReceivedLengthOK, TxFlow, RxFlow, DlyCrcEn, TxPauseTV,
91
                       MAC, PadIn, PadOut, CrcEnIn, CrcEnOut, TxDataOut, TxStartFrmOut, TxEndFrmOut,
92
                       TxDoneOut, TxAbortOut, TxUsedDataOut, WillSendControlFrame, TxCtrlEndFrm,
93
                       ReceivedPauseFrm, ControlFrmAddressOK, SetPauseTimer, r_PassAll, RxStatusWriteLatched_sync2
94
                      );
95
 
96
 
97
parameter   Tp = 1;
98
 
99
 
100
input         MTxClk;                   // Transmit clock (from PHY)
101
input         MRxClk;                   // Receive clock (from PHY)
102
input         TxReset;                  // Transmit reset
103
input         RxReset;                  // Receive reset
104
input         TPauseRq;                 // Transmit control frame (from host)
105
input   [7:0] TxDataIn;                 // Transmit packet data byte (from host)
106
input         TxStartFrmIn;             // Transmit packet start frame input (from host)
107
input         TxUsedDataIn;             // Transmit packet used data (from TxEthMAC)
108
input         TxEndFrmIn;               // Transmit packet end frame input (from host)
109
input         TxDoneIn;                 // Transmit packet done (from TxEthMAC)
110
input         TxAbortIn;                // Transmit packet abort (input from TxEthMAC)
111
input         PadIn;                    // Padding (input from registers)
112
input         CrcEnIn;                  // Crc append (input from registers)
113
input   [7:0] RxData;                   // Receive Packet Data (from RxEthMAC)
114
input         RxValid;                  // Received a valid packet
115
input         RxStartFrm;               // Receive packet start frame (input from RxEthMAC)
116
input         RxEndFrm;                 // Receive packet end frame (input from RxEthMAC)
117
input         ReceiveEnd;               // End of receiving of the current packet (input from RxEthMAC)
118
input         ReceivedPacketGood;       // Received packet is good
119
input         ReceivedLengthOK;         // Length of the received packet is OK
120
input         TxFlow;                   // Tx flow control (from registers)
121
input         RxFlow;                   // Rx flow control (from registers)
122
input         DlyCrcEn;                 // Delayed CRC enabled (from registers)
123
input  [15:0] TxPauseTV;                // Transmit Pause Timer Value (from registers)
124
input  [47:0] MAC;                      // MAC address (from registers)
125
input         RxStatusWriteLatched_sync2;
126
input         r_PassAll;
127
 
128
output  [7:0] TxDataOut;                // Transmit Packet Data (to TxEthMAC)
129
output        TxStartFrmOut;            // Transmit packet start frame (output to TxEthMAC)
130
output        TxEndFrmOut;              // Transmit packet end frame (output to TxEthMAC)
131
output        TxDoneOut;                // Transmit packet done (to host)
132
output        TxAbortOut;               // Transmit packet aborted (to host)
133
output        TxUsedDataOut;            // Transmit packet used data (to host)
134
output        PadOut;                   // Padding (output to TxEthMAC)
135
output        CrcEnOut;                 // Crc append (output to TxEthMAC)
136
output        WillSendControlFrame;
137
output        TxCtrlEndFrm;
138
output        ReceivedPauseFrm;
139
output        ControlFrmAddressOK;
140
output        SetPauseTimer;
141
 
142
reg           TxUsedDataOutDetected;
143
reg           TxAbortInLatched;
144
reg           TxDoneInLatched;
145
reg           MuxedDone;
146
reg           MuxedAbort;
147
 
148
wire          Pause;
149
wire          TxCtrlStartFrm;
150
wire    [7:0] ControlData;
151
wire          CtrlMux;
152
wire          SendingCtrlFrm;           // Sending Control Frame (enables padding and CRC)
153
wire          BlockTxDone;
154
 
155
 
156
// Signal TxUsedDataOut was detected (a transfer is already in progress)
157
always @ (posedge MTxClk or posedge TxReset)
158
begin
159
  if(TxReset)
160
    TxUsedDataOutDetected <= #Tp 1'b0;
161
  else
162
  if(TxDoneIn | TxAbortIn)
163
    TxUsedDataOutDetected <= #Tp 1'b0;
164
  else
165
  if(TxUsedDataOut)
166
    TxUsedDataOutDetected <= #Tp 1'b1;
167
end
168
 
169
 
170
// Latching variables
171
always @ (posedge MTxClk or posedge TxReset)
172
begin
173
  if(TxReset)
174
    begin
175
      TxAbortInLatched <= #Tp 1'b0;
176
      TxDoneInLatched  <= #Tp 1'b0;
177
    end
178
  else
179
    begin
180
      TxAbortInLatched <= #Tp TxAbortIn;
181
      TxDoneInLatched  <= #Tp TxDoneIn;
182
    end
183
end
184
 
185
 
186
 
187
// Generating muxed abort signal
188
always @ (posedge MTxClk or posedge TxReset)
189
begin
190
  if(TxReset)
191
    MuxedAbort <= #Tp 1'b0;
192
  else
193
  if(TxStartFrmIn)
194
    MuxedAbort <= #Tp 1'b0;
195
  else
196
  if(TxAbortIn & ~TxAbortInLatched & TxUsedDataOutDetected)
197
    MuxedAbort <= #Tp 1'b1;
198
end
199
 
200
 
201
// Generating muxed done signal
202
always @ (posedge MTxClk or posedge TxReset)
203
begin
204
  if(TxReset)
205
    MuxedDone <= #Tp 1'b0;
206
  else
207
  if(TxStartFrmIn)
208
    MuxedDone <= #Tp 1'b0;
209
  else
210
  if(TxDoneIn & (~TxDoneInLatched) & TxUsedDataOutDetected)
211
    MuxedDone <= #Tp 1'b1;
212
end
213
 
214
 
215
// TxDoneOut
216
assign TxDoneOut  = CtrlMux? ((~TxStartFrmIn) & (~BlockTxDone) & MuxedDone) :
217
                             ((~TxStartFrmIn) & (~BlockTxDone) & TxDoneIn);
218
 
219
// TxAbortOut
220
assign TxAbortOut  = CtrlMux? ((~TxStartFrmIn) & (~BlockTxDone) & MuxedAbort) :
221
                              ((~TxStartFrmIn) & (~BlockTxDone) & TxAbortIn);
222
 
223
// TxUsedDataOut
224
assign TxUsedDataOut  = ~CtrlMux & TxUsedDataIn;
225
 
226
// TxStartFrmOut
227
assign TxStartFrmOut = CtrlMux? TxCtrlStartFrm : (TxStartFrmIn & ~Pause);
228
 
229
 
230
// TxEndFrmOut
231
assign TxEndFrmOut = CtrlMux? TxCtrlEndFrm : TxEndFrmIn;
232
 
233
 
234
// TxDataOut[7:0]
235
assign TxDataOut[7:0] = CtrlMux? ControlData[7:0] : TxDataIn[7:0];
236
 
237
 
238
// PadOut
239
assign PadOut = PadIn | SendingCtrlFrm;
240
 
241
 
242
// CrcEnOut
243
assign CrcEnOut = CrcEnIn | SendingCtrlFrm;
244
 
245
 
246
 
247
// Connecting receivecontrol module
248
eth_receivecontrol receivecontrol1
249
(
250
 .MTxClk(MTxClk), .MRxClk(MRxClk), .TxReset(TxReset), .RxReset(RxReset), .RxData(RxData),
251
 .RxValid(RxValid), .RxStartFrm(RxStartFrm), .RxEndFrm(RxEndFrm), .RxFlow(RxFlow),
252
 .ReceiveEnd(ReceiveEnd), .MAC(MAC), .DlyCrcEn(DlyCrcEn), .TxDoneIn(TxDoneIn),
253
 .TxAbortIn(TxAbortIn), .TxStartFrmOut(TxStartFrmOut), .ReceivedLengthOK(ReceivedLengthOK),
254
 .ReceivedPacketGood(ReceivedPacketGood), .TxUsedDataOutDetected(TxUsedDataOutDetected),
255
 .Pause(Pause), .ReceivedPauseFrm(ReceivedPauseFrm), .AddressOK(ControlFrmAddressOK),
256
 .r_PassAll(r_PassAll), .RxStatusWriteLatched_sync2(RxStatusWriteLatched_sync2), .SetPauseTimer(SetPauseTimer)
257
);
258
 
259
 
260
eth_transmitcontrol transmitcontrol1
261
(
262
 .MTxClk(MTxClk), .TxReset(TxReset), .TxUsedDataIn(TxUsedDataIn), .TxUsedDataOut(TxUsedDataOut),
263
 .TxDoneIn(TxDoneIn), .TxAbortIn(TxAbortIn), .TxStartFrmIn(TxStartFrmIn), .TPauseRq(TPauseRq),
264
 .TxUsedDataOutDetected(TxUsedDataOutDetected), .TxFlow(TxFlow), .DlyCrcEn(DlyCrcEn), .TxPauseTV(TxPauseTV),
265
 .MAC(MAC), .TxCtrlStartFrm(TxCtrlStartFrm), .TxCtrlEndFrm(TxCtrlEndFrm), .SendingCtrlFrm(SendingCtrlFrm),
266
 .CtrlMux(CtrlMux), .ControlData(ControlData), .WillSendControlFrame(WillSendControlFrame), .BlockTxDone(BlockTxDone)
267
);
268
 
269
 
270
 
271
endmodule

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.