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csantifort |
//////////////////////////////////////////////////////////////////
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// //
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// Wrapper for Xilinx Spartan-6 RAM Block //
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// //
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// This file is part of the Amber project //
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// http://www.opencores.org/project,amber //
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// //
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// Description //
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// 2048 words x 32 bits with a per byte write enable //
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// //
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// Author(s): //
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// - Conor Santifort, csantifort.amber@gmail.com //
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// //
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//////////////////////////////////////////////////////////////////
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// //
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// Copyright (C) 2010 Authors and OPENCORES.ORG //
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// //
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// This source file may be used and distributed without //
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// restriction provided that this copyright statement is not //
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// removed from the file and that any derivative work contains //
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// the original copyright notice and the associated disclaimer. //
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// //
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// This source file is free software; you can redistribute it //
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// and/or modify it under the terms of the GNU Lesser General //
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// Public License as published by the Free Software Foundation; //
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// either version 2.1 of the License, or (at your option) any //
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// later version. //
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// //
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// This source is distributed in the hope that it will be //
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// useful, but WITHOUT ANY WARRANTY; without even the implied //
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// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //
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// PURPOSE. See the GNU Lesser General Public License for more //
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// details. //
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// //
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// You should have received a copy of the GNU Lesser General //
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// Public License along with this source; if not, download it //
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// from http://www.opencores.org/lgpl.shtml //
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// //
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//////////////////////////////////////////////////////////////////
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module xs6_sram_2048x32_byte_en
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#(
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parameter SRAM0_INIT_0 = 256'h0,
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parameter SRAM0_INIT_1 = 256'h0,
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parameter SRAM0_INIT_2 = 256'h0,
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parameter SRAM0_INIT_3 = 256'h0,
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parameter SRAM0_INIT_4 = 256'h0,
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parameter SRAM0_INIT_5 = 256'h0,
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parameter SRAM0_INIT_6 = 256'h0,
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parameter SRAM0_INIT_7 = 256'h0,
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parameter SRAM0_INIT_8 = 256'h0,
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parameter SRAM0_INIT_9 = 256'h0,
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parameter SRAM0_INIT_10 = 256'h0,
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parameter SRAM0_INIT_11 = 256'h0,
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parameter SRAM0_INIT_12 = 256'h0,
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parameter SRAM0_INIT_13 = 256'h0,
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parameter SRAM0_INIT_14 = 256'h0,
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parameter SRAM0_INIT_15 = 256'h0,
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parameter SRAM0_INIT_16 = 256'h0,
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parameter SRAM0_INIT_17 = 256'h0,
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parameter SRAM0_INIT_18 = 256'h0,
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parameter SRAM0_INIT_19 = 256'h0,
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parameter SRAM0_INIT_20 = 256'h0,
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parameter SRAM0_INIT_21 = 256'h0,
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parameter SRAM0_INIT_22 = 256'h0,
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parameter SRAM0_INIT_23 = 256'h0,
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parameter SRAM0_INIT_24 = 256'h0,
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parameter SRAM0_INIT_25 = 256'h0,
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parameter SRAM0_INIT_26 = 256'h0,
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parameter SRAM0_INIT_27 = 256'h0,
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parameter SRAM0_INIT_28 = 256'h0,
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parameter SRAM0_INIT_29 = 256'h0,
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parameter SRAM0_INIT_30 = 256'h0,
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parameter SRAM0_INIT_31 = 256'h0,
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parameter SRAM0_INIT_32 = 256'h0,
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parameter SRAM0_INIT_33 = 256'h0,
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parameter SRAM0_INIT_34 = 256'h0,
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parameter SRAM0_INIT_35 = 256'h0,
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parameter SRAM0_INIT_36 = 256'h0,
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parameter SRAM0_INIT_37 = 256'h0,
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parameter SRAM0_INIT_38 = 256'h0,
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parameter SRAM0_INIT_39 = 256'h0,
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parameter SRAM0_INIT_40 = 256'h0,
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parameter SRAM0_INIT_41 = 256'h0,
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parameter SRAM0_INIT_42 = 256'h0,
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parameter SRAM0_INIT_43 = 256'h0,
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parameter SRAM0_INIT_44 = 256'h0,
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parameter SRAM0_INIT_45 = 256'h0,
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parameter SRAM0_INIT_46 = 256'h0,
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parameter SRAM0_INIT_47 = 256'h0,
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parameter SRAM0_INIT_48 = 256'h0,
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parameter SRAM0_INIT_49 = 256'h0,
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parameter SRAM0_INIT_50 = 256'h0,
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parameter SRAM0_INIT_51 = 256'h0,
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parameter SRAM0_INIT_52 = 256'h0,
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parameter SRAM0_INIT_53 = 256'h0,
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parameter SRAM0_INIT_54 = 256'h0,
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parameter SRAM0_INIT_55 = 256'h0,
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parameter SRAM0_INIT_56 = 256'h0,
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parameter SRAM0_INIT_57 = 256'h0,
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parameter SRAM0_INIT_58 = 256'h0,
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parameter SRAM0_INIT_59 = 256'h0,
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parameter SRAM0_INIT_60 = 256'h0,
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parameter SRAM0_INIT_61 = 256'h0,
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parameter SRAM0_INIT_62 = 256'h0,
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parameter SRAM0_INIT_63 = 256'h0,
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parameter SRAM1_INIT_0 = 256'h0,
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parameter SRAM1_INIT_1 = 256'h0,
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parameter SRAM1_INIT_2 = 256'h0,
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parameter SRAM1_INIT_3 = 256'h0,
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parameter SRAM1_INIT_4 = 256'h0,
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parameter SRAM1_INIT_5 = 256'h0,
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parameter SRAM1_INIT_6 = 256'h0,
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parameter SRAM1_INIT_7 = 256'h0,
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parameter SRAM1_INIT_8 = 256'h0,
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parameter SRAM1_INIT_9 = 256'h0,
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parameter SRAM1_INIT_10 = 256'h0,
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parameter SRAM1_INIT_11 = 256'h0,
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parameter SRAM1_INIT_12 = 256'h0,
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parameter SRAM1_INIT_13 = 256'h0,
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parameter SRAM1_INIT_14 = 256'h0,
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parameter SRAM1_INIT_15 = 256'h0,
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parameter SRAM1_INIT_16 = 256'h0,
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parameter SRAM1_INIT_17 = 256'h0,
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parameter SRAM1_INIT_18 = 256'h0,
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parameter SRAM1_INIT_19 = 256'h0,
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parameter SRAM1_INIT_20 = 256'h0,
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parameter SRAM1_INIT_21 = 256'h0,
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parameter SRAM1_INIT_22 = 256'h0,
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parameter SRAM1_INIT_23 = 256'h0,
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parameter SRAM1_INIT_24 = 256'h0,
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parameter SRAM1_INIT_25 = 256'h0,
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parameter SRAM1_INIT_26 = 256'h0,
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parameter SRAM1_INIT_27 = 256'h0,
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parameter SRAM1_INIT_28 = 256'h0,
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parameter SRAM1_INIT_29 = 256'h0,
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parameter SRAM1_INIT_30 = 256'h0,
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parameter SRAM1_INIT_31 = 256'h0,
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parameter SRAM1_INIT_32 = 256'h0,
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parameter SRAM1_INIT_33 = 256'h0,
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parameter SRAM1_INIT_34 = 256'h0,
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parameter SRAM1_INIT_35 = 256'h0,
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parameter SRAM1_INIT_36 = 256'h0,
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parameter SRAM1_INIT_37 = 256'h0,
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parameter SRAM1_INIT_38 = 256'h0,
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parameter SRAM1_INIT_39 = 256'h0,
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parameter SRAM1_INIT_40 = 256'h0,
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parameter SRAM1_INIT_41 = 256'h0,
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parameter SRAM1_INIT_42 = 256'h0,
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parameter SRAM1_INIT_43 = 256'h0,
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parameter SRAM1_INIT_44 = 256'h0,
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parameter SRAM1_INIT_45 = 256'h0,
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parameter SRAM1_INIT_46 = 256'h0,
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parameter SRAM1_INIT_47 = 256'h0,
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parameter SRAM1_INIT_48 = 256'h0,
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parameter SRAM1_INIT_49 = 256'h0,
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parameter SRAM1_INIT_50 = 256'h0,
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parameter SRAM1_INIT_51 = 256'h0,
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parameter SRAM1_INIT_52 = 256'h0,
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parameter SRAM1_INIT_53 = 256'h0,
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parameter SRAM1_INIT_54 = 256'h0,
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parameter SRAM1_INIT_55 = 256'h0,
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parameter SRAM1_INIT_56 = 256'h0,
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parameter SRAM1_INIT_57 = 256'h0,
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parameter SRAM1_INIT_58 = 256'h0,
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parameter SRAM1_INIT_59 = 256'h0,
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parameter SRAM1_INIT_60 = 256'h0,
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parameter SRAM1_INIT_61 = 256'h0,
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parameter SRAM1_INIT_62 = 256'h0,
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parameter SRAM1_INIT_63 = 256'h0,
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parameter SRAM2_INIT_0 = 256'h0,
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parameter SRAM2_INIT_1 = 256'h0,
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parameter SRAM2_INIT_2 = 256'h0,
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parameter SRAM2_INIT_3 = 256'h0,
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parameter SRAM2_INIT_4 = 256'h0,
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parameter SRAM2_INIT_5 = 256'h0,
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parameter SRAM2_INIT_6 = 256'h0,
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parameter SRAM2_INIT_7 = 256'h0,
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parameter SRAM2_INIT_8 = 256'h0,
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parameter SRAM2_INIT_9 = 256'h0,
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parameter SRAM2_INIT_10 = 256'h0,
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parameter SRAM2_INIT_11 = 256'h0,
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parameter SRAM2_INIT_12 = 256'h0,
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parameter SRAM2_INIT_13 = 256'h0,
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parameter SRAM2_INIT_14 = 256'h0,
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parameter SRAM2_INIT_15 = 256'h0,
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parameter SRAM2_INIT_16 = 256'h0,
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parameter SRAM2_INIT_17 = 256'h0,
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parameter SRAM2_INIT_18 = 256'h0,
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parameter SRAM2_INIT_19 = 256'h0,
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parameter SRAM2_INIT_20 = 256'h0,
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parameter SRAM2_INIT_21 = 256'h0,
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parameter SRAM2_INIT_22 = 256'h0,
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parameter SRAM2_INIT_23 = 256'h0,
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parameter SRAM2_INIT_24 = 256'h0,
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parameter SRAM2_INIT_25 = 256'h0,
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parameter SRAM2_INIT_26 = 256'h0,
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parameter SRAM2_INIT_27 = 256'h0,
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parameter SRAM2_INIT_28 = 256'h0,
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parameter SRAM2_INIT_29 = 256'h0,
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parameter SRAM2_INIT_30 = 256'h0,
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| 208 |
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parameter SRAM2_INIT_31 = 256'h0,
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parameter SRAM2_INIT_32 = 256'h0,
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parameter SRAM2_INIT_33 = 256'h0,
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parameter SRAM2_INIT_34 = 256'h0,
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| 212 |
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parameter SRAM2_INIT_35 = 256'h0,
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| 213 |
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parameter SRAM2_INIT_36 = 256'h0,
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| 214 |
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parameter SRAM2_INIT_37 = 256'h0,
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| 215 |
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parameter SRAM2_INIT_38 = 256'h0,
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| 216 |
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parameter SRAM2_INIT_39 = 256'h0,
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| 217 |
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parameter SRAM2_INIT_40 = 256'h0,
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| 218 |
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parameter SRAM2_INIT_41 = 256'h0,
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| 219 |
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parameter SRAM2_INIT_42 = 256'h0,
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| 220 |
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parameter SRAM2_INIT_43 = 256'h0,
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| 221 |
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parameter SRAM2_INIT_44 = 256'h0,
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| 222 |
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parameter SRAM2_INIT_45 = 256'h0,
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| 223 |
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parameter SRAM2_INIT_46 = 256'h0,
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| 224 |
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parameter SRAM2_INIT_47 = 256'h0,
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| 225 |
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parameter SRAM2_INIT_48 = 256'h0,
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| 226 |
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parameter SRAM2_INIT_49 = 256'h0,
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| 227 |
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parameter SRAM2_INIT_50 = 256'h0,
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| 228 |
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parameter SRAM2_INIT_51 = 256'h0,
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| 229 |
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parameter SRAM2_INIT_52 = 256'h0,
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| 230 |
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parameter SRAM2_INIT_53 = 256'h0,
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| 231 |
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parameter SRAM2_INIT_54 = 256'h0,
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| 232 |
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parameter SRAM2_INIT_55 = 256'h0,
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| 233 |
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parameter SRAM2_INIT_56 = 256'h0,
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| 234 |
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parameter SRAM2_INIT_57 = 256'h0,
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| 235 |
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parameter SRAM2_INIT_58 = 256'h0,
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| 236 |
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parameter SRAM2_INIT_59 = 256'h0,
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| 237 |
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parameter SRAM2_INIT_60 = 256'h0,
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| 238 |
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parameter SRAM2_INIT_61 = 256'h0,
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| 239 |
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parameter SRAM2_INIT_62 = 256'h0,
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| 240 |
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parameter SRAM2_INIT_63 = 256'h0,
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| 241 |
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| 242 |
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parameter SRAM3_INIT_0 = 256'h0,
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| 243 |
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parameter SRAM3_INIT_1 = 256'h0,
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| 244 |
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parameter SRAM3_INIT_2 = 256'h0,
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| 245 |
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parameter SRAM3_INIT_3 = 256'h0,
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| 246 |
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parameter SRAM3_INIT_4 = 256'h0,
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| 247 |
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parameter SRAM3_INIT_5 = 256'h0,
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| 248 |
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parameter SRAM3_INIT_6 = 256'h0,
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| 249 |
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parameter SRAM3_INIT_7 = 256'h0,
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| 250 |
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parameter SRAM3_INIT_8 = 256'h0,
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| 251 |
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parameter SRAM3_INIT_9 = 256'h0,
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| 252 |
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parameter SRAM3_INIT_10 = 256'h0,
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| 253 |
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parameter SRAM3_INIT_11 = 256'h0,
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| 254 |
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parameter SRAM3_INIT_12 = 256'h0,
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| 255 |
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parameter SRAM3_INIT_13 = 256'h0,
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| 256 |
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parameter SRAM3_INIT_14 = 256'h0,
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| 257 |
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parameter SRAM3_INIT_15 = 256'h0,
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| 258 |
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parameter SRAM3_INIT_16 = 256'h0,
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| 259 |
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parameter SRAM3_INIT_17 = 256'h0,
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| 260 |
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parameter SRAM3_INIT_18 = 256'h0,
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| 261 |
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parameter SRAM3_INIT_19 = 256'h0,
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| 262 |
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parameter SRAM3_INIT_20 = 256'h0,
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| 263 |
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parameter SRAM3_INIT_21 = 256'h0,
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| 264 |
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parameter SRAM3_INIT_22 = 256'h0,
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| 265 |
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parameter SRAM3_INIT_23 = 256'h0,
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| 266 |
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parameter SRAM3_INIT_24 = 256'h0,
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| 267 |
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parameter SRAM3_INIT_25 = 256'h0,
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| 268 |
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parameter SRAM3_INIT_26 = 256'h0,
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| 269 |
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parameter SRAM3_INIT_27 = 256'h0,
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| 270 |
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parameter SRAM3_INIT_28 = 256'h0,
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| 271 |
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parameter SRAM3_INIT_29 = 256'h0,
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| 272 |
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parameter SRAM3_INIT_30 = 256'h0,
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| 273 |
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parameter SRAM3_INIT_31 = 256'h0,
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| 274 |
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parameter SRAM3_INIT_32 = 256'h0,
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| 275 |
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parameter SRAM3_INIT_33 = 256'h0,
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| 276 |
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parameter SRAM3_INIT_34 = 256'h0,
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| 277 |
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parameter SRAM3_INIT_35 = 256'h0,
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| 278 |
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parameter SRAM3_INIT_36 = 256'h0,
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| 279 |
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parameter SRAM3_INIT_37 = 256'h0,
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| 280 |
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parameter SRAM3_INIT_38 = 256'h0,
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| 281 |
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parameter SRAM3_INIT_39 = 256'h0,
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| 282 |
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parameter SRAM3_INIT_40 = 256'h0,
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| 283 |
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parameter SRAM3_INIT_41 = 256'h0,
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| 284 |
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parameter SRAM3_INIT_42 = 256'h0,
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| 285 |
|
|
parameter SRAM3_INIT_43 = 256'h0,
|
| 286 |
|
|
parameter SRAM3_INIT_44 = 256'h0,
|
| 287 |
|
|
parameter SRAM3_INIT_45 = 256'h0,
|
| 288 |
|
|
parameter SRAM3_INIT_46 = 256'h0,
|
| 289 |
|
|
parameter SRAM3_INIT_47 = 256'h0,
|
| 290 |
|
|
parameter SRAM3_INIT_48 = 256'h0,
|
| 291 |
|
|
parameter SRAM3_INIT_49 = 256'h0,
|
| 292 |
|
|
parameter SRAM3_INIT_50 = 256'h0,
|
| 293 |
|
|
parameter SRAM3_INIT_51 = 256'h0,
|
| 294 |
|
|
parameter SRAM3_INIT_52 = 256'h0,
|
| 295 |
|
|
parameter SRAM3_INIT_53 = 256'h0,
|
| 296 |
|
|
parameter SRAM3_INIT_54 = 256'h0,
|
| 297 |
|
|
parameter SRAM3_INIT_55 = 256'h0,
|
| 298 |
|
|
parameter SRAM3_INIT_56 = 256'h0,
|
| 299 |
|
|
parameter SRAM3_INIT_57 = 256'h0,
|
| 300 |
|
|
parameter SRAM3_INIT_58 = 256'h0,
|
| 301 |
|
|
parameter SRAM3_INIT_59 = 256'h0,
|
| 302 |
|
|
parameter SRAM3_INIT_60 = 256'h0,
|
| 303 |
|
|
parameter SRAM3_INIT_61 = 256'h0,
|
| 304 |
|
|
parameter SRAM3_INIT_62 = 256'h0,
|
| 305 |
|
|
parameter SRAM3_INIT_63 = 256'h0,
|
| 306 |
|
|
|
| 307 |
|
|
parameter UNUSED = 1'd1
|
| 308 |
|
|
|
| 309 |
|
|
)
|
| 310 |
|
|
|
| 311 |
|
|
(
|
| 312 |
|
|
input i_clk,
|
| 313 |
|
|
input [31:0] i_write_data,
|
| 314 |
|
|
input i_write_enable,
|
| 315 |
|
|
input [10:0] i_address,
|
| 316 |
|
|
input [3:0] i_byte_enable,
|
| 317 |
|
|
output [31:0] o_read_data
|
| 318 |
|
|
|
| 319 |
|
|
);
|
| 320 |
|
|
|
| 321 |
|
|
|
| 322 |
|
|
wire [3:0] wea;
|
| 323 |
|
|
wire [31:0] data_out [3:0];
|
| 324 |
|
|
|
| 325 |
|
|
assign o_read_data = { data_out[3][7:0], data_out[2][7:0],
|
| 326 |
|
|
data_out[1][7:0], data_out[0][7:0] };
|
| 327 |
|
|
|
| 328 |
|
|
assign wea = {4{i_write_enable}} & i_byte_enable;
|
| 329 |
|
|
|
| 330 |
|
|
|
| 331 |
|
|
RAMB16BWER #(
|
| 332 |
|
|
.INIT_00 ( SRAM0_INIT_0 ),
|
| 333 |
|
|
.INIT_01 ( SRAM0_INIT_1 ),
|
| 334 |
|
|
.INIT_02 ( SRAM0_INIT_2 ),
|
| 335 |
|
|
.INIT_03 ( SRAM0_INIT_3 ),
|
| 336 |
|
|
.INIT_04 ( SRAM0_INIT_4 ),
|
| 337 |
|
|
.INIT_05 ( SRAM0_INIT_5 ),
|
| 338 |
|
|
.INIT_06 ( SRAM0_INIT_6 ),
|
| 339 |
|
|
.INIT_07 ( SRAM0_INIT_7 ),
|
| 340 |
|
|
.INIT_08 ( SRAM0_INIT_8 ),
|
| 341 |
|
|
.INIT_09 ( SRAM0_INIT_9 ),
|
| 342 |
|
|
.INIT_0A ( SRAM0_INIT_10 ),
|
| 343 |
|
|
.INIT_0B ( SRAM0_INIT_11 ),
|
| 344 |
|
|
.INIT_0C ( SRAM0_INIT_12 ),
|
| 345 |
|
|
.INIT_0D ( SRAM0_INIT_13 ),
|
| 346 |
|
|
.INIT_0E ( SRAM0_INIT_14 ),
|
| 347 |
|
|
.INIT_0F ( SRAM0_INIT_15 ),
|
| 348 |
|
|
.INIT_10 ( SRAM0_INIT_16 ),
|
| 349 |
|
|
.INIT_11 ( SRAM0_INIT_17 ),
|
| 350 |
|
|
.INIT_12 ( SRAM0_INIT_18 ),
|
| 351 |
|
|
.INIT_13 ( SRAM0_INIT_19 ),
|
| 352 |
|
|
.INIT_14 ( SRAM0_INIT_20 ),
|
| 353 |
|
|
.INIT_15 ( SRAM0_INIT_21 ),
|
| 354 |
|
|
.INIT_16 ( SRAM0_INIT_22 ),
|
| 355 |
|
|
.INIT_17 ( SRAM0_INIT_23 ),
|
| 356 |
|
|
.INIT_18 ( SRAM0_INIT_24 ),
|
| 357 |
|
|
.INIT_19 ( SRAM0_INIT_25 ),
|
| 358 |
|
|
.INIT_1A ( SRAM0_INIT_26 ),
|
| 359 |
|
|
.INIT_1B ( SRAM0_INIT_27 ),
|
| 360 |
|
|
.INIT_1C ( SRAM0_INIT_28 ),
|
| 361 |
|
|
.INIT_1D ( SRAM0_INIT_29 ),
|
| 362 |
|
|
.INIT_1E ( SRAM0_INIT_30 ),
|
| 363 |
|
|
.INIT_1F ( SRAM0_INIT_31 ),
|
| 364 |
|
|
.INIT_20 ( SRAM0_INIT_32 ),
|
| 365 |
|
|
.INIT_21 ( SRAM0_INIT_33 ),
|
| 366 |
|
|
.INIT_22 ( SRAM0_INIT_34 ),
|
| 367 |
|
|
.INIT_23 ( SRAM0_INIT_35 ),
|
| 368 |
|
|
.INIT_24 ( SRAM0_INIT_36 ),
|
| 369 |
|
|
.INIT_25 ( SRAM0_INIT_37 ),
|
| 370 |
|
|
.INIT_26 ( SRAM0_INIT_38 ),
|
| 371 |
|
|
.INIT_27 ( SRAM0_INIT_39 ),
|
| 372 |
|
|
.INIT_28 ( SRAM0_INIT_40 ),
|
| 373 |
|
|
.INIT_29 ( SRAM0_INIT_41 ),
|
| 374 |
|
|
.INIT_2A ( SRAM0_INIT_42 ),
|
| 375 |
|
|
.INIT_2B ( SRAM0_INIT_43 ),
|
| 376 |
|
|
.INIT_2C ( SRAM0_INIT_44 ),
|
| 377 |
|
|
.INIT_2D ( SRAM0_INIT_45 ),
|
| 378 |
|
|
.INIT_2E ( SRAM0_INIT_46 ),
|
| 379 |
|
|
.INIT_2F ( SRAM0_INIT_47 ),
|
| 380 |
|
|
.INIT_30 ( SRAM0_INIT_48 ),
|
| 381 |
|
|
.INIT_31 ( SRAM0_INIT_49 ),
|
| 382 |
|
|
.INIT_32 ( SRAM0_INIT_50 ),
|
| 383 |
|
|
.INIT_33 ( SRAM0_INIT_51 ),
|
| 384 |
|
|
.INIT_34 ( SRAM0_INIT_52 ),
|
| 385 |
|
|
.INIT_35 ( SRAM0_INIT_53 ),
|
| 386 |
|
|
.INIT_36 ( SRAM0_INIT_54 ),
|
| 387 |
|
|
.INIT_37 ( SRAM0_INIT_55 ),
|
| 388 |
|
|
.INIT_38 ( SRAM0_INIT_56 ),
|
| 389 |
|
|
.INIT_39 ( SRAM0_INIT_57 ),
|
| 390 |
|
|
.INIT_3A ( SRAM0_INIT_58 ),
|
| 391 |
|
|
.INIT_3B ( SRAM0_INIT_59 ),
|
| 392 |
|
|
.INIT_3C ( SRAM0_INIT_60 ),
|
| 393 |
|
|
.INIT_3D ( SRAM0_INIT_61 ),
|
| 394 |
|
|
.INIT_3E ( SRAM0_INIT_62 ),
|
| 395 |
|
|
.INIT_3F ( SRAM0_INIT_63 ),
|
| 396 |
|
|
|
| 397 |
|
|
.DATA_WIDTH_A ( 9 ),
|
| 398 |
|
|
.DATA_WIDTH_B ( 9 ),
|
| 399 |
|
|
.DOA_REG ( 0 ),
|
| 400 |
|
|
.DOB_REG ( 0 ),
|
| 401 |
|
|
.EN_RSTRAM_A ( "FALSE" ),
|
| 402 |
|
|
.EN_RSTRAM_B ( "FALSE" ),
|
| 403 |
|
|
.SRVAL_A ( 36'h000000000 ),
|
| 404 |
|
|
.RSTTYPE ( "SYNC" ),
|
| 405 |
|
|
.RST_PRIORITY_A ( "CE" ),
|
| 406 |
|
|
.RST_PRIORITY_B ( "CE" ),
|
| 407 |
|
|
.SIM_COLLISION_CHECK ( "ALL" ),
|
| 408 |
|
|
.SIM_DEVICE ( "SPARTAN6" ),
|
| 409 |
|
|
.INIT_A ( 36'h000000000 ),
|
| 410 |
|
|
.INIT_B ( 36'h000000000 ),
|
| 411 |
|
|
.WRITE_MODE_A ( "READ_FIRST" ),
|
| 412 |
|
|
.WRITE_MODE_B ( "READ_FIRST" ),
|
| 413 |
|
|
.SRVAL_B ( 36'h000000000 )
|
| 414 |
|
|
)
|
| 415 |
|
|
u_sram0 (
|
| 416 |
|
|
.REGCEA ( 1'd0 ),
|
| 417 |
|
|
.CLKA ( i_clk ),
|
| 418 |
|
|
.ENB ( 1'd0 ),
|
| 419 |
|
|
.RSTB ( 1'd0 ),
|
| 420 |
|
|
.CLKB ( 1'd0 ),
|
| 421 |
|
|
.REGCEB ( 1'd0 ),
|
| 422 |
|
|
.RSTA ( 1'd0 ),
|
| 423 |
|
|
.ENA ( 1'd1 ),
|
| 424 |
|
|
.DIPA ( 4'd0 ),
|
| 425 |
|
|
.WEA ( {wea[3], wea[3], wea[3], wea[3]} ),
|
| 426 |
|
|
.DOA ( data_out[3] ),
|
| 427 |
|
|
.ADDRA ( {i_address[10:0], 3'd0} ),
|
| 428 |
|
|
.ADDRB ( 14'd0 ),
|
| 429 |
|
|
.DIB ( 32'd0 ),
|
| 430 |
|
|
.DOPA ( ),
|
| 431 |
|
|
.DIPB ( 4'd0 ),
|
| 432 |
|
|
.DOPB ( ),
|
| 433 |
|
|
.DOB ( ),
|
| 434 |
|
|
.WEB ( 4'd0 ),
|
| 435 |
|
|
.DIA ( {24'd0, i_write_data[31:24]} )
|
| 436 |
|
|
);
|
| 437 |
|
|
|
| 438 |
|
|
|
| 439 |
|
|
|
| 440 |
|
|
RAMB16BWER #(
|
| 441 |
|
|
.INIT_00 ( SRAM1_INIT_0 ),
|
| 442 |
|
|
.INIT_01 ( SRAM1_INIT_1 ),
|
| 443 |
|
|
.INIT_02 ( SRAM1_INIT_2 ),
|
| 444 |
|
|
.INIT_03 ( SRAM1_INIT_3 ),
|
| 445 |
|
|
.INIT_04 ( SRAM1_INIT_4 ),
|
| 446 |
|
|
.INIT_05 ( SRAM1_INIT_5 ),
|
| 447 |
|
|
.INIT_06 ( SRAM1_INIT_6 ),
|
| 448 |
|
|
.INIT_07 ( SRAM1_INIT_7 ),
|
| 449 |
|
|
.INIT_08 ( SRAM1_INIT_8 ),
|
| 450 |
|
|
.INIT_09 ( SRAM1_INIT_9 ),
|
| 451 |
|
|
.INIT_0A ( SRAM1_INIT_10 ),
|
| 452 |
|
|
.INIT_0B ( SRAM1_INIT_11 ),
|
| 453 |
|
|
.INIT_0C ( SRAM1_INIT_12 ),
|
| 454 |
|
|
.INIT_0D ( SRAM1_INIT_13 ),
|
| 455 |
|
|
.INIT_0E ( SRAM1_INIT_14 ),
|
| 456 |
|
|
.INIT_0F ( SRAM1_INIT_15 ),
|
| 457 |
|
|
.INIT_10 ( SRAM1_INIT_16 ),
|
| 458 |
|
|
.INIT_11 ( SRAM1_INIT_17 ),
|
| 459 |
|
|
.INIT_12 ( SRAM1_INIT_18 ),
|
| 460 |
|
|
.INIT_13 ( SRAM1_INIT_19 ),
|
| 461 |
|
|
.INIT_14 ( SRAM1_INIT_20 ),
|
| 462 |
|
|
.INIT_15 ( SRAM1_INIT_21 ),
|
| 463 |
|
|
.INIT_16 ( SRAM1_INIT_22 ),
|
| 464 |
|
|
.INIT_17 ( SRAM1_INIT_23 ),
|
| 465 |
|
|
.INIT_18 ( SRAM1_INIT_24 ),
|
| 466 |
|
|
.INIT_19 ( SRAM1_INIT_25 ),
|
| 467 |
|
|
.INIT_1A ( SRAM1_INIT_26 ),
|
| 468 |
|
|
.INIT_1B ( SRAM1_INIT_27 ),
|
| 469 |
|
|
.INIT_1C ( SRAM1_INIT_28 ),
|
| 470 |
|
|
.INIT_1D ( SRAM1_INIT_29 ),
|
| 471 |
|
|
.INIT_1E ( SRAM1_INIT_30 ),
|
| 472 |
|
|
.INIT_1F ( SRAM1_INIT_31 ),
|
| 473 |
|
|
.INIT_20 ( SRAM1_INIT_32 ),
|
| 474 |
|
|
.INIT_21 ( SRAM1_INIT_33 ),
|
| 475 |
|
|
.INIT_22 ( SRAM1_INIT_34 ),
|
| 476 |
|
|
.INIT_23 ( SRAM1_INIT_35 ),
|
| 477 |
|
|
.INIT_24 ( SRAM1_INIT_36 ),
|
| 478 |
|
|
.INIT_25 ( SRAM1_INIT_37 ),
|
| 479 |
|
|
.INIT_26 ( SRAM1_INIT_38 ),
|
| 480 |
|
|
.INIT_27 ( SRAM1_INIT_39 ),
|
| 481 |
|
|
.INIT_28 ( SRAM1_INIT_40 ),
|
| 482 |
|
|
.INIT_29 ( SRAM1_INIT_41 ),
|
| 483 |
|
|
.INIT_2A ( SRAM1_INIT_42 ),
|
| 484 |
|
|
.INIT_2B ( SRAM1_INIT_43 ),
|
| 485 |
|
|
.INIT_2C ( SRAM1_INIT_44 ),
|
| 486 |
|
|
.INIT_2D ( SRAM1_INIT_45 ),
|
| 487 |
|
|
.INIT_2E ( SRAM1_INIT_46 ),
|
| 488 |
|
|
.INIT_2F ( SRAM1_INIT_47 ),
|
| 489 |
|
|
.INIT_30 ( SRAM1_INIT_48 ),
|
| 490 |
|
|
.INIT_31 ( SRAM1_INIT_49 ),
|
| 491 |
|
|
.INIT_32 ( SRAM1_INIT_50 ),
|
| 492 |
|
|
.INIT_33 ( SRAM1_INIT_51 ),
|
| 493 |
|
|
.INIT_34 ( SRAM1_INIT_52 ),
|
| 494 |
|
|
.INIT_35 ( SRAM1_INIT_53 ),
|
| 495 |
|
|
.INIT_36 ( SRAM1_INIT_54 ),
|
| 496 |
|
|
.INIT_37 ( SRAM1_INIT_55 ),
|
| 497 |
|
|
.INIT_38 ( SRAM1_INIT_56 ),
|
| 498 |
|
|
.INIT_39 ( SRAM1_INIT_57 ),
|
| 499 |
|
|
.INIT_3A ( SRAM1_INIT_58 ),
|
| 500 |
|
|
.INIT_3B ( SRAM1_INIT_59 ),
|
| 501 |
|
|
.INIT_3C ( SRAM1_INIT_60 ),
|
| 502 |
|
|
.INIT_3D ( SRAM1_INIT_61 ),
|
| 503 |
|
|
.INIT_3E ( SRAM1_INIT_62 ),
|
| 504 |
|
|
.INIT_3F ( SRAM1_INIT_63 ),
|
| 505 |
|
|
.DATA_WIDTH_A ( 9 ),
|
| 506 |
|
|
.DATA_WIDTH_B ( 9 ),
|
| 507 |
|
|
.DOA_REG ( 0 ),
|
| 508 |
|
|
.DOB_REG ( 0 ),
|
| 509 |
|
|
.EN_RSTRAM_A ( "FALSE" ),
|
| 510 |
|
|
.EN_RSTRAM_B ( "FALSE" ),
|
| 511 |
|
|
.SRVAL_A ( 36'h000000000 ),
|
| 512 |
|
|
.INITP_00 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
|
| 513 |
|
|
.INITP_01 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
|
| 514 |
|
|
.INITP_02 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
|
| 515 |
|
|
.INITP_03 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
|
| 516 |
|
|
.INITP_04 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
|
| 517 |
|
|
.INITP_05 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
|
| 518 |
|
|
.INITP_06 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
|
| 519 |
|
|
.INITP_07 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
|
| 520 |
|
|
.RSTTYPE ( "SYNC" ),
|
| 521 |
|
|
.RST_PRIORITY_A ( "CE" ),
|
| 522 |
|
|
.RST_PRIORITY_B ( "CE" ),
|
| 523 |
|
|
.SIM_COLLISION_CHECK ( "ALL" ),
|
| 524 |
|
|
.SIM_DEVICE ( "SPARTAN6" ),
|
| 525 |
|
|
.INIT_A ( 36'h000000000 ),
|
| 526 |
|
|
.INIT_B ( 36'h000000000 ),
|
| 527 |
|
|
.WRITE_MODE_A ( "READ_FIRST" ),
|
| 528 |
|
|
.WRITE_MODE_B ( "READ_FIRST" ),
|
| 529 |
|
|
.SRVAL_B ( 36'h000000000 )
|
| 530 |
|
|
)
|
| 531 |
|
|
u_sram1 (
|
| 532 |
|
|
.REGCEA(1'd0),
|
| 533 |
|
|
.CLKA ( i_clk ),
|
| 534 |
|
|
.ENB ( 1'd0 ),
|
| 535 |
|
|
.RSTB ( 1'd0 ),
|
| 536 |
|
|
.CLKB ( 1'd0 ),
|
| 537 |
|
|
.REGCEB ( 1'd0 ),
|
| 538 |
|
|
.RSTA ( 1'd0 ),
|
| 539 |
|
|
.ENA ( 1'd1 ),
|
| 540 |
|
|
.DIPA ( 4'd0 ),
|
| 541 |
|
|
.WEA ({wea[2], wea[2], wea[2], wea[2]} ),
|
| 542 |
|
|
.DOA ( data_out[2] ),
|
| 543 |
|
|
.ADDRA ( {i_address[10:0], 3'd0} ),
|
| 544 |
|
|
.ADDRB ( 14'd0 ),
|
| 545 |
|
|
.DIB ( 32'd0 ),
|
| 546 |
|
|
.DOPA ( ),
|
| 547 |
|
|
.DIPB ( 4'd0 ),
|
| 548 |
|
|
.DOPB ( ),
|
| 549 |
|
|
.DOB ( ),
|
| 550 |
|
|
.WEB ( 4'd0 ),
|
| 551 |
|
|
.DIA ( {24'd0, i_write_data[23:16]} )
|
| 552 |
|
|
);
|
| 553 |
|
|
|
| 554 |
|
|
|
| 555 |
|
|
RAMB16BWER #(
|
| 556 |
|
|
.INIT_00 ( SRAM2_INIT_0 ),
|
| 557 |
|
|
.INIT_01 ( SRAM2_INIT_1 ),
|
| 558 |
|
|
.INIT_02 ( SRAM2_INIT_2 ),
|
| 559 |
|
|
.INIT_03 ( SRAM2_INIT_3 ),
|
| 560 |
|
|
.INIT_04 ( SRAM2_INIT_4 ),
|
| 561 |
|
|
.INIT_05 ( SRAM2_INIT_5 ),
|
| 562 |
|
|
.INIT_06 ( SRAM2_INIT_6 ),
|
| 563 |
|
|
.INIT_07 ( SRAM2_INIT_7 ),
|
| 564 |
|
|
.INIT_08 ( SRAM2_INIT_8 ),
|
| 565 |
|
|
.INIT_09 ( SRAM2_INIT_9 ),
|
| 566 |
|
|
.INIT_0A ( SRAM2_INIT_10 ),
|
| 567 |
|
|
.INIT_0B ( SRAM2_INIT_11 ),
|
| 568 |
|
|
.INIT_0C ( SRAM2_INIT_12 ),
|
| 569 |
|
|
.INIT_0D ( SRAM2_INIT_13 ),
|
| 570 |
|
|
.INIT_0E ( SRAM2_INIT_14 ),
|
| 571 |
|
|
.INIT_0F ( SRAM2_INIT_15 ),
|
| 572 |
|
|
.INIT_10 ( SRAM2_INIT_16 ),
|
| 573 |
|
|
.INIT_11 ( SRAM2_INIT_17 ),
|
| 574 |
|
|
.INIT_12 ( SRAM2_INIT_18 ),
|
| 575 |
|
|
.INIT_13 ( SRAM2_INIT_19 ),
|
| 576 |
|
|
.INIT_14 ( SRAM2_INIT_20 ),
|
| 577 |
|
|
.INIT_15 ( SRAM2_INIT_21 ),
|
| 578 |
|
|
.INIT_16 ( SRAM2_INIT_22 ),
|
| 579 |
|
|
.INIT_17 ( SRAM2_INIT_23 ),
|
| 580 |
|
|
.INIT_18 ( SRAM2_INIT_24 ),
|
| 581 |
|
|
.INIT_19 ( SRAM2_INIT_25 ),
|
| 582 |
|
|
.INIT_1A ( SRAM2_INIT_26 ),
|
| 583 |
|
|
.INIT_1B ( SRAM2_INIT_27 ),
|
| 584 |
|
|
.INIT_1C ( SRAM2_INIT_28 ),
|
| 585 |
|
|
.INIT_1D ( SRAM2_INIT_29 ),
|
| 586 |
|
|
.INIT_1E ( SRAM2_INIT_30 ),
|
| 587 |
|
|
.INIT_1F ( SRAM2_INIT_31 ),
|
| 588 |
|
|
.INIT_20 ( SRAM2_INIT_32 ),
|
| 589 |
|
|
.INIT_21 ( SRAM2_INIT_33 ),
|
| 590 |
|
|
.INIT_22 ( SRAM2_INIT_34 ),
|
| 591 |
|
|
.INIT_23 ( SRAM2_INIT_35 ),
|
| 592 |
|
|
.INIT_24 ( SRAM2_INIT_36 ),
|
| 593 |
|
|
.INIT_25 ( SRAM2_INIT_37 ),
|
| 594 |
|
|
.INIT_26 ( SRAM2_INIT_38 ),
|
| 595 |
|
|
.INIT_27 ( SRAM2_INIT_39 ),
|
| 596 |
|
|
.INIT_28 ( SRAM2_INIT_40 ),
|
| 597 |
|
|
.INIT_29 ( SRAM2_INIT_41 ),
|
| 598 |
|
|
.INIT_2A ( SRAM2_INIT_42 ),
|
| 599 |
|
|
.INIT_2B ( SRAM2_INIT_43 ),
|
| 600 |
|
|
.INIT_2C ( SRAM2_INIT_44 ),
|
| 601 |
|
|
.INIT_2D ( SRAM2_INIT_45 ),
|
| 602 |
|
|
.INIT_2E ( SRAM2_INIT_46 ),
|
| 603 |
|
|
.INIT_2F ( SRAM2_INIT_47 ),
|
| 604 |
|
|
.INIT_30 ( SRAM2_INIT_48 ),
|
| 605 |
|
|
.INIT_31 ( SRAM2_INIT_49 ),
|
| 606 |
|
|
.INIT_32 ( SRAM2_INIT_50 ),
|
| 607 |
|
|
.INIT_33 ( SRAM2_INIT_51 ),
|
| 608 |
|
|
.INIT_34 ( SRAM2_INIT_52 ),
|
| 609 |
|
|
.INIT_35 ( SRAM2_INIT_53 ),
|
| 610 |
|
|
.INIT_36 ( SRAM2_INIT_54 ),
|
| 611 |
|
|
.INIT_37 ( SRAM2_INIT_55 ),
|
| 612 |
|
|
.INIT_38 ( SRAM2_INIT_56 ),
|
| 613 |
|
|
.INIT_39 ( SRAM2_INIT_57 ),
|
| 614 |
|
|
.INIT_3A ( SRAM2_INIT_58 ),
|
| 615 |
|
|
.INIT_3B ( SRAM2_INIT_59 ),
|
| 616 |
|
|
.INIT_3C ( SRAM2_INIT_60 ),
|
| 617 |
|
|
.INIT_3D ( SRAM2_INIT_61 ),
|
| 618 |
|
|
.INIT_3E ( SRAM2_INIT_62 ),
|
| 619 |
|
|
.INIT_3F ( SRAM2_INIT_63 ),
|
| 620 |
|
|
.DATA_WIDTH_A ( 9 ),
|
| 621 |
|
|
.DATA_WIDTH_B ( 9 ),
|
| 622 |
|
|
.DOA_REG ( 0 ),
|
| 623 |
|
|
.DOB_REG ( 0 ),
|
| 624 |
|
|
.EN_RSTRAM_A ( "FALSE" ),
|
| 625 |
|
|
.EN_RSTRAM_B ( "FALSE" ),
|
| 626 |
|
|
.SRVAL_A ( 36'h000000000 ),
|
| 627 |
|
|
.INITP_00 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
|
| 628 |
|
|
.INITP_01 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
|
| 629 |
|
|
.INITP_02 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
|
| 630 |
|
|
.INITP_03 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
|
| 631 |
|
|
.INITP_04 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
|
| 632 |
|
|
.INITP_05 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
|
| 633 |
|
|
.INITP_06 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
|
| 634 |
|
|
.INITP_07 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
|
| 635 |
|
|
.RSTTYPE ( "SYNC" ),
|
| 636 |
|
|
.RST_PRIORITY_A ( "CE" ),
|
| 637 |
|
|
.RST_PRIORITY_B ( "CE" ),
|
| 638 |
|
|
.SIM_COLLISION_CHECK ( "ALL" ),
|
| 639 |
|
|
.SIM_DEVICE ( "SPARTAN6" ),
|
| 640 |
|
|
.INIT_A ( 36'h000000000 ),
|
| 641 |
|
|
.INIT_B ( 36'h000000000 ),
|
| 642 |
|
|
.WRITE_MODE_A ( "READ_FIRST" ),
|
| 643 |
|
|
.WRITE_MODE_B ( "READ_FIRST" ),
|
| 644 |
|
|
.SRVAL_B ( 36'h000000000 )
|
| 645 |
|
|
|
| 646 |
|
|
)
|
| 647 |
|
|
u_sram2 (
|
| 648 |
|
|
.REGCEA ( 1'd0 ),
|
| 649 |
|
|
.CLKA ( i_clk ),
|
| 650 |
|
|
.ENB ( 1'd0 ),
|
| 651 |
|
|
.RSTB ( 1'd0 ),
|
| 652 |
|
|
.CLKB ( 1'd0 ),
|
| 653 |
|
|
.REGCEB ( 1'd0 ),
|
| 654 |
|
|
.RSTA ( 1'd0 ),
|
| 655 |
|
|
.ENA ( 1'd1 ),
|
| 656 |
|
|
.DIPA ( 4'd0 ),
|
| 657 |
|
|
.WEA ( {wea[1], wea[1], wea[1], wea[1]} ),
|
| 658 |
|
|
.DOA ( data_out[1] ),
|
| 659 |
|
|
.ADDRA ( {i_address[10:0], 3'd0} ),
|
| 660 |
|
|
.ADDRB ( 14'd0 ),
|
| 661 |
|
|
.DIB ( 32'd0 ),
|
| 662 |
|
|
.DOPA ( ),
|
| 663 |
|
|
.DIPB ( 4'd0 ),
|
| 664 |
|
|
.DOPB ( ),
|
| 665 |
|
|
.DOB ( ),
|
| 666 |
|
|
.WEB ( 4'd0 ),
|
| 667 |
|
|
.DIA ( {24'd0, i_write_data[15:08]} )
|
| 668 |
|
|
);
|
| 669 |
|
|
|
| 670 |
|
|
|
| 671 |
|
|
|
| 672 |
|
|
|
| 673 |
|
|
RAMB16BWER #(
|
| 674 |
|
|
.INIT_00 ( SRAM3_INIT_0 ),
|
| 675 |
|
|
.INIT_01 ( SRAM3_INIT_1 ),
|
| 676 |
|
|
.INIT_02 ( SRAM3_INIT_2 ),
|
| 677 |
|
|
.INIT_03 ( SRAM3_INIT_3 ),
|
| 678 |
|
|
.INIT_04 ( SRAM3_INIT_4 ),
|
| 679 |
|
|
.INIT_05 ( SRAM3_INIT_5 ),
|
| 680 |
|
|
.INIT_06 ( SRAM3_INIT_6 ),
|
| 681 |
|
|
.INIT_07 ( SRAM3_INIT_7 ),
|
| 682 |
|
|
.INIT_08 ( SRAM3_INIT_8 ),
|
| 683 |
|
|
.INIT_09 ( SRAM3_INIT_9 ),
|
| 684 |
|
|
.INIT_0A ( SRAM3_INIT_10 ),
|
| 685 |
|
|
.INIT_0B ( SRAM3_INIT_11 ),
|
| 686 |
|
|
.INIT_0C ( SRAM3_INIT_12 ),
|
| 687 |
|
|
.INIT_0D ( SRAM3_INIT_13 ),
|
| 688 |
|
|
.INIT_0E ( SRAM3_INIT_14 ),
|
| 689 |
|
|
.INIT_0F ( SRAM3_INIT_15 ),
|
| 690 |
|
|
.INIT_10 ( SRAM3_INIT_16 ),
|
| 691 |
|
|
.INIT_11 ( SRAM3_INIT_17 ),
|
| 692 |
|
|
.INIT_12 ( SRAM3_INIT_18 ),
|
| 693 |
|
|
.INIT_13 ( SRAM3_INIT_19 ),
|
| 694 |
|
|
.INIT_14 ( SRAM3_INIT_20 ),
|
| 695 |
|
|
.INIT_15 ( SRAM3_INIT_21 ),
|
| 696 |
|
|
.INIT_16 ( SRAM3_INIT_22 ),
|
| 697 |
|
|
.INIT_17 ( SRAM3_INIT_23 ),
|
| 698 |
|
|
.INIT_18 ( SRAM3_INIT_24 ),
|
| 699 |
|
|
.INIT_19 ( SRAM3_INIT_25 ),
|
| 700 |
|
|
.INIT_1A ( SRAM3_INIT_26 ),
|
| 701 |
|
|
.INIT_1B ( SRAM3_INIT_27 ),
|
| 702 |
|
|
.INIT_1C ( SRAM3_INIT_28 ),
|
| 703 |
|
|
.INIT_1D ( SRAM3_INIT_29 ),
|
| 704 |
|
|
.INIT_1E ( SRAM3_INIT_30 ),
|
| 705 |
|
|
.INIT_1F ( SRAM3_INIT_31 ),
|
| 706 |
|
|
.INIT_20 ( SRAM3_INIT_32 ),
|
| 707 |
|
|
.INIT_21 ( SRAM3_INIT_33 ),
|
| 708 |
|
|
.INIT_22 ( SRAM3_INIT_34 ),
|
| 709 |
|
|
.INIT_23 ( SRAM3_INIT_35 ),
|
| 710 |
|
|
.INIT_24 ( SRAM3_INIT_36 ),
|
| 711 |
|
|
.INIT_25 ( SRAM3_INIT_37 ),
|
| 712 |
|
|
.INIT_26 ( SRAM3_INIT_38 ),
|
| 713 |
|
|
.INIT_27 ( SRAM3_INIT_39 ),
|
| 714 |
|
|
.INIT_28 ( SRAM3_INIT_40 ),
|
| 715 |
|
|
.INIT_29 ( SRAM3_INIT_41 ),
|
| 716 |
|
|
.INIT_2A ( SRAM3_INIT_42 ),
|
| 717 |
|
|
.INIT_2B ( SRAM3_INIT_43 ),
|
| 718 |
|
|
.INIT_2C ( SRAM3_INIT_44 ),
|
| 719 |
|
|
.INIT_2D ( SRAM3_INIT_45 ),
|
| 720 |
|
|
.INIT_2E ( SRAM3_INIT_46 ),
|
| 721 |
|
|
.INIT_2F ( SRAM3_INIT_47 ),
|
| 722 |
|
|
.INIT_30 ( SRAM3_INIT_48 ),
|
| 723 |
|
|
.INIT_31 ( SRAM3_INIT_49 ),
|
| 724 |
|
|
.INIT_32 ( SRAM3_INIT_50 ),
|
| 725 |
|
|
.INIT_33 ( SRAM3_INIT_51 ),
|
| 726 |
|
|
.INIT_34 ( SRAM3_INIT_52 ),
|
| 727 |
|
|
.INIT_35 ( SRAM3_INIT_53 ),
|
| 728 |
|
|
.INIT_36 ( SRAM3_INIT_54 ),
|
| 729 |
|
|
.INIT_37 ( SRAM3_INIT_55 ),
|
| 730 |
|
|
.INIT_38 ( SRAM3_INIT_56 ),
|
| 731 |
|
|
.INIT_39 ( SRAM3_INIT_57 ),
|
| 732 |
|
|
.INIT_3A ( SRAM3_INIT_58 ),
|
| 733 |
|
|
.INIT_3B ( SRAM3_INIT_59 ),
|
| 734 |
|
|
.INIT_3C ( SRAM3_INIT_60 ),
|
| 735 |
|
|
.INIT_3D ( SRAM3_INIT_61 ),
|
| 736 |
|
|
.INIT_3E ( SRAM3_INIT_62 ),
|
| 737 |
|
|
.INIT_3F ( SRAM3_INIT_63 ),
|
| 738 |
|
|
.DATA_WIDTH_A ( 9 ),
|
| 739 |
|
|
.DATA_WIDTH_B ( 9 ),
|
| 740 |
|
|
.DOA_REG ( 0 ),
|
| 741 |
|
|
.DOB_REG ( 0 ),
|
| 742 |
|
|
.EN_RSTRAM_A ( "FALSE" ),
|
| 743 |
|
|
.EN_RSTRAM_B ( "FALSE" ),
|
| 744 |
|
|
.SRVAL_A ( 36'h000000000 ),
|
| 745 |
|
|
.INITP_00 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
|
| 746 |
|
|
.INITP_01 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
|
| 747 |
|
|
.INITP_02 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
|
| 748 |
|
|
.INITP_03 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
|
| 749 |
|
|
.INITP_04 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
|
| 750 |
|
|
.INITP_05 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
|
| 751 |
|
|
.INITP_06 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
|
| 752 |
|
|
.INITP_07 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
|
| 753 |
|
|
.RSTTYPE ( "SYNC" ),
|
| 754 |
|
|
.RST_PRIORITY_A ( "CE" ),
|
| 755 |
|
|
.RST_PRIORITY_B ( "CE" ),
|
| 756 |
|
|
.SIM_COLLISION_CHECK ( "ALL" ),
|
| 757 |
|
|
.SIM_DEVICE ( "SPARTAN6" ),
|
| 758 |
|
|
.INIT_A ( 36'h000000000 ),
|
| 759 |
|
|
.INIT_B ( 36'h000000000 ),
|
| 760 |
|
|
.WRITE_MODE_A ( "READ_FIRST" ),
|
| 761 |
|
|
.WRITE_MODE_B ( "READ_FIRST" ),
|
| 762 |
|
|
.SRVAL_B ( 36'h000000000 )
|
| 763 |
|
|
)
|
| 764 |
|
|
u_sram3 (
|
| 765 |
|
|
.REGCEA ( 1'd0 ),
|
| 766 |
|
|
.CLKA ( i_clk ),
|
| 767 |
|
|
.ENB ( 1'd0 ),
|
| 768 |
|
|
.RSTB ( 1'd0 ),
|
| 769 |
|
|
.CLKB ( 1'd0 ),
|
| 770 |
|
|
.REGCEB ( 1'd0 ),
|
| 771 |
|
|
.RSTA ( 1'd0 ),
|
| 772 |
|
|
.ENA ( 1'd1 ),
|
| 773 |
|
|
.WEA ({wea[0], wea[0], wea[0], wea[0]} ),
|
| 774 |
|
|
.DOA ( data_out[0] ),
|
| 775 |
|
|
.ADDRA ({i_address[10:0], 3'd0} ),
|
| 776 |
|
|
.ADDRB ( 14'd0 ),
|
| 777 |
|
|
.DIA ( {24'd0, i_write_data[7:0]} ),
|
| 778 |
|
|
.DIB ( 32'd0 ),
|
| 779 |
|
|
.DIPA ( 4'd0 ),
|
| 780 |
|
|
.DIPB ( 4'd0 ),
|
| 781 |
|
|
.DOPA ( ),
|
| 782 |
|
|
.DOPB ( ),
|
| 783 |
|
|
.DOB ( ),
|
| 784 |
|
|
.WEB ( 4'd0 )
|
| 785 |
|
|
);
|
| 786 |
|
|
|
| 787 |
|
|
|
| 788 |
|
|
endmodule
|
