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//////////////////////////////////////////////////////////////////
//                                                              //
//  Testbench UART                                              //
//                                                              //
//  This file is part of the Amber project                      //
//  http://www.opencores.org/project,amber                      //
//                                                              //
//  Description                                                 //
//  Provides a target to test the wishbone UART against.        //
//                                                              //
//  Author(s):                                                  //
//      - Conor Santifort, csantifort.amber@gmail.com           //
//                                                              //
//////////////////////////////////////////////////////////////////
//                                                              //
// Copyright (C) 2010 Authors and OPENCORES.ORG                 //
//                                                              //
// This source file may be used and distributed without         //
// restriction provided that this copyright statement is not    //
// removed from the file and that any derivative work contains  //
// the original copyright notice and the associated disclaimer. //
//                                                              //
// This source file is free software; you can redistribute it   //
// and/or modify it under the terms of the GNU Lesser General   //
// Public License as published by the Free Software Foundation; //
// either version 2.1 of the License, or (at your option) any   //
// later version.                                               //
//                                                              //
// This source is distributed in the hope that it will be       //
// useful, but WITHOUT ANY WARRANTY; without even the implied   //
// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      //
// PURPOSE.  See the GNU Lesser General Public License for more //
// details.                                                     //
//                                                              //
// You should have received a copy of the GNU Lesser General    //
// Public License along with this source; if not, download it   //
// from http://www.opencores.org/lgpl.shtml                     //
//                                                              //
//////////////////////////////////////////////////////////////////
 
`timescale  1 ps / 1 ps
`include "system_config_defines.v"
`include "global_defines.v"
 
 
module tb_uart (
input                       i_uart_cts_n,          // Clear To Send
output reg                  o_uart_txd,
output                      o_uart_rts_n,          // Request to Send
input                       i_uart_rxd
 
);
 
assign o_uart_rts_n = 1'd0;  // allow the other side to transmit all the time
 
// -------------------------------------------------------------------------
// Baud Rate Configuration
// -------------------------------------------------------------------------
 
// Baud period in nanoseconds
localparam UART_BAUD         = `AMBER_UART_BAUD;            // Hz
localparam UART_BIT_PERIOD   = 1000000000 / UART_BAUD;      // nS
 
// -------------------------------------------------------------------------
 
reg             clk_uart;
reg             clk_uart_rst_n;
 
reg [1:0]       rx_state;
reg [2:0]       rx_bit;
reg [7:0]       rx_byte;
reg [3:0]       rx_tap;
reg [3:0]       rx_bit_count;
wire            rx_bit_start;
wire            rx_start_negedge;
reg             rx_start_negedge_d1;
 
reg [1:0]       tx_state;
reg [2:0]       tx_bit;
reg [7:0]       tx_byte;
reg [3:0]       tx_bit_count;
wire            tx_bit_start;
wire            tx_start;
wire            loopback;
wire            tx_push;
reg             tx_push_r;
wire            tx_push_toggle;
wire [7:0]      txd;
 
wire            txfifo_empty;
wire            txfifo_full;
reg  [7:0]      tx_fifo [15:0];
reg  [4:0]      txfifo_wp;
reg  [4:0]      txfifo_rp;
 
 
// ======================================================
// UART Clock
// ======================================================
 
// runs at 10x baud rate
initial
    begin
    clk_uart        = 1'd0;
    forever #(UART_BIT_PERIOD*100/2) clk_uart = ~clk_uart;
    end
 
initial
    begin
    // in reset
    clk_uart_rst_n  = 1'd0;
    // out of reset
    #(UART_BIT_PERIOD*1000) clk_uart_rst_n  = 1'd1;
    end
 
 
// ======================================================
// UART Receive
// ======================================================
always @( posedge clk_uart or negedge clk_uart_rst_n )
    if ( ~clk_uart_rst_n )
        rx_bit_count <= 'd0;
    else if ( rx_bit_count == 4'd9 )
        rx_bit_count <= 'd0;
    // align the bit count to the centre each incoming bit    
    else if ( rx_start_negedge )
        rx_bit_count <= 'd0;
    else
        rx_bit_count <= rx_bit_count + 1'd1;
 
assign rx_bit_start     = rx_bit_count == 4'd0;
assign rx_start_negedge = rx_tap[3] && !rx_tap[2] && rx_state == 2'd0;
 
always @( posedge clk_uart or negedge clk_uart_rst_n )
    if ( ~clk_uart_rst_n )
        begin
        rx_state            <= 'd0;
        rx_bit              <= 'd0;
        rx_byte             <= 'd0;
        rx_tap              <= 'd0;
        rx_start_negedge_d1 <= 'd0;
        end
    else
        begin
        rx_tap <= { rx_tap[2:0], i_uart_rxd };
        rx_start_negedge_d1 <= rx_start_negedge;
 
        if ( rx_bit_start )
            begin
            case ( rx_state )
 
                // wait for start bit edge at end of tap
                // then sample bits at start of tap, approx
                // in the center of each bit
                2'd0: if ( rx_start_negedge_d1 )
                        rx_state <= 2'd1;
 
                // 8 bits in a word        
                2'd1: if ( rx_bit == 3'd7 )
                        rx_state <= 2'd2;
 
                // stop bit
                2'd2: rx_state <= 2'd0;
 
            endcase
 
            if ( rx_state == 2'd1 )
                begin
                rx_bit  <= rx_bit + 1'd1;
                // UART sends LSB first
                rx_byte <= {i_uart_rxd, rx_byte[7:1]};
                end
 
            // Ignore carriage returns so don't get a blank line
            // between every printed line in silumations   
            if ( rx_state == 2'd2 && rx_byte != 8'h0d && rx_byte != 8'h0c )
                $write("%c", rx_byte);
            end
        end
 
 
// ========================================================
// UART Transmit
// ========================================================
 
// Get control bits from the wishbone uart test register
assign tx_start     = `U_TEST_MODULE.tb_uart_control_reg[0];
assign loopback     = `U_TEST_MODULE.tb_uart_control_reg[1];
 
always @* `U_TEST_MODULE.tb_uart_status_reg[1:0] = {txfifo_full, txfifo_empty};
 
assign tx_push      = `U_TEST_MODULE.tb_uart_push;
assign txd          = `U_TEST_MODULE.tb_uart_txd_reg;
 
assign tx_bit_start = tx_bit_count == 4'd0;
assign txfifo_empty = txfifo_wp == txfifo_rp;
assign txfifo_full  = txfifo_wp == {~txfifo_rp[4], txfifo_rp[3:0]};
 
 
// Detect when the tx_push signal changes value. It is on a different
// clock domain so this is needed to detect it cleanly
always @( posedge clk_uart or negedge clk_uart_rst_n )
    if ( ~clk_uart_rst_n )
        tx_push_r <= 'd0;
    else
        tx_push_r <= tx_push;
 
assign tx_push_toggle =  tx_push ^ tx_push_r;
 
 
always @( posedge clk_uart or negedge clk_uart_rst_n )
    if ( ~clk_uart_rst_n )
        tx_bit_count <= 'd0;
    else if ( tx_bit_count == 4'd9 )
        tx_bit_count <= 'd0;
    else
        tx_bit_count <= tx_bit_count + 1'd1;
 
 
// Transmit FIFO. 8 entries
always @( posedge clk_uart or negedge clk_uart_rst_n )
    if ( ~clk_uart_rst_n )
        begin
        txfifo_wp               <=    'd0;
        end
    else if ( !loopback && tx_push_toggle && !txfifo_full )
        begin
        tx_fifo[txfifo_wp[3:0]] <=    txd;
        txfifo_wp               <=    txfifo_wp + 1'd1;
        end
    else if ( !loopback && tx_push_toggle && txfifo_full )
        begin
        `TB_WARNING_MESSAGE
        $display("TB UART FIFO overflow");
        end
    // loopback received byte into tx buffer    
    else if ( loopback && rx_state == 2'd2 && rx_bit_start )
        begin
        tx_fifo[txfifo_wp[3:0]] <=    rx_byte;
        txfifo_wp               <=    txfifo_wp + 1'd1;
        end
 
 
always @( posedge clk_uart or negedge clk_uart_rst_n )
    if ( ~clk_uart_rst_n )
        begin
        tx_state            <= 'd0;
        tx_bit              <= 'd0;
        tx_byte             <= 'd0;
        o_uart_txd          <= 1'd1;
        txfifo_rp           <= 'd0;
        end
    else
        begin
        if ( tx_bit_start )
            begin
            case ( tx_state )
 
                // wait for trigger to start transmitting
                2'd0: if ( tx_start && !txfifo_empty && !i_uart_cts_n )
                        begin
                        tx_state    <= 2'd1;
                        tx_byte     <= tx_fifo[txfifo_rp[3:0]];
                        txfifo_rp   <= txfifo_rp + 1'd1;
                        // transmit start bit
                        o_uart_txd  <= 1'd0;
                        end
 
                // 8 bits in a word        
                2'd1: if ( !i_uart_cts_n )
                        begin
                        if ( tx_bit == 3'd7 )
                            tx_state <= 2'd2;
                        tx_bit      <= tx_bit + 1'd1;
                        tx_byte     <= {1'd0, tx_byte[7:1]};
                        // UART sends LSB first
                        o_uart_txd  <= tx_byte[0];
                        end
 
                // stop bit
                2'd2:   begin
                        tx_state    <= 2'd0;
                        o_uart_txd  <= 1'd1;
                        end
            endcase
            end
        end
 
 
endmodule
 

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[/] [amber/] [trunk/] [hw/] [vlog/] [tb/] [tb_uart.v] - Blame information for rev 63

Line No.	Rev	Author	Line
1	2	csantifort	`//////////////////////////////////////////////////////////////////`
2			`// //`
3			`// Testbench UART //`
4			`// //`
5			`// This file is part of the Amber project //`
6			`// http://www.opencores.org/project,amber //`
7			`// //`
8			`// Description //`
9			`// Provides a target to test the wishbone UART against. //`
10			`// //`
11			`// Author(s): //`
12			`// - Conor Santifort, csantifort.amber@gmail.com //`
13			`// //`
14			`//////////////////////////////////////////////////////////////////`
15			`// //`
16			`// Copyright (C) 2010 Authors and OPENCORES.ORG //`
17			`// //`
18			`// This source file may be used and distributed without //`
19			`// restriction provided that this copyright statement is not //`
20			`// removed from the file and that any derivative work contains //`
21			`// the original copyright notice and the associated disclaimer. //`
22			`// //`
23			`// This source file is free software; you can redistribute it //`
24			`// and/or modify it under the terms of the GNU Lesser General //`
25			`// Public License as published by the Free Software Foundation; //`
26			`// either version 2.1 of the License, or (at your option) any //`
27			`// later version. //`
28			`// //`
29			`// This source is distributed in the hope that it will be //`
30			`// useful, but WITHOUT ANY WARRANTY; without even the implied //`
31			`// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //`
32			`// PURPOSE. See the GNU Lesser General Public License for more //`
33			`// details. //`
34			`// //`
35			`// You should have received a copy of the GNU Lesser General //`
36			`// Public License along with this source; if not, download it //`
37			`// from http://www.opencores.org/lgpl.shtml //`
38			`// //`
39			`//////////////////////////////////////////////////////////////////`
40
41	27	csantifort	`timescale 1 ps / 1 ps
42	63	csantifort	`include "system_config_defines.v"
43			`include "global_defines.v"
44	2	csantifort
45	63	csantifort
46	2	csantifort	`module tb_uart (`
47			`input i_uart_cts_n, // Clear To Send`
48			`output reg o_uart_txd,`
49			`output o_uart_rts_n, // Request to Send`
50			`input i_uart_rxd`
51
52			`);`
53
54			`assign o_uart_rts_n = 1'd0; // allow the other side to transmit all the time`
55
56			`// -------------------------------------------------------------------------`
57			`// Baud Rate Configuration`
58			`// -------------------------------------------------------------------------`
59
60			`// Baud period in nanoseconds`
61			localparam UART_BAUD = `AMBER_UART_BAUD; // Hz
62			`localparam UART_BIT_PERIOD = 1000000000 / UART_BAUD; // nS`
63
64			`// -------------------------------------------------------------------------`
65
66			`reg clk_uart;`
67			`reg clk_uart_rst_n;`
68
69			`reg [1:0] rx_state;`
70			`reg [2:0] rx_bit;`
71			`reg [7:0] rx_byte;`
72			`reg [3:0] rx_tap;`
73			`reg [3:0] rx_bit_count;`
74			`wire rx_bit_start;`
75			`wire rx_start_negedge;`
76			`reg rx_start_negedge_d1;`
77
78			`reg [1:0] tx_state;`
79			`reg [2:0] tx_bit;`
80			`reg [7:0] tx_byte;`
81			`reg [3:0] tx_bit_count;`
82			`wire tx_bit_start;`
83			`wire tx_start;`
84			`wire loopback;`
85			`wire tx_push;`
86			`reg tx_push_r;`
87			`wire tx_push_toggle;`
88			`wire [7:0] txd;`
89
90			`wire txfifo_empty;`
91			`wire txfifo_full;`
92			`reg [7:0] tx_fifo [15:0];`
93			`reg [4:0] txfifo_wp;`
94			`reg [4:0] txfifo_rp;`
95
96
97			`// ======================================================`
98			`// UART Clock`
99			`// ======================================================`
100
101			`// runs at 10x baud rate`
102			`initial`
103			`begin`
104			`clk_uart = 1'd0;`
105			`forever #(UART_BIT_PERIOD*100/2) clk_uart = ~clk_uart;`
106			`end`
107
108			`initial`
109			`begin`
110			`// in reset`
111			`clk_uart_rst_n = 1'd0;`
112			`// out of reset`
113			`#(UART_BIT_PERIOD*1000) clk_uart_rst_n = 1'd1;`
114			`end`
115
116
117			`// ======================================================`
118			`// UART Receive`
119			`// ======================================================`
120			`always @( posedge clk_uart or negedge clk_uart_rst_n )`
121			`if ( ~clk_uart_rst_n )`
122			`rx_bit_count <= 'd0;`
123			`else if ( rx_bit_count == 4'd9 )`
124			`rx_bit_count <= 'd0;`
125			`// align the bit count to the centre each incoming bit`
126			`else if ( rx_start_negedge )`
127			`rx_bit_count <= 'd0;`
128			`else`
129			`rx_bit_count <= rx_bit_count + 1'd1;`
130
131			`assign rx_bit_start = rx_bit_count == 4'd0;`
132			`assign rx_start_negedge = rx_tap[3] && !rx_tap[2] && rx_state == 2'd0;`
133
134			`always @( posedge clk_uart or negedge clk_uart_rst_n )`
135			`if ( ~clk_uart_rst_n )`
136			`begin`
137			`rx_state <= 'd0;`
138			`rx_bit <= 'd0;`
139			`rx_byte <= 'd0;`
140			`rx_tap <= 'd0;`
141			`rx_start_negedge_d1 <= 'd0;`
142			`end`
143			`else`
144			`begin`
145			`rx_tap <= { rx_tap[2:0], i_uart_rxd };`
146			`rx_start_negedge_d1 <= rx_start_negedge;`
147
148			`if ( rx_bit_start )`
149			`begin`
150			`case ( rx_state )`
151
152			`// wait for start bit edge at end of tap`
153			`// then sample bits at start of tap, approx`
154			`// in the center of each bit`
155			`2'd0: if ( rx_start_negedge_d1 )`
156			`rx_state <= 2'd1;`
157
158			`// 8 bits in a word`
159			`2'd1: if ( rx_bit == 3'd7 )`
160			`rx_state <= 2'd2;`
161
162			`// stop bit`
163			`2'd2: rx_state <= 2'd0;`
164
165			`endcase`
166
167			`if ( rx_state == 2'd1 )`
168			`begin`
169			`rx_bit <= rx_bit + 1'd1;`
170			`// UART sends LSB first`
171			`rx_byte <= {i_uart_rxd, rx_byte[7:1]};`
172			`end`
173
174			`// Ignore carriage returns so don't get a blank line`
175			`// between every printed line in silumations`
176			`if ( rx_state == 2'd2 && rx_byte != 8'h0d && rx_byte != 8'h0c )`
177			`$write("%c", rx_byte);`
178			`end`
179			`end`
180
181
182			`// ========================================================`
183			`// UART Transmit`
184			`// ========================================================`
185
186			`// Get control bits from the wishbone uart test register`
187			assign tx_start = `U_TEST_MODULE.tb_uart_control_reg[0];
188			assign loopback = `U_TEST_MODULE.tb_uart_control_reg[1];
189
190			always @* `U_TEST_MODULE.tb_uart_status_reg[1:0] = {txfifo_full, txfifo_empty};
191
192			assign tx_push = `U_TEST_MODULE.tb_uart_push;
193			assign txd = `U_TEST_MODULE.tb_uart_txd_reg;
194
195			`assign tx_bit_start = tx_bit_count == 4'd0;`
196			`assign txfifo_empty = txfifo_wp == txfifo_rp;`
197			`assign txfifo_full = txfifo_wp == {~txfifo_rp[4], txfifo_rp[3:0]};`
198
199
200			`// Detect when the tx_push signal changes value. It is on a different`
201			`// clock domain so this is needed to detect it cleanly`
202			`always @( posedge clk_uart or negedge clk_uart_rst_n )`
203			`if ( ~clk_uart_rst_n )`
204			`tx_push_r <= 'd0;`
205			`else`
206			`tx_push_r <= tx_push;`
207
208			`assign tx_push_toggle = tx_push ^ tx_push_r;`
209
210
211			`always @( posedge clk_uart or negedge clk_uart_rst_n )`
212			`if ( ~clk_uart_rst_n )`
213			`tx_bit_count <= 'd0;`
214			`else if ( tx_bit_count == 4'd9 )`
215			`tx_bit_count <= 'd0;`
216			`else`
217			`tx_bit_count <= tx_bit_count + 1'd1;`
218
219
220			`// Transmit FIFO. 8 entries`
221			`always @( posedge clk_uart or negedge clk_uart_rst_n )`
222			`if ( ~clk_uart_rst_n )`
223			`begin`
224			`txfifo_wp <= 'd0;`
225			`end`
226			`else if ( !loopback && tx_push_toggle && !txfifo_full )`
227			`begin`
228			`tx_fifo[txfifo_wp[3:0]] <= txd;`
229			`txfifo_wp <= txfifo_wp + 1'd1;`
230			`end`
231			`else if ( !loopback && tx_push_toggle && txfifo_full )`
232			`begin`
233			`TB_WARNING_MESSAGE
234			`$display("TB UART FIFO overflow");`
235			`end`
236			`// loopback received byte into tx buffer`
237			`else if ( loopback && rx_state == 2'd2 && rx_bit_start )`
238			`begin`
239			`tx_fifo[txfifo_wp[3:0]] <= rx_byte;`
240			`txfifo_wp <= txfifo_wp + 1'd1;`
241			`end`
242
243
244			`always @( posedge clk_uart or negedge clk_uart_rst_n )`
245			`if ( ~clk_uart_rst_n )`
246			`begin`
247			`tx_state <= 'd0;`
248			`tx_bit <= 'd0;`
249			`tx_byte <= 'd0;`
250			`o_uart_txd <= 1'd1;`
251			`txfifo_rp <= 'd0;`
252			`end`
253			`else`
254			`begin`
255			`if ( tx_bit_start )`
256			`begin`
257			`case ( tx_state )`
258
259			`// wait for trigger to start transmitting`
260			`2'd0: if ( tx_start && !txfifo_empty && !i_uart_cts_n )`
261			`begin`
262			`tx_state <= 2'd1;`
263			`tx_byte <= tx_fifo[txfifo_rp[3:0]];`
264			`txfifo_rp <= txfifo_rp + 1'd1;`
265			`// transmit start bit`
266			`o_uart_txd <= 1'd0;`
267			`end`
268
269			`// 8 bits in a word`
270			`2'd1: if ( !i_uart_cts_n )`
271			`begin`
272			`if ( tx_bit == 3'd7 )`
273			`tx_state <= 2'd2;`
274			`tx_bit <= tx_bit + 1'd1;`
275			`tx_byte <= {1'd0, tx_byte[7:1]};`
276			`// UART sends LSB first`
277			`o_uart_txd <= tx_byte[0];`
278			`end`
279
280			`// stop bit`
281			`2'd2: begin`
282			`tx_state <= 2'd0;`
283			`o_uart_txd <= 1'd1;`
284			`end`
285			`endcase`
286			`end`
287			`end`
288
289
290			`endmodule`
291