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Subversion Repositories an-fpga-implementation-of-low-latency-noc-based-mpsoc

[/] [an-fpga-implementation-of-low-latency-noc-based-mpsoc/] [trunk/] [mpsoc/] [boards/] [Altera/] [DE0_nano/] [DE0_nano.v] - Blame information for rev 48

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1 48 alirezamon 
//=======================================================
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//  This code is generated by Terasic System Builder
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//=======================================================
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module DE0_Nano(
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        //////////// CLOCK //////////
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        CLOCK_50,
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        //////////// LED //////////
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        LED,
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        //////////// KEY //////////
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        KEY,
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        //////////// SW //////////
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        SW,
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        //////////// SDRAM //////////
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        DRAM_ADDR,
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        DRAM_BA,
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        DRAM_CAS_N,
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        DRAM_CKE,
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        DRAM_CLK,
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        DRAM_CS_N,
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        DRAM_DQ,
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        DRAM_DQM,
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        DRAM_RAS_N,
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        DRAM_WE_N,
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        //////////// EPCS //////////
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        EPCS_ASDO,
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        EPCS_DATA0,
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        EPCS_DCLK,
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        EPCS_NCSO,
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        //////////// Accelerometer and EEPROM //////////
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        G_SENSOR_CS_N,
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        G_SENSOR_INT,
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        I2C_SCLK,
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        I2C_SDAT,
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        //////////// ADC //////////
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        ADC_CS_N,
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        ADC_SADDR,
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        ADC_SCLK,
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        ADC_SDAT,
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        //////////// 2x13 GPIO Header //////////
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        GPIO_2,
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        GPIO_2_IN,
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        //////////// GPIO_0, GPIO_0 connect to GPIO Default //////////
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        GPIO_0,
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        GPIO_0_IN,
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        //////////// GPIO_1, GPIO_1 connect to GPIO Default //////////
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        GPIO_1,
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        GPIO_1_IN
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);
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//=======================================================
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//  PARAMETER declarations
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//=======================================================
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//=======================================================
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//  PORT declarations
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//=======================================================
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//////////// CLOCK //////////
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input                                   CLOCK_50;
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//////////// LED //////////
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output               [7:0]               LED;
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//////////// KEY //////////
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input                [1:0]               KEY;
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//////////// SW //////////
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input                [3:0]               SW;
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//////////// SDRAM //////////
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output              [12:0]               DRAM_ADDR;
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output               [1:0]               DRAM_BA;
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output                                  DRAM_CAS_N;
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output                                  DRAM_CKE;
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output                                  DRAM_CLK;
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output                                  DRAM_CS_N;
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inout               [15:0]               DRAM_DQ;
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output               [1:0]               DRAM_DQM;
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output                                  DRAM_RAS_N;
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output                                  DRAM_WE_N;
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//////////// EPCS //////////
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output                                  EPCS_ASDO;
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input                                   EPCS_DATA0;
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output                                  EPCS_DCLK;
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output                                  EPCS_NCSO;
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//////////// Accelerometer and EEPROM //////////
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output                                  G_SENSOR_CS_N;
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input                                   G_SENSOR_INT;
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output                                  I2C_SCLK;
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inout                                   I2C_SDAT;
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//////////// ADC //////////
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output                                  ADC_CS_N;
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output                                  ADC_SADDR;
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output                                  ADC_SCLK;
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input                                   ADC_SDAT;
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//////////// 2x13 GPIO Header //////////
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inout               [12:0]               GPIO_2;
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input                [2:0]               GPIO_2_IN;
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//////////// GPIO_0, GPIO_0 connect to GPIO Default //////////
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inout               [33:0]               GPIO_0;
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input                [1:0]               GPIO_0_IN;
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//////////// GPIO_1, GPIO_1 connect to GPIO Default //////////
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inout               [33:0]               GPIO_1;
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input                [1:0]               GPIO_1_IN;
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//=======================================================
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//  REG/WIRE declarations
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//=======================================================
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//=======================================================
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//  Structural coding
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//=======================================================
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endmodule

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