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[/] [an-fpga-implementation-of-low-latency-noc-based-mpsoc/] [trunk/] [mpsoc/] [boards/] [Altera/] [DE1_SoC/] [DE1_SoC.v] - Blame information for rev 48

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1 48 alirezamon 
============================================================================
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// Copyright (c) 2013 by Terasic Technologies Inc.
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// ============================================================================
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//
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// Permission:
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//
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//   Terasic grants permission to use and modify this code for use
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//   in synthesis for all Terasic Development Boards and Altera Development
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//   Kits made by Terasic.  Other use of this code, including the selling
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//   ,duplication, or modification of any portion is strictly prohibited.
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//
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// Disclaimer:
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//
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//   This VHDL/Verilog or C/C++ source code is intended as a design reference
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//   which illustrates how these types of functions can be implemented.
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//   It is the user's responsibility to verify their design for
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//   consistency and functionality through the use of formal
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//   verification methods.  Terasic provides no warranty regarding the use
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//   or functionality of this code.
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//
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// ============================================================================
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//
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//  Terasic Technologies Inc
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//  9F., No.176, Sec.2, Gongdao 5th Rd, East Dist, Hsinchu City, 30070. Taiwan
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//
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//
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//                     web: http://www.terasic.com/
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//                     email: support@terasic.com
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//
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// ============================================================================
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//Date:  Thu Jul 11 11:26:45 2013
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// ============================================================================
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`define ENABLE_ADC
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`define ENABLE_AUD
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`define ENABLE_CLOCK2
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`define ENABLE_CLOCK3
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`define ENABLE_CLOCK4
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`define ENABLE_CLOCK
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`define ENABLE_DRAM
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`define ENABLE_FAN
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`define ENABLE_FPGA
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`define ENABLE_GPIO
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`define ENABLE_HEX
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//`define ENABLE_HPS
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`define ENABLE_IRDA
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`define ENABLE_KEY
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`define ENABLE_LEDR
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`define ENABLE_PS2
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`define ENABLE_SW
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`define ENABLE_TD
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`define ENABLE_VGA
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module DE1_SOC_golden_top(
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      /* Enables ADC - 3.3V */
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        `ifdef ENABLE_ADC
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      output             ADC_CONVST,
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      output             ADC_DIN,
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      input              ADC_DOUT,
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      output             ADC_SCLK,
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        `endif
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       /* Enables AUD - 3.3V */
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        `ifdef ENABLE_AUD
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      input              AUD_ADCDAT,
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      inout              AUD_ADCLRCK,
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      inout              AUD_BCLK,
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      output             AUD_DACDAT,
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      inout              AUD_DACLRCK,
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      output             AUD_XCK,
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        `endif
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      /* Enables CLOCK2  */
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        `ifdef ENABLE_CLOCK2
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      input              CLOCK2_50,
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        `endif
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      /* Enables CLOCK3 */
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        `ifdef ENABLE_CLOCK3
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      input              CLOCK3_50,
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        `endif
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      /* Enables CLOCK4 */
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        `ifdef ENABLE_CLOCK4
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      input              CLOCK4_50,
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        `endif
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      /* Enables CLOCK */
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        `ifdef ENABLE_CLOCK
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      input              CLOCK_50,
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        `endif
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       /* Enables DRAM - 3.3V */
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        `ifdef ENABLE_DRAM
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      output      [12:0] DRAM_ADDR,
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      output      [1:0]  DRAM_BA,
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      output             DRAM_CAS_N,
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      output             DRAM_CKE,
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      output             DRAM_CLK,
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      output             DRAM_CS_N,
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      inout       [15:0] DRAM_DQ,
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      output             DRAM_LDQM,
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      output             DRAM_RAS_N,
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      output             DRAM_UDQM,
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      output             DRAM_WE_N,
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        `endif
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      /* Enables FAN - 3.3V */
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        `ifdef ENABLE_FAN
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      output             FAN_CTRL,
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        `endif
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      /* Enables FPGA - 3.3V */
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        `ifdef ENABLE_FPGA
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      output             FPGA_I2C_SCLK,
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      inout              FPGA_I2C_SDAT,
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        `endif
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      /* Enables GPIO - 3.3V */
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        `ifdef ENABLE_GPIO
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      inout     [35:0]         GPIO_0,
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      inout     [35:0]         GPIO_1,
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        `endif
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      /* Enables HEX - 3.3V */
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        `ifdef ENABLE_HEX
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      output      [6:0]  HEX0,
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      output      [6:0]  HEX1,
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      output      [6:0]  HEX2,
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      output      [6:0]  HEX3,
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      output      [6:0]  HEX4,
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      output      [6:0]  HEX5,
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        `endif
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        /* Enables HPS */
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        `ifdef ENABLE_HPS
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      inout              HPS_CONV_USB_N,
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      output      [14:0] HPS_DDR3_ADDR,
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      output      [2:0]  HPS_DDR3_BA,
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      output             HPS_DDR3_CAS_N,
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      output             HPS_DDR3_CKE,
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      output             HPS_DDR3_CK_N, //1.5V
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      output             HPS_DDR3_CK_P, //1.5V
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      output             HPS_DDR3_CS_N,
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      output      [3:0]  HPS_DDR3_DM,
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      inout       [31:0] HPS_DDR3_DQ,
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      inout       [3:0]  HPS_DDR3_DQS_N,
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      inout       [3:0]  HPS_DDR3_DQS_P,
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      output             HPS_DDR3_ODT,
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      output             HPS_DDR3_RAS_N,
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      output             HPS_DDR3_RESET_N,
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      input              HPS_DDR3_RZQ,
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      output             HPS_DDR3_WE_N,
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      output             HPS_ENET_GTX_CLK,
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      inout              HPS_ENET_INT_N,
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      output             HPS_ENET_MDC,
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      inout              HPS_ENET_MDIO,
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      input              HPS_ENET_RX_CLK,
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      input       [3:0]  HPS_ENET_RX_DATA,
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      input              HPS_ENET_RX_DV,
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      output      [3:0]  HPS_ENET_TX_DATA,
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      output             HPS_ENET_TX_EN,
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      inout       [3:0]  HPS_FLASH_DATA,
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      output             HPS_FLASH_DCLK,
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      output             HPS_FLASH_NCSO,
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      inout              HPS_GSENSOR_INT,
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      inout              HPS_I2C1_SCLK,
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      inout              HPS_I2C1_SDAT,
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      inout              HPS_I2C2_SCLK,
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      inout              HPS_I2C2_SDAT,
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      inout              HPS_I2C_CONTROL,
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      inout              HPS_KEY,
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      inout              HPS_LED,
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      inout              HPS_LTC_GPIO,
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      output             HPS_SD_CLK,
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      inout              HPS_SD_CMD,
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      inout       [3:0]  HPS_SD_DATA,
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      output             HPS_SPIM_CLK,
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      input              HPS_SPIM_MISO,
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      output             HPS_SPIM_MOSI,
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      inout              HPS_SPIM_SS,
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      input              HPS_UART_RX,
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      output             HPS_UART_TX,
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      input              HPS_USB_CLKOUT,
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      inout       [7:0]  HPS_USB_DATA,
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      input              HPS_USB_DIR,
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      input              HPS_USB_NXT,
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      output             HPS_USB_STP,
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`endif
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endmodule
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