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Subversion Repositories an-fpga-implementation-of-low-latency-noc-based-mpsoc

[/] [an-fpga-implementation-of-low-latency-noc-based-mpsoc/] [trunk/] [mpsoc/] [boards/] [Altera/] [DE5/] [DE5.v] - Blame information for rev 48

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Line No. Rev Author Line
1 48 alirezamon 
 
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//=======================================================
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//  This code is generated by Terasic System Builder
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//=======================================================
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module Top(
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        //////////// CLOCK //////////
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        OSC_50_B3B,
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        OSC_50_B3D,
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        OSC_50_B4A,
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        OSC_50_B4D,
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        OSC_50_B7A,
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        OSC_50_B7D,
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        OSC_50_B8A,
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        OSC_50_B8D,
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        //////////// LED x 10 //////////
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        LED,
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        LED_BRACKET,
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        LED_RJ45_L,
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        LED_RJ45_R,
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        //////////// BUTTON x 4 and CPU_RESET_n //////////
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        BUTTON,
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        CPU_RESET_n,
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        //////////// SWITCH x 4 //////////
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        SW,
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        //////////// 7-Segement //////////
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        HEX0_D,
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        HEX0_DP,
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        HEX1_D,
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        HEX1_DP,
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        //////////// Temperature //////////
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        TEMP_CLK,
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        TEMP_DATA,
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        TEMP_INT_n,
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        TEMP_OVERT_n,
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        //////////// Fan //////////
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        FAN_CTRL,
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        //////////// RS232 //////////
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        RS422_DE,
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        RS422_DIN,
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        RS422_DOUT,
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        RS422_RE_n,
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        RS422_TE,
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        //////////// Flash/MAX Address/Data Share Bus //////////
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        FSM_A,
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        FSM_D,
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        //////////// Flash Control //////////
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        FLASH_ADV_n,
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        FLASH_CE_n,
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        FLASH_CLK,
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        FLASH_OE_n,
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        FLASH_RDY_BSY_n,
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        FLASH_RESET_n,
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        FLASH_WE_n
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);
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//=======================================================
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//  PARAMETER declarations
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//=======================================================
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//=======================================================
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//  PORT declarations
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//=======================================================
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//////////// CLOCK //////////
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input                                   OSC_50_B3B;
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input                                   OSC_50_B3D;
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input                                   OSC_50_B4A;
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input                                   OSC_50_B4D;
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input                                   OSC_50_B7A;
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input                                   OSC_50_B7D;
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input                                   OSC_50_B8A;
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input                                   OSC_50_B8D;
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//////////// LED x 10 //////////
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output               [3:0]               LED;
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output               [3:0]               LED_BRACKET;
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output                                  LED_RJ45_L;
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output                                  LED_RJ45_R;
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//////////// BUTTON x 4 and CPU_RESET_n //////////
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input                [3:0]               BUTTON;
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input                                   CPU_RESET_n;
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//////////// SWITCH x 4 //////////
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input                [3:0]               SW;
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//////////// 7-Segement //////////
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output               [6:0]               HEX0_D;
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output                                  HEX0_DP;
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output               [6:0]               HEX1_D;
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output                                  HEX1_DP;
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//////////// Temperature //////////
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output                                  TEMP_CLK;
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inout                                   TEMP_DATA;
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input                                   TEMP_INT_n;
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input                                   TEMP_OVERT_n;
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//////////// Fan //////////
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inout                                   FAN_CTRL;
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//////////// RS232 //////////
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output                                  RS422_DE;
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input                                   RS422_DIN;
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output                                  RS422_DOUT;
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output                                  RS422_RE_n;
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output                                  RS422_TE;
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//////////// Flash/MAX Address/Data Share Bus //////////
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output              [26:0]               FSM_A;
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inout               [31:0]               FSM_D;
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//////////// Flash Control //////////
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output                                  FLASH_ADV_n;
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output               [1:0]               FLASH_CE_n;
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output                                  FLASH_CLK;
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output                                  FLASH_OE_n;
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input                [1:0]               FLASH_RDY_BSY_n;
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output                                  FLASH_RESET_n;
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output                                  FLASH_WE_n;
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//=======================================================
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//  REG/WIRE declarations
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//=======================================================
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//=======================================================
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//  Structural coding
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//=======================================================
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endmodule

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