Subversion Repositories an-fpga-implementation-of-low-latency-noc-based-mpsoc

All notable changes to this project will be documented in this file.

##[1.7.0] - 15-7-2017

## Added

-  Software compilation text-editor

-  Processing tile Diagrame Viewer

-  Modelsim/Verilator/QuartusII GUI compilation assist

-  Multi-channel DMA

## changed

-  New multi-channel DMA-based NI

##[1.6.0] - 6-3-2017

## Added

-  NoC GUI simulator (using Verilator)

##[1.5.2] - 22-2-2017

## changed

- fixed bug in wishbone bus

##[1.5.1] - 3-2-2017

## changed

- src_c/jtag_main.c:  variable length memory support is added.

- NoC emulator:  Jtag tabs are reduced to total of 3. A 64 core 2-VC NoC emulation is sucessfully tested on DE4 FPGA board.

- ssa: Now can work with fully adaptive routing.

##[1.5.0] - 13-10-2016

### Added

- static straight allocator (SSA) which accelerates packets traversing to the same direction to the NoC router.

- NoC emulator.

- Altor processor.

- Jtag_wb: allow access to the wishbone bus slave ports via Jtag.

- Jtag_main: A C code which allows host PC to have access to the jtag_wb.

## changed

- Memory IP cores are categorized into two IPs: Single and double port.

- The access via jtag_wb or Altera In-System Memory Content Editor is added as optional via parameter setting for single port memory.

##[1.0.0] - 27-1-2016

### added

- ProNoC: new version with GUI generator

- Interface generator

- IP generator

- Processing tile generator

- NoC based MCSoC generator