URL https://opencores.org/ocsvn/an-fpga-implementation-of-low-latency-noc-based-mpsoc/an-fpga-implementation-of-low-latency-noc-based-mpsoc/trunk

Subversion Repositories an-fpga-implementation-of-low-latency-noc-based-mpsoc

[/] [an-fpga-implementation-of-low-latency-noc-based-mpsoc/] [trunk/] [mpsoc/] [change.log] - Blame information for rev 41

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All notable changes to this project will be documented in this file.
 
##[1.8.1] - 30-7-2018
## Added
-  GUI for setting Linux variables
## changed
-  Support NoC Simulation for packet payload width larger than 32-bits and core number larger than 64.
 
 
##[1.8.0] - 16-5-2018
## Added
-  Support hard-built QoS/EoS support in NoC using weighted Round-Robin arbiter
-  Add real application task grah simulation support in NoC simulator
-  add new
-  Add two new (OpenRISC) softprocessors: Or1200 & Mor1kx
-  Add documentation for timer, ni-master, ni-slave, memory, and dma IP cores.
-  Add User manual file
-  Add USB blaster II support in JTAG controller
-  Add GUI for adding new Altera FPGA boards.
-  The simulator/ emulator now can provide additional simulation results
        (a) Average latency per average desired flit injection ratio
        (b) Average throughput per average desired flit injection ratio
        (c) send/received packets number for each router at different injection ratios
        (d) send/received worst-case delay for each router at different injection ratios
        (e) Simulation execution clock cycles
## changed
-  Fixed the bug in NoC that halts the simulation when B is defined as 2.
-  Support Burst Type Extension for Incrementing and Decrementing bursts in RAM controller
 
 
##[1.7.0] - 15-7-2017
## Added
-  Software compilation text-editor
-  Processing tile Diagram Viewer
-  Modelsim/Verilator/QuartusII GUI compilation assist
-  Multi-channel DMA
## changed
-  New multi-channel DMA-based NI
 
 
##[1.6.0] - 6-3-2017
## Added
-  NoC GUI simulator (using Verilator)
 
 
##[1.5.2] - 22-2-2017
## changed
- Fixed bug in wishbone bus
 
 
##[1.5.1] - 3-2-2017
## changed
- src_c/jtag_main.c:  variable length memory support is added.
- NoC emulator:  Jtag tabs are reduced to total of 3. A 64 core 2-VC NoC emulation is successfully tested on DE4 FPGA board.
- ssa: Now can work with fully adaptive routing.
 
 
##[1.5.0] - 13-10-2016
### Added
- static straight allocator (SSA) which accelerates packets traversing to the same direction to the NoC router.
- NoC emulator.
- Altor processor.
- Jtag_wb: allow access to the wishbone bus slave ports via Jtag.
- Jtag_main: A C code which allows host PC to have access to the jtag_wb.
## changed
- Memory IP cores are categorized into two IPs: Single and double port.
- The access via jtag_wb or Altera In-System Memory Content Editor is added as optional via parameter setting for single port memory.
 
 
##[1.0.0] - 27-1-2016
### added
- ProNoC: new version with GUI generator
- Interface generator
- IP generator
- Processing tile generator
- NoC based MCSoC generator

Line No.	Rev	Author	Line
1	25	alirezamon	`All notable changes to this project will be documented in this file.`
2
3	41	alirezamon	`##[1.8.1] - 30-7-2018`
4			`## Added`
5			`- GUI for setting Linux variables`
6			`## changed`
7			`- Support NoC Simulation for packet payload width larger than 32-bits and core number larger than 64.`
8
9
10	38	alirezamon	`##[1.8.0] - 16-5-2018`
11			`## Added`
12			`- Support hard-built QoS/EoS support in NoC using weighted Round-Robin arbiter`
13			`- Add real application task grah simulation support in NoC simulator`
14			`- add new`
15			`- Add two new (OpenRISC) softprocessors: Or1200 & Mor1kx`
16	41	alirezamon	`- Add documentation for timer, ni-master, ni-slave, memory, and dma IP cores.`
17	38	alirezamon	`- Add User manual file`
18	41	alirezamon	`- Add USB blaster II support in JTAG controller`
19	38	alirezamon	`- Add GUI for adding new Altera FPGA boards.`
20	41	alirezamon	`- The simulator/ emulator now can provide additional simulation results`
21	38	alirezamon	`(a) Average latency per average desired flit injection ratio`
22			`(b) Average throughput per average desired flit injection ratio`
23			`(c) send/received packets number for each router at different injection ratios`
24			`(d) send/received worst-case delay for each router at different injection ratios`
25			`(e) Simulation execution clock cycles`
26			`## changed`
27	41	alirezamon	`- Fixed the bug in NoC that halts the simulation when B is defined as 2.`
28	38	alirezamon	`- Support Burst Type Extension for Incrementing and Decrementing bursts in RAM controller`
29	28	alirezamon
30	38	alirezamon
31	34	alirezamon	`##[1.7.0] - 15-7-2017`
32			`## Added`
33			`- Software compilation text-editor`
34	41	alirezamon	`- Processing tile Diagram Viewer`
35	34	alirezamon	`- Modelsim/Verilator/QuartusII GUI compilation assist`
36			`- Multi-channel DMA`
37			`## changed`
38			`- New multi-channel DMA-based NI`
39
40
41	32	alirezamon	`##[1.6.0] - 6-3-2017`
42			`## Added`
43	34	alirezamon	`- NoC GUI simulator (using Verilator)`
44	32	alirezamon
45
46	31	alirezamon	`##[1.5.2] - 22-2-2017`
47			`## changed`
48	41	alirezamon	`- Fixed bug in wishbone bus`
49	31	alirezamon
50	41	alirezamon
51	28	alirezamon	`##[1.5.1] - 3-2-2017`
52			`## changed`
53			`- src_c/jtag_main.c: variable length memory support is added.`
54	41	alirezamon	`- NoC emulator: Jtag tabs are reduced to total of 3. A 64 core 2-VC NoC emulation is successfully tested on DE4 FPGA board.`
55	34	alirezamon	`- ssa: Now can work with fully adaptive routing.`
56	28	alirezamon
57
58	25	alirezamon	`##[1.5.0] - 13-10-2016`
59			`### Added`
60			`- static straight allocator (SSA) which accelerates packets traversing to the same direction to the NoC router.`
61			`- NoC emulator.`
62			`- Altor processor.`
63			`- Jtag_wb: allow access to the wishbone bus slave ports via Jtag.`
64			`- Jtag_main: A C code which allows host PC to have access to the jtag_wb.`
65			`## changed`
66			`- Memory IP cores are categorized into two IPs: Single and double port.`
67			`- The access via jtag_wb or Altera In-System Memory Content Editor is added as optional via parameter setting for single port memory.`
68
69
70			`##[1.0.0] - 27-1-2016`
71			`### added`
72			`- ProNoC: new version with GUI generator`
73			`- Interface generator`
74			`- IP generator`
75			`- Processing tile generator`
76			`- NoC based MCSoC generator`

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[/] [an-fpga-implementation-of-low-latency-noc-based-mpsoc/] [trunk/] [mpsoc/] [change.log] - Blame information for rev 41