URL https://opencores.org/ocsvn/an-fpga-implementation-of-low-latency-noc-based-mpsoc/an-fpga-implementation-of-low-latency-noc-based-mpsoc/trunk

Subversion Repositories an-fpga-implementation-of-low-latency-noc-based-mpsoc

[/] [an-fpga-implementation-of-low-latency-noc-based-mpsoc/] [trunk/] [mpsoc/] [change.log] - Blame information for rev 54

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All notable changes to this project will be documented in this file.
 
##[2.1.0] -26-03-2022
## added
- Multicast/Broadcast support
- SynFull traffic model is Integrated to NoC simulator
 
 
##[2.0.0] -15-10-2020
## added
- SMART, single cycle multi-hop bypass
- Selfloop support
- gui for UART terminal
- gui for a runtime memory controller
- Support Xilinx FPFAs
- Software Auto-generation using CAL language (CAL2C)
- Support multi threading in Verilator-based NoC simulator
- Integrated Netrace to NoC simulator
- add new topologies: Fmesh
- gui for custom NoC topology generation
- GTK3 support
 
## changed
- NoC codes are changing to systemVerilog. Now it uses struct for router connection interface.
 
 
##[1.9.1] -24-07-2019
## changed
- Some bugs are fixed in jtag interface.
 
##[1.9.0] -30-04-2019
## Added
- add single flit sized packet support
- add new topologies: Fattree, tree, concentrated mesh (Cmesh)
- Topology Diagram Viewer
 
## changed
- The endpoint and router addresses format has been changed to support different topologies.
 
 
 
##[1.8.2] -13-12-2018
## Added
- add latency standard deviation to simulation results graphs
- add Simple message passing demo on 4×4 MPSoC
- add some error flags to NI
## changed
- fix some bugs in NI
- Enable Verilator simulation on MPSoC
 
##[1.8.1] - 30-7-2018
## Added
-  GUI for setting Linux variables
## changed
-  Support NoC Simulation for packet payload width larger than 32-bits and core number larger than 64.
 
 
##[1.8.1] - 30-7-2018
## Added
-  GUI for setting Linux variables
## changed
-  Support NoC Simulation for packet payload width larger than 32-bits and core number larger than 64.
 
 
##[1.8.0] - 16-5-2018
## Added
-  Support hard-built QoS/EoS support in NoC using weighted Round-Robin arbiter
-  Add real application task grah simulation support in NoC simulator
-  add new
-  Add two new (OpenRISC) softprocessors: Or1200 & Mor1kx
-  Add documentation for timer, ni-master, ni-slave, memory, and dma IP cores.
-  Add User manual file
-  Add USB blaster II support in JTAG controller
-  Add GUI for adding new Altera FPGA boards.
-  The simulator/ emulator now can provide additional simulation results
        (a) Average latency per average desired flit injection ratio
        (b) Average throughput per average desired flit injection ratio
        (c) send/received packets number for each router at different injection ratios
        (d) send/received worst-case delay for each router at different injection ratios
        (e) Simulation execution clock cycles
## changed
-  Fixed the bug in NoC that halts the simulation when B is defined as 2.
-  Support Burst Type Extension for Incrementing and Decrementing bursts in RAM controller
 
 
##[1.7.0] - 15-7-2017
## Added
-  Software compilation text-editor
-  Processing tile Diagram Viewer
-  Modelsim/Verilator/QuartusII GUI compilation assist
-  Multi-chanel DMA
## changed
-  New multi-chanel DMA-based NI
 
 
##[1.6.0] - 6-3-2017
## Added
-  NoC GUI simulator (using Verilator)
 
 
##[1.5.2] - 22-2-2017
## changed
- Fixed bug in wishbone bus
 
 
##[1.5.1] - 3-2-2017
## changed
- src_c/jtag_main.c:  variable length memory support is added.
- NoC emulator:  Jtag tabs are reduced to total of 3. A 64 core 2-VC NoC emulation is successfully tested on DE4 FPGA board.
- ssa: Now can work with fully adaptive routing.
 
 
##[1.5.0] - 13-10-2016
### Added
- static straight allocator (SSA) which accelerates packets traversing to the same direction to the NoC router.
- NoC emulator.
- Jtag_wb: allow access to the wishbone bus slave ports via Jtag.
- Jtag_main: A C code which allows host PC to have access to the jtag_wb.
## changed
- Memory IP cores are categorized into two IPs: Single and double port.
- The access via jtag_wb or Altera In-System Memory Content Editor is added as optional via parameter setting for single port memory.
 
 
##[1.0.0] - 27-1-2016
### added
- ProNoC: new version with GUI generator
- Interface generator
- IP generator
- Processing tile generator
- NoC based MCSoC generator

Line No.	Rev	Author	Line
1	25	alirezamon	`All notable changes to this project will be documented in this file.`
2	54	alirezamon
3			`##[2.1.0] -26-03-2022`
4			`## added`
5			`- Multicast/Broadcast support`
6			`- SynFull traffic model is Integrated to NoC simulator`
7
8
9	48	alirezamon	`##[2.0.0] -15-10-2020`
10			`## added`
11	54	alirezamon	`- SMART, single cycle multi-hop bypass`
12			`- Selfloop support`
13	48	alirezamon	`- gui for UART terminal`
14	54	alirezamon	`- gui for a runtime memory controller`
15			`- Support Xilinx FPFAs`
16	48	alirezamon	`- Software Auto-generation using CAL language (CAL2C)`
17	54	alirezamon	`- Support multi threading in Verilator-based NoC simulator`
18			`- Integrated Netrace to NoC simulator`
19	48	alirezamon	`- add new topologies: Fmesh`
20	54	alirezamon	`- gui for custom NoC topology generation`
21	48	alirezamon	`- GTK3 support`
22	25	alirezamon
23	48	alirezamon	`## changed`
24			`- NoC codes are changing to systemVerilog. Now it uses struct for router connection interface.`
25
26
27	45	alirezamon	`##[1.9.1] -24-07-2019`
28			`## changed`
29	48	alirezamon	`- Some bugs are fixed in jtag interface.`
30	43	alirezamon
31			`##[1.9.0] -30-04-2019`
32			`## Added`
33			`- add single flit sized packet support`
34			`- add new topologies: Fattree, tree, concentrated mesh (Cmesh)`
35			`- Topology Diagram Viewer`
36
37			`## changed`
38			`- The endpoint and router addresses format has been changed to support different topologies.`
39
40
41
42	42	alirezamon	`##[1.8.2] -13-12-2018`
43			`## Added`
44			`- add latency standard deviation to simulation results graphs`
45			`- add Simple message passing demo on 4×4 MPSoC`
46			`- add some error flags to NI`
47			`## changed`
48			`- fix some bugs in NI`
49			`- Enable Verilator simulation on MPSoC`
50
51	43	alirezamon	`##[1.8.1] - 30-7-2018`
52			`## Added`
53			`- GUI for setting Linux variables`
54			`## changed`
55			`- Support NoC Simulation for packet payload width larger than 32-bits and core number larger than 64.`
56	42	alirezamon
57	43	alirezamon
58	41	alirezamon	`##[1.8.1] - 30-7-2018`
59			`## Added`
60			`- GUI for setting Linux variables`
61			`## changed`
62			`- Support NoC Simulation for packet payload width larger than 32-bits and core number larger than 64.`
63
64
65	38	alirezamon	`##[1.8.0] - 16-5-2018`
66			`## Added`
67			`- Support hard-built QoS/EoS support in NoC using weighted Round-Robin arbiter`
68			`- Add real application task grah simulation support in NoC simulator`
69			`- add new`
70			`- Add two new (OpenRISC) softprocessors: Or1200 & Mor1kx`
71	41	alirezamon	`- Add documentation for timer, ni-master, ni-slave, memory, and dma IP cores.`
72	38	alirezamon	`- Add User manual file`
73	41	alirezamon	`- Add USB blaster II support in JTAG controller`
74	38	alirezamon	`- Add GUI for adding new Altera FPGA boards.`
75	41	alirezamon	`- The simulator/ emulator now can provide additional simulation results`
76	38	alirezamon	`(a) Average latency per average desired flit injection ratio`
77			`(b) Average throughput per average desired flit injection ratio`
78			`(c) send/received packets number for each router at different injection ratios`
79			`(d) send/received worst-case delay for each router at different injection ratios`
80			`(e) Simulation execution clock cycles`
81			`## changed`
82	41	alirezamon	`- Fixed the bug in NoC that halts the simulation when B is defined as 2.`
83	38	alirezamon	`- Support Burst Type Extension for Incrementing and Decrementing bursts in RAM controller`
84	28	alirezamon
85	38	alirezamon
86	34	alirezamon	`##[1.7.0] - 15-7-2017`
87			`## Added`
88			`- Software compilation text-editor`
89	41	alirezamon	`- Processing tile Diagram Viewer`
90	34	alirezamon	`- Modelsim/Verilator/QuartusII GUI compilation assist`
91	48	alirezamon	`- Multi-chanel DMA`
92	34	alirezamon	`## changed`
93	48	alirezamon	`- New multi-chanel DMA-based NI`
94	34	alirezamon
95
96	32	alirezamon	`##[1.6.0] - 6-3-2017`
97			`## Added`
98	34	alirezamon	`- NoC GUI simulator (using Verilator)`
99	32	alirezamon
100
101	31	alirezamon	`##[1.5.2] - 22-2-2017`
102			`## changed`
103	41	alirezamon	`- Fixed bug in wishbone bus`
104	31	alirezamon
105	41	alirezamon
106	28	alirezamon	`##[1.5.1] - 3-2-2017`
107			`## changed`
108			`- src_c/jtag_main.c: variable length memory support is added.`
109	41	alirezamon	`- NoC emulator: Jtag tabs are reduced to total of 3. A 64 core 2-VC NoC emulation is successfully tested on DE4 FPGA board.`
110	34	alirezamon	`- ssa: Now can work with fully adaptive routing.`
111	28	alirezamon
112
113	25	alirezamon	`##[1.5.0] - 13-10-2016`
114			`### Added`
115			`- static straight allocator (SSA) which accelerates packets traversing to the same direction to the NoC router.`
116			`- NoC emulator.`
117			`- Jtag_wb: allow access to the wishbone bus slave ports via Jtag.`
118			`- Jtag_main: A C code which allows host PC to have access to the jtag_wb.`
119			`## changed`
120			`- Memory IP cores are categorized into two IPs: Single and double port.`
121			`- The access via jtag_wb or Altera In-System Memory Content Editor is added as optional via parameter setting for single port memory.`
122
123
124			`##[1.0.0] - 27-1-2016`
125			`### added`
126			`- ProNoC: new version with GUI generator`
127			`- Interface generator`
128			`- IP generator`
129			`- Processing tile generator`
130			`- NoC based MCSoC generator`

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Subversion Repositories an-fpga-implementation-of-low-latency-noc-based-mpsoc

[/] [an-fpga-implementation-of-low-latency-noc-based-mpsoc/] [trunk/] [mpsoc/] [change.log] - Blame information for rev 54