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Subversion Repositories an-fpga-implementation-of-low-latency-noc-based-mpsoc

[/] [an-fpga-implementation-of-low-latency-noc-based-mpsoc/] [trunk/] [mpsoc/] [perl_gui/] [lib/] [emulate/] [tt.EML] - Blame information for rev 48

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Line No. Rev Author Line
1 48 alirezamon 
#######################################################################
2 
##      File: tt.EML
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##
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##      Copyright (C) 2014-2019  Alireza Monemi
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##
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##      This file is part of ProNoC 1.9.1
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##
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##      WARNING: THIS IS AN AUTO-GENERATED FILE. CHANGES TO IT
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##      MAY CAUSE UNEXPECTED BEHAVIOR.
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################################################################################
11 
 
12 
$emulate = bless( {
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                    'samples' => undef,
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                    'compile_pin' => {
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                                       'done_led' => 'LED',
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                                       'reset' => 'FPGA_CLK1_50',
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                                       'jtag_reset_led' => 'LED',
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                                       'noc_reset_led' => 'LED',
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                                       'clk' => 'KEY'
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                                     },
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                    'noc_param' => {
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                                     'AVC_ATOMIC_EN' => 0,
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                                     'LB' => '4',
24 
                                     'SSA_EN' => '"NO"',
25 
                                     'DEBUG_EN' => '0',
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                                     'B' => '4',
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                                     'COMBINATION_TYPE' => '"COMB_NONSPEC"',
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                                     'VC_REALLOCATION_TYPE' => '"NONATOMIC"',
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                                     'T2' => '2',
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                                     'WEIGHTw' => '4',
31 
                                     'ESCAP_VC_MASK' => '2\'b01',
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                                     'C' => 0,
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                                     'SELF_LOOP_EN' => '"NO"',
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                                     'SWA_ARBITER_TYPE' => '"RRA"',
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                                     'MUX_TYPE' => '"BINARY"',
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                                     'V' => '2',
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                                     'BYTE_EN' => 0,
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                                     'T3' => '1',
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                                     'TOPOLOGY' => '"MESH"',
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                                     'PCK_TYPE' => '"MULTI_FLIT"',
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                                     'Fpay' => '32',
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                                     'ADD_PIPREG_AFTER_CROSSBAR' => '1\'b0',
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                                     'FIRST_ARBITER_EXT_P_EN' => 1,
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                                     'MIN_PCK_SIZE' => '2',
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                                     'ROUTE_NAME' => '"XY"',
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                                     'T1' => '2',
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                                     'CONGESTION_INDEX' => 3,
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                                     'SMART_MAX' => '0'
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                                   },
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                    'compile' => {
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                                   'quartus bin' => '/home/alireza/intelFPGA_lite/questa/questasim/bin/',
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                                   'type' => 'QuartusII',
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                                   'compilers' => 'QuartusII',
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                                   'board' => 'DE10_Nano_VB2'
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                                 },
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                    'compile_pin_range_hsb' => {},
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                    'process_notebook' => {
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                                            'currentpage' => 1
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                                          },
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                    'P3-_param' => {
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                                     'X_Title' => 'Desired Avg. Injected Load Per Router (flits/clock (%))',
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                                     'legend_placement' => 'BL',
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                                     'Y_MIN' => 0,
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                                     'X_MAX' => 100,
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                                     'label_font' => 'MediumBold',
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                                     'legend_font' => 'MediumBold',
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                                     'X_MIN' => 0,
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                                     'x_axis_font' => 'MediumBold',
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                                     'LINEw' => 3,
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                                     'Y_Title' => 'Total Emulation Time (clk)'
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                                   },
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                    'setting' => {
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                                   'show_adv_setting' => 0,
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                                   'soc_path' => 'lib/soc',
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                                   'show_noc_setting' => 1,
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                                   'show_tile_setting' => 0
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                                 },
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                    'noc_setting_gui' => {
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                                           'ha' => '0',
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                                           'va' => '0'
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                                         },
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                    'P0Latency_param' => {
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                                           'X_MIN' => 0,
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                                           'x_axis_font' => 'MediumBold',
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                                           'LINEw' => 3,
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                                           'Y_Title' => 'Avg. Latency (clock)',
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                                           'legend_placement' => 'BL',
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                                           'Y_MIN' => 0,
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                                           'X_MAX' => 100,
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                                           'label_font' => 'MediumBold',
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                                           'legend_font' => 'MediumBold',
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                                           'X_Title' => 'Desired Avg. Injected Load Per Router (flits/clock (%))'
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                                         },
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                    'P3' => {
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                              'active' => '-'
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                            },
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                    'noc_type' => {
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                                    'ROUTER_TYPE' => '"VC_BASED"'
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                                  },
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                    'P1Received_param' => {
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                                            'X_Title' => 'Core ID',
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                                            'legend_font' => 'MediumBold',
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                                            'label_font' => 'MediumBold',
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                                            'X_MAX' => 100,
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                                            'legend_placement' => 'BL',
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                                            'Y_MIN' => 0,
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                                            'X_MIN' => 0,
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                                            'Y_Title' => 'Received Packets Per Router',
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                                            'x_axis_font' => 'MediumBold',
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                                            'LINEw' => 3
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                                          },
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                    'P1' => {
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                              'active' => 'Received'
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                            },
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                    'graph_save' => {
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                                      'save_all_result' => 0
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                                    },
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                    'status' => 'ideal',
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                    'P2Received_param' => {
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                                            'X_Title' => 'Core ID',
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                                            'X_MIN' => 0,
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                                            'LINEw' => 3,
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                                            'x_axis_font' => 'MediumBold',
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                                            'Y_Title' => 'Worst-Case Delay (clk)',
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                                            'legend_placement' => 'BL',
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                                            'Y_MIN' => 0,
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                                            'legend_font' => 'MediumBold',
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                                            'label_font' => 'MediumBold',
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                                            'X_MAX' => 100
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                                          },
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                    'P0Latency' => {
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                                     'type' => '2D_line'
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                                   },
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                    'P0' => {
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                              'active' => 'Latency'
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                            },
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                    'P2Received' => {
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                                      'type' => '3D_bar',
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                                      'dimension' => '3D'
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                                    },
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                    'P3-' => {
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                               'type' => '2D_line'
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                             },
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                    'compile_pin_pos' => {
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                                           'done_led' => [
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                                                           3,
147 
 
148 
                                                         ],
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                                           'reset' => [
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                                                        4,
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152 
                                                      ],
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                                           'noc_reset_led' => [
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                                                                3,
155 
 
156 
                                                              ],
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                                           'jtag_reset_led' => [
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                                                                 3,
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160 
                                                               ],
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                                           'clk' => [
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                                                      6,
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164 
                                                    ]
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                                         },
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                    'no_name' => {},
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                    'emulation_column' => {
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                                            'va' => '0',
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                                            'ha' => '0'
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                                          },
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                    'file_name' => undef,
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                    'chart_notebook' => {},
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                    'gui_status' => {
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                                      'timeout' => 0,
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                                      'status' => 'ideal'
176 
                                    },
177 
                    'compile_pin_range_lsb' => {
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                                                 'noc_reset_led' => 0,
179 
                                                 'jtag_reset_led' => 0,
180 
                                                 'clk' => 0,
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                                                 'done_led' => 0
182 
                                               },
183 
                    'compile_assign_type' => {
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                                               'clk' => 'Direct',
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                                               'reset' => 'Direct'
186 
                                             },
187 
                    'fpga_param' => {
188 
                                      'TIMSTMP_FIFO_NUM' => 16,
189 
                                      'SAVE_NAME' => 'emulate1',
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                                      'SOF_DIR' => '/home/alireza/work/git/hca_git/mpsoc_work/emulate'
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                                    },
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                    'parameters_order' => {
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                                            'fpga_param' => [
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                                                              'TIMSTMP_FIFO_NUM',
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                                                              'SAVE_NAME',
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                                                              'SOF_DIR'
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                                                            ],
198 
                                            'noc_type' => [
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                                                            'ROUTER_TYPE'
200 
                                                          ],
201 
                                            'noc_param' => [
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                                                             'TOPOLOGY',
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                                                             'T1',
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                                                             'T2',
205 
                                                             'T3',
206 
                                                             'V',
207 
                                                             'B',
208 
                                                             'LB',
209 
                                                             'Fpay',
210 
                                                             'ROUTE_NAME',
211 
                                                             'PCK_TYPE',
212 
                                                             'MIN_PCK_SIZE',
213 
                                                             'BYTE_EN',
214 
                                                             'SSA_EN',
215 
                                                             'SMART_MAX',
216 
                                                             'CONGESTION_INDEX',
217 
                                                             'ESCAP_VC_MASK',
218 
                                                             'VC_REALLOCATION_TYPE',
219 
                                                             'COMBINATION_TYPE',
220 
                                                             'MUX_TYPE',
221 
                                                             'C',
222 
                                                             'DEBUG_EN',
223 
                                                             'ADD_PIPREG_AFTER_CROSSBAR',
224 
                                                             'FIRST_ARBITER_EXT_P_EN',
225 
                                                             'SWA_ARBITER_TYPE',
226 
                                                             'WEIGHTw',
227 
                                                             'SELF_LOOP_EN',
228 
                                                             'AVC_ATOMIC_EN'
229 
                                                           ]
230 
                                          },
231 
                    'P1Received' => {
232 
                                      'dimension' => '3D',
233 
                                      'type' => '3D_bar'
234 
                                    },
235 
                    'emulate_name' => 'tt',
236 
                    'P2' => {
237 
                              'active' => 'Received'
238 
                            }
239 
                  }, 'emulator' );

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