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alirezamon |
#######################################################################
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## File: ethmac_100.IP
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##
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## Copyright (C) 2014-2016 Alireza Monemi
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##
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## This file is part of ProNoC 1.7.0
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##
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## WARNING: THIS IS AN AUTO-GENERATED FILE. CHANGES TO IT
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## MAY CAUSE UNEXPECTED BEHAIVOR.
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################################################################################
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$ethtop = bless( {
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'version' => 1,
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'module_name' => 'ethtop',
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'unused' => {
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'plug:wb_master[0]' => [
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'bte_o',
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'rty_i',
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'cti_o',
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'tag_o'
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],
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'plug:wb_slave[0]' => [
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'cti_i',
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'bte_i',
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'tag_i',
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'rty_o'
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]
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},
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'plugs' => {
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'wb_master' => {
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'wb_master' => {},
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'value' => 1,
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'type' => 'num',
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'0' => {
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'name' => 'wb_master'
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}
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},
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'wb_slave' => {
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'value' => 1,
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'wb_slave' => {},
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'type' => 'num',
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'0' => {
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'addr' => '0x9200_0000 0x92ff_ffff Ethernet Controller',
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'width' => 11,
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'name' => 'wb_slave'
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}
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},
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'clk' => {
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'value' => 1,
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'clk' => {},
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'type' => 'num',
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'0' => {
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'name' => 'clk'
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}
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},
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'interrupt_peripheral' => {
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'value' => 1,
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'interrupt_peripheral' => {},
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'0' => {
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'name' => 'interrupt_peripheral'
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},
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'type' => 'num'
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},
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'reset' => {
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'value' => 1,
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'0' => {
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'name' => 'reset'
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},
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'type' => 'num',
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'reset' => {}
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}
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},
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'custom_file_num' => 1,
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'ports' => {
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'wb_clk_i' => {
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'range' => '',
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'intfc_name' => 'plug:clk[0]',
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'intfc_port' => 'clk_i',
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'type' => 'input'
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},
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'm_wb_adr_o' => {
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'intfc_port' => 'adr_o',
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'type' => 'output',
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'range' => '31:0',
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'intfc_name' => 'plug:wb_master[0]'
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},
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'mtxd_pad_o' => {
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'intfc_port' => 'IO',
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'type' => 'output',
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'range' => '3:0',
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'intfc_name' => 'IO'
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},
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'int_o' => {
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'intfc_port' => 'int_o',
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'type' => 'output',
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'range' => '',
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'intfc_name' => 'plug:interrupt_peripheral[0]'
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},
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'mdc_pad_o' => {
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'intfc_port' => 'IO',
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'type' => 'output',
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'range' => '',
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'intfc_name' => 'IO'
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},
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'wb_ack_o' => {
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'intfc_port' => 'ack_o',
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'type' => 'output',
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'range' => '',
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'intfc_name' => 'plug:wb_slave[0]'
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},
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'mtxen_pad_o' => {
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'intfc_port' => 'IO',
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'type' => 'output',
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'range' => '',
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'intfc_name' => 'IO'
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},
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'wb_dat_i' => {
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'intfc_port' => 'dat_i',
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'type' => 'input',
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'range' => '31:0',
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'intfc_name' => 'plug:wb_slave[0]'
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},
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'wb_stb_i' => {
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'type' => 'input',
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'intfc_port' => 'stb_i',
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'intfc_name' => 'plug:wb_slave[0]',
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'range' => ''
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},
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'mcrs_pad_i' => {
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'intfc_name' => 'IO',
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'range' => '',
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'type' => 'input',
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'intfc_port' => 'IO'
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},
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'wb_rst_i' => {
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'type' => 'input',
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'intfc_port' => 'reset_i',
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'intfc_name' => 'plug:reset[0]',
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'range' => ''
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},
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'm_wb_dat_i' => {
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'range' => '31:0',
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'intfc_name' => 'plug:wb_master[0]',
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'intfc_port' => 'dat_i',
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'type' => 'input'
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},
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'md_pad_o' => {
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'range' => '',
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'intfc_name' => 'IO',
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'intfc_port' => 'IO',
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'type' => 'output'
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},
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'mcoll_pad_i' => {
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'range' => '',
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'intfc_name' => 'IO',
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'intfc_port' => 'IO',
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'type' => 'input'
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},
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'm_wb_stb_o' => {
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'range' => '',
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'intfc_name' => 'plug:wb_master[0]',
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'intfc_port' => 'stb_o',
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'type' => 'output'
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},
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'm_wb_err_i' => {
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'type' => 'input',
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'intfc_port' => 'err_i',
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'intfc_name' => 'plug:wb_master[0]',
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'range' => ''
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},
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'm_wb_cyc_o' => {
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'intfc_port' => 'cyc_o',
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'type' => 'output',
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'range' => '',
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'intfc_name' => 'plug:wb_master[0]'
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},
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'mtx_clk_pad_i' => {
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'intfc_port' => 'IO',
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'type' => 'input',
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'range' => '',
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'intfc_name' => 'IO'
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},
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'wb_err_o' => {
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'intfc_port' => 'err_o',
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'type' => 'output',
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'range' => '',
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'intfc_name' => 'plug:wb_slave[0]'
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},
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'wb_cyc_i' => {
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'intfc_name' => 'plug:wb_slave[0]',
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'range' => '',
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'type' => 'input',
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'intfc_port' => 'cyc_i'
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},
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'm_wb_dat_o' => {
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'range' => '31:0',
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'intfc_name' => 'plug:wb_master[0]',
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'intfc_port' => 'dat_o',
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'type' => 'output'
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},
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'mrxdv_pad_i' => {
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'intfc_port' => 'IO',
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'type' => 'input',
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'range' => '',
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'intfc_name' => 'IO'
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},
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'md_padoe_o' => {
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'intfc_name' => 'IO',
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'range' => '',
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'type' => 'output',
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'intfc_port' => 'IO'
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},
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'wb_dat_o' => {
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'range' => '31:0',
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'intfc_name' => 'plug:wb_slave[0]',
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'intfc_port' => 'dat_o',
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'type' => 'output'
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},
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'm_wb_ack_i' => {
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'range' => '',
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'intfc_name' => 'plug:wb_master[0]',
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'intfc_port' => 'ack_i',
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'type' => 'input'
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},
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'm_wb_we_o' => {
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'intfc_name' => 'plug:wb_master[0]',
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'range' => '',
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'type' => 'output',
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'intfc_port' => 'we_o'
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},
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'mrx_clk_pad_i' => {
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'intfc_port' => 'IO',
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'type' => 'input',
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'range' => '',
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'intfc_name' => 'IO'
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},
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'wb_sel_i' => {
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'intfc_name' => 'plug:wb_slave[0]',
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'range' => '3:0',
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'type' => 'input',
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'intfc_port' => 'sel_i'
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},
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'm_wb_sel_o' => {
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'type' => 'output',
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'intfc_port' => 'sel_o',
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'intfc_name' => 'plug:wb_master[0]',
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'range' => '3:0'
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},
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'mtxerr_pad_o' => {
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'range' => '',
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'intfc_name' => 'IO',
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'intfc_port' => 'IO',
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'type' => 'output'
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},
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'wb_we_i' => {
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'intfc_name' => 'plug:wb_slave[0]',
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'range' => '',
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'type' => 'input',
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'intfc_port' => 'we_i'
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},
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'mrxerr_pad_i' => {
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'intfc_name' => 'IO',
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'range' => '',
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'type' => 'input',
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'intfc_port' => 'IO'
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},
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'wb_adr_i' => {
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'type' => 'input',
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'intfc_port' => 'adr_i',
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'intfc_name' => 'plug:wb_slave[0]',
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'range' => '9:0'
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},
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'mrxd_pad_i' => {
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'type' => 'input',
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'intfc_port' => 'IO',
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'intfc_name' => 'IO',
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'range' => '3:0'
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},
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'md_pad_i' => {
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'intfc_name' => 'IO',
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| 281 |
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'range' => '',
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'type' => 'input',
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'intfc_port' => 'IO'
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}
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},
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'system_h' => '
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void ${IP}_init();
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void ${IP}_interrupt();
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void ${IP}_recv_ack(void);
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int ${IP}_send(int length); //return (-1) or length (still processing previous) or asserted
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| 293 |
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#define ${IP}_BASE_ADDR $BASE
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#define ${IP}_MODER (*((volatile unsigned int *) (${IP}_BASE_ADDR+0x00 )))
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| 295 |
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#define ${IP}_INT_SOURCE (*((volatile unsigned int *) (${IP}_BASE_ADDR+0x04 )))
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| 296 |
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#define ${IP}_INT_MASK (*((volatile unsigned int *) (${IP}_BASE_ADDR+0x08 )))
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| 297 |
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#define ${IP}_IPGT (*((volatile unsigned int *) (${IP}_BASE_ADDR+0x0C )))
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| 298 |
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#define ${IP}_IPGR1 (*((volatile unsigned int *) (${IP}_BASE_ADDR+0x10 )))
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| 299 |
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#define ${IP}_IPGR2 (*((volatile unsigned int *) (${IP}_BASE_ADDR+0x14 )))
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| 300 |
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#define ${IP}_PACKETLEN (*((volatile unsigned int *) (${IP}_BASE_ADDR+0x18 )))
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| 301 |
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#define ${IP}_COLLCONF (*((volatile unsigned int *) (${IP}_BASE_ADDR+0x1C )))
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| 302 |
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#define ${IP}_TX_BD_NUM (*((volatile unsigned int *) (${IP}_BASE_ADDR+0x20 )))
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| 303 |
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#define ${IP}_CTRLMODER (*((volatile unsigned int *) (${IP}_BASE_ADDR+0x24 )))
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| 304 |
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#define ${IP}_MIIMODER (*((volatile unsigned int *) (${IP}_BASE_ADDR+0x28 )))
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| 305 |
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#define ${IP}_MIICOMMAND (*((volatile unsigned int *) (${IP}_BASE_ADDR+0x2C )))
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| 306 |
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#define ${IP}_MIIADDR (*((volatile unsigned int *) (${IP}_BASE_ADDR+0x30 )))
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| 307 |
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#define ${IP}_MIITX_DATA (*((volatile unsigned int *) (${IP}_BASE_ADDR+0x34 )))
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| 308 |
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#define ${IP}_MIIRX_DATA (*((volatile unsigned int *) (${IP}_BASE_ADDR+0x38 )))
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| 309 |
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#define ${IP}_MIISTATUS (*((volatile unsigned int *) (${IP}_BASE_ADDR+0x3C )))
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| 310 |
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#define ${IP}_MAC_ADDR0 (*((volatile unsigned int *) (${IP}_BASE_ADDR+0x40 )))
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| 311 |
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#define ${IP}_MAC_ADDR1 (*((volatile unsigned int *) (${IP}_BASE_ADDR+0x44 )))
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| 312 |
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#define ${IP}_HASH0_ADR (*((volatile unsigned int *) (${IP}_BASE_ADDR+0x48 )))
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| 313 |
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#define ${IP}_HASH1_ADR (*((volatile unsigned int *) (${IP}_BASE_ADDR+0x4C )))
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| 314 |
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#define ${IP}_TXCTRL (*((volatile unsigned int *) (${IP}_BASE_ADDR+0x50 )))
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| 315 |
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#define ${IP}_TXBD0H (*((volatile unsigned int *) (${IP}_BASE_ADDR+0x404 )))
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| 316 |
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#define ${IP}_TXBD0L (*((volatile unsigned int *) (${IP}_BASE_ADDR+0x400 )))
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| 317 |
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#define ${IP}_RXBD0H (*((volatile unsigned int *) (${IP}_BASE_ADDR+0x604 ))) //this depends on TX_BD_NUM but this is the standard value
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| 318 |
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#define ${IP}_RXBD0L (*((volatile unsigned int *) (${IP}_BASE_ADDR+0x600 ))) //this depends on TX_BD_NUM but this is the standard value
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| 319 |
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| 320 |
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| 321 |
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#include "${IP}.h"',
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| 322 |
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'ip_name' => 'ethmac_100',
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| 323 |
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|
'file_name' => '/home/alireza/Mywork/mpsoc/src_peripheral/ethmac/ethtop.v',
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| 324 |
|
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'ports_order' => [
|
| 325 |
|
|
'wb_clk_i',
|
| 326 |
|
|
'wb_rst_i',
|
| 327 |
|
|
'wb_dat_i',
|
| 328 |
|
|
'wb_dat_o',
|
| 329 |
|
|
'wb_adr_i',
|
| 330 |
|
|
'wb_sel_i',
|
| 331 |
|
|
'wb_we_i',
|
| 332 |
|
|
'wb_cyc_i',
|
| 333 |
|
|
'wb_stb_i',
|
| 334 |
|
|
'wb_ack_o',
|
| 335 |
|
|
'wb_err_o',
|
| 336 |
|
|
'm_wb_adr_o',
|
| 337 |
|
|
'm_wb_sel_o',
|
| 338 |
|
|
'm_wb_we_o',
|
| 339 |
|
|
'm_wb_dat_o',
|
| 340 |
|
|
'm_wb_dat_i',
|
| 341 |
|
|
'm_wb_cyc_o',
|
| 342 |
|
|
'm_wb_stb_o',
|
| 343 |
|
|
'm_wb_ack_i',
|
| 344 |
|
|
'm_wb_err_i',
|
| 345 |
|
|
'mtx_clk_pad_i',
|
| 346 |
|
|
'mtxd_pad_o',
|
| 347 |
|
|
'mtxen_pad_o',
|
| 348 |
|
|
'mtxerr_pad_o',
|
| 349 |
|
|
'mrx_clk_pad_i',
|
| 350 |
|
|
'mrxd_pad_i',
|
| 351 |
|
|
'mrxdv_pad_i',
|
| 352 |
|
|
'mrxerr_pad_i',
|
| 353 |
|
|
'mcoll_pad_i',
|
| 354 |
|
|
'mcrs_pad_i',
|
| 355 |
|
|
'mdc_pad_o',
|
| 356 |
|
|
'md_pad_i',
|
| 357 |
|
|
'md_pad_o',
|
| 358 |
|
|
'md_padoe_o',
|
| 359 |
|
|
'int_o'
|
| 360 |
|
|
],
|
| 361 |
|
|
'hdl_files' => [
|
| 362 |
|
|
'/mpsoc/src_peripheral/ethmac/rtl/eth_clockgen.v',
|
| 363 |
|
|
'/mpsoc/src_peripheral/ethmac/rtl/eth_cop.v',
|
| 364 |
|
|
'/mpsoc/src_peripheral/ethmac/rtl/eth_crc.v',
|
| 365 |
|
|
'/mpsoc/src_peripheral/ethmac/rtl/eth_fifo.v',
|
| 366 |
|
|
'/mpsoc/src_peripheral/ethmac/rtl/ethmac.v',
|
| 367 |
|
|
'/mpsoc/src_peripheral/ethmac/rtl/eth_maccontrol.v',
|
| 368 |
|
|
'/mpsoc/src_peripheral/ethmac/rtl/ethmac_defines.v',
|
| 369 |
|
|
'/mpsoc/src_peripheral/ethmac/rtl/eth_macstatus.v',
|
| 370 |
|
|
'/mpsoc/src_peripheral/ethmac/rtl/eth_miim.v',
|
| 371 |
|
|
'/mpsoc/src_peripheral/ethmac/rtl/eth_outputcontrol.v',
|
| 372 |
|
|
'/mpsoc/src_peripheral/ethmac/rtl/eth_random.v',
|
| 373 |
|
|
'/mpsoc/src_peripheral/ethmac/rtl/eth_receivecontrol.v',
|
| 374 |
|
|
'/mpsoc/src_peripheral/ethmac/rtl/eth_register.v',
|
| 375 |
|
|
'/mpsoc/src_peripheral/ethmac/rtl/eth_registers.v',
|
| 376 |
|
|
'/mpsoc/src_peripheral/ethmac/rtl/eth_rxaddrcheck.v',
|
| 377 |
|
|
'/mpsoc/src_peripheral/ethmac/rtl/eth_rxcounters.v',
|
| 378 |
|
|
'/mpsoc/src_peripheral/ethmac/rtl/eth_rxethmac.v',
|
| 379 |
|
|
'/mpsoc/src_peripheral/ethmac/rtl/eth_rxstatem.v',
|
| 380 |
|
|
'/mpsoc/src_peripheral/ethmac/rtl/eth_shiftreg.v',
|
| 381 |
|
|
'/mpsoc/src_peripheral/ethmac/rtl/eth_spram_256x32.v',
|
| 382 |
|
|
'/mpsoc/src_peripheral/ethmac/rtl/eth_top.v',
|
| 383 |
|
|
'/mpsoc/src_peripheral/ethmac/rtl/eth_transmitcontrol.v',
|
| 384 |
|
|
'/mpsoc/src_peripheral/ethmac/rtl/eth_txcounters.v',
|
| 385 |
|
|
'/mpsoc/src_peripheral/ethmac/rtl/eth_txethmac.v',
|
| 386 |
|
|
'/mpsoc/src_peripheral/ethmac/rtl/eth_txstatem.v',
|
| 387 |
|
|
'/mpsoc/src_peripheral/ethmac/rtl/eth_wishbone.v',
|
| 388 |
|
|
'/mpsoc/src_peripheral/ethmac/rtl/timescale.v',
|
| 389 |
|
|
'/mpsoc/src_peripheral/ethmac/rtl/xilinx_dist_ram_16x32.v',
|
| 390 |
|
|
'/mpsoc/src_peripheral/ethmac/ethtop.v',
|
| 391 |
|
|
'/mpsoc/src_peripheral/ethmac/eth_generic_ram.v'
|
| 392 |
|
|
],
|
| 393 |
|
|
'parameters_order' => [
|
| 394 |
|
|
'TX_FIFO_DATA_WIDTH',
|
| 395 |
|
|
'TX_FIFO_DEPTH',
|
| 396 |
|
|
'TX_FIFO_CNT_WIDTH',
|
| 397 |
|
|
'RX_FIFO_DATA_WIDTH',
|
| 398 |
|
|
'RX_FIFO_DEPTH',
|
| 399 |
|
|
'RX_FIFO_CNT_WIDTH'
|
| 400 |
|
|
],
|
| 401 |
|
|
'description' => 'The Ethernet MAC 10/100 Mbps.
|
| 402 |
|
|
For more information please check: https://opencores.org/project,ethmac',
|
| 403 |
|
|
'gen_sw_files' => [
|
| 404 |
|
|
'/mpsoc/src_peripheral/ethmac/ethfrename_sep_t${IP}.h'
|
| 405 |
|
|
],
|
| 406 |
|
|
'parameters' => {
|
| 407 |
|
|
'RX_FIFO_DEPTH' => {
|
| 408 |
|
|
'content' => '',
|
| 409 |
|
|
'redefine_param' => 1,
|
| 410 |
|
|
'default' => ' 16',
|
| 411 |
|
|
'info' => undef,
|
| 412 |
|
|
'type' => 'Fixed',
|
| 413 |
|
|
'global_param' => 0
|
| 414 |
|
|
},
|
| 415 |
|
|
'TX_FIFO_DEPTH' => {
|
| 416 |
|
|
'content' => '',
|
| 417 |
|
|
'redefine_param' => 1,
|
| 418 |
|
|
'default' => ' 16',
|
| 419 |
|
|
'info' => undef,
|
| 420 |
|
|
'global_param' => 0,
|
| 421 |
|
|
'type' => 'Fixed'
|
| 422 |
|
|
},
|
| 423 |
|
|
'RX_FIFO_DATA_WIDTH' => {
|
| 424 |
|
|
'type' => 'Fixed',
|
| 425 |
|
|
'global_param' => 0,
|
| 426 |
|
|
'content' => '',
|
| 427 |
|
|
'redefine_param' => 1,
|
| 428 |
|
|
'info' => undef,
|
| 429 |
|
|
'default' => ' 32'
|
| 430 |
|
|
},
|
| 431 |
|
|
'TX_FIFO_DATA_WIDTH' => {
|
| 432 |
|
|
'redefine_param' => 1,
|
| 433 |
|
|
'content' => '',
|
| 434 |
|
|
'default' => ' 32',
|
| 435 |
|
|
'info' => undef,
|
| 436 |
|
|
'type' => 'Fixed',
|
| 437 |
|
|
'global_param' => 0
|
| 438 |
|
|
},
|
| 439 |
|
|
'RX_FIFO_CNT_WIDTH' => {
|
| 440 |
|
|
'default' => ' 5',
|
| 441 |
|
|
'redefine_param' => 1,
|
| 442 |
|
|
'content' => '',
|
| 443 |
|
|
'info' => undef,
|
| 444 |
|
|
'global_param' => 0,
|
| 445 |
|
|
'type' => 'Fixed'
|
| 446 |
|
|
},
|
| 447 |
|
|
'TX_FIFO_CNT_WIDTH' => {
|
| 448 |
|
|
'type' => 'Fixed',
|
| 449 |
|
|
'global_param' => 0,
|
| 450 |
|
|
'info' => undef,
|
| 451 |
|
|
'redefine_param' => 1,
|
| 452 |
|
|
'content' => '',
|
| 453 |
|
|
'default' => ' 5'
|
| 454 |
|
|
}
|
| 455 |
|
|
},
|
| 456 |
|
|
'sw_files' => [],
|
| 457 |
|
|
'gui_status' => {
|
| 458 |
|
|
'status' => 'ideal',
|
| 459 |
|
|
'timeout' => 0
|
| 460 |
|
|
},
|
| 461 |
|
|
'custom_file' => {
|
| 462 |
|
|
'0' => {}
|
| 463 |
|
|
},
|
| 464 |
|
|
'category' => 'Communication',
|
| 465 |
|
|
'modules' => {
|
| 466 |
|
|
'ethtop' => {}
|
| 467 |
|
|
}
|
| 468 |
|
|
}, 'ip_gen' );
|
