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[/] [an-fpga-implementation-of-low-latency-noc-based-mpsoc/] [trunk/] [mpsoc/] [perl_gui/] [lib/] [ip/] [DMA/] [dma.IP] - Blame information for rev 34

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#######################################################################
##      File: dma.IP
##
##      Copyright (C) 2014-2016  Alireza Monemi
##
##      This file is part of ProNoC 1.7.0
##
##      WARNING: THIS IS AN AUTO-GENERATED FILE. CHANGES TO IT
##      MAY CAUSE UNEXPECTED BEHAIVOR.
################################################################################
 
$dma_multi_chan_wb = bless( {
                              'parameters_order' => [
                                                      'CHANNEL',
                                                      'MAX_TRANSACTION_WIDTH',
                                                      'MAX_BURST_SIZE',
                                                      'FIFO_B',
                                                      'DEBUG_EN',
                                                      'Dw',
                                                      'S_Aw',
                                                      'M_Aw',
                                                      'TAGw',
                                                      'SELw'
                                                    ],
                              'ports_order' => [
                                                 'reset',
                                                 'clk',
                                                 's_dat_i',
                                                 's_sel_i',
                                                 's_addr_i',
                                                 's_cti_i',
                                                 's_stb_i',
                                                 's_cyc_i',
                                                 's_we_i',
                                                 's_dat_o',
                                                 's_ack_o',
                                                 'm_rd_sel_o',
                                                 'm_rd_addr_o',
                                                 'm_rd_cti_o',
                                                 'm_rd_stb_o',
                                                 'm_rd_cyc_o',
                                                 'm_rd_we_o',
                                                 'm_rd_dat_i',
                                                 'm_rd_ack_i',
                                                 'm_wr_sel_o',
                                                 'm_wr_dat_o',
                                                 'm_wr_addr_o',
                                                 'm_wr_cti_o',
                                                 'm_wr_stb_o',
                                                 'm_wr_cyc_o',
                                                 'm_wr_we_o',
                                                 'm_wr_ack_i',
                                                 'irq'
                                               ],
                              'module_name' => 'dma_multi_chan_wb',
                              'unused' => {
                                            'plug:wb_master[0]' => [
                                                                     'dat_o',
                                                                     'bte_o',
                                                                     'rty_i',
                                                                     'err_i',
                                                                     'tag_o'
                                                                   ],
                                            'plug:wb_master[1]' => [
                                                                     'bte_o',
                                                                     'rty_i',
                                                                     'err_i',
                                                                     'tag_o',
                                                                     'dat_i'
                                                                   ],
                                            'plug:wb_slave[0]' => [
                                                                    'bte_i',
                                                                    'rty_o',
                                                                    'tag_i',
                                                                    'err_o'
                                                                  ]
                                          },
                              'hdl_files' => [
                                               '/mpsoc/src_noc/main_comp.v',
                                               '/mpsoc/src_noc/arbiter.v',
                                               '/mpsoc/src_peripheral/DMA/dma_multi_channel_wb.v',
                                               '/mpsoc/src_noc/flit_buffer.v'
                                             ],
                              'modules' => {
                                             'shared_mem_fifos' => {},
                                             'dma_single_wb' => {},
                                             'dma_multi_chan_wb' => {}
                                           },
                              'gui_status' => {
                                                'status' => 'ideal',
                                                'timeout' => 0
                                              },
                              'ports' => {
                                           's_cti_i' => {
                                                          'intfc_name' => 'plug:wb_slave[0]',
                                                          'intfc_port' => 'cti_i',
                                                          'type' => 'input',
                                                          'range' => 'TAGw-1     :   0'
                                                        },
                                           's_we_i' => {
                                                         'range' => '',
                                                         'intfc_port' => 'we_i',
                                                         'type' => 'input',
                                                         'intfc_name' => 'plug:wb_slave[0]'
                                                       },
                                           's_cyc_i' => {
                                                          'range' => '',
                                                          'intfc_port' => 'cyc_i',
                                                          'type' => 'input',
                                                          'intfc_name' => 'plug:wb_slave[0]'
                                                        },
                                           's_dat_o' => {
                                                          'range' => 'Dw-1       :   0',
                                                          'intfc_port' => 'dat_o',
                                                          'type' => 'output',
                                                          'intfc_name' => 'plug:wb_slave[0]'
                                                        },
                                           's_addr_i' => {
                                                           'range' => 'S_Aw-1     :   0',
                                                           'intfc_name' => 'plug:wb_slave[0]',
                                                           'type' => 'input',
                                                           'intfc_port' => 'adr_i'
                                                         },
                                           'm_wr_cyc_o' => {
                                                             'type' => 'output',
                                                             'intfc_port' => 'cyc_o',
                                                             'intfc_name' => 'plug:wb_master[1]',
                                                             'range' => ''
                                                           },
                                           'm_rd_dat_i' => {
                                                             'range' => 'Dw-1           :  0',
                                                             'type' => 'input',
                                                             'intfc_port' => 'dat_i',
                                                             'intfc_name' => 'plug:wb_master[0]'
                                                           },
                                           'm_rd_cti_o' => {
                                                             'intfc_name' => 'plug:wb_master[0]',
                                                             'intfc_port' => 'cti_o',
                                                             'type' => 'output',
                                                             'range' => 'TAGw-1          :   0'
                                                           },
                                           's_ack_o' => {
                                                          'range' => '',
                                                          'intfc_name' => 'plug:wb_slave[0]',
                                                          'intfc_port' => 'ack_o',
                                                          'type' => 'output'
                                                        },
                                           'clk' => {
                                                      'range' => '',
                                                      'intfc_name' => 'plug:clk[0]',
                                                      'type' => 'input',
                                                      'intfc_port' => 'clk_i'
                                                    },
                                           'm_wr_cti_o' => {
                                                             'range' => 'TAGw-1          :   0',
                                                             'intfc_name' => 'plug:wb_master[1]',
                                                             'type' => 'output',
                                                             'intfc_port' => 'cti_o'
                                                           },
                                           's_dat_i' => {
                                                          'range' => 'Dw-1       :   0',
                                                          'intfc_name' => 'plug:wb_slave[0]',
                                                          'type' => 'input',
                                                          'intfc_port' => 'dat_i'
                                                        },
                                           'm_rd_stb_o' => {
                                                             'intfc_name' => 'plug:wb_master[0]',
                                                             'intfc_port' => 'stb_o',
                                                             'type' => 'output',
                                                             'range' => ''
                                                           },
                                           's_sel_i' => {
                                                          'type' => 'input',
                                                          'intfc_port' => 'sel_i',
                                                          'intfc_name' => 'plug:wb_slave[0]',
                                                          'range' => 'SELw-1     :   0'
                                                        },
                                           'm_rd_we_o' => {
                                                            'type' => 'output',
                                                            'intfc_port' => 'we_o',
                                                            'intfc_name' => 'plug:wb_master[0]',
                                                            'range' => ''
                                                          },
                                           'm_wr_dat_o' => {
                                                             'range' => 'Dw-1            :   0',
                                                             'intfc_name' => 'plug:wb_master[1]',
                                                             'type' => 'output',
                                                             'intfc_port' => 'dat_o'
                                                           },
                                           'm_wr_stb_o' => {
                                                             'intfc_name' => 'plug:wb_master[1]',
                                                             'type' => 'output',
                                                             'intfc_port' => 'stb_o',
                                                             'range' => ''
                                                           },
                                           'reset' => {
                                                        'range' => '',
                                                        'intfc_name' => 'plug:reset[0]',
                                                        'type' => 'input',
                                                        'intfc_port' => 'reset_i'
                                                      },
                                           'm_wr_addr_o' => {
                                                              'range' => 'M_Aw-1          :   0',
                                                              'intfc_port' => 'adr_o',
                                                              'type' => 'output',
                                                              'intfc_name' => 'plug:wb_master[1]'
                                                            },
                                           'm_rd_addr_o' => {
                                                              'intfc_name' => 'plug:wb_master[0]',
                                                              'type' => 'output',
                                                              'intfc_port' => 'adr_o',
                                                              'range' => 'M_Aw-1          :   0'
                                                            },
                                           'm_wr_sel_o' => {
                                                             'range' => 'SELw-1          :   0',
                                                             'intfc_name' => 'plug:wb_master[1]',
                                                             'type' => 'output',
                                                             'intfc_port' => 'sel_o'
                                                           },
                                           'm_wr_ack_i' => {
                                                             'range' => '',
                                                             'intfc_port' => 'ack_i',
                                                             'type' => 'input',
                                                             'intfc_name' => 'plug:wb_master[1]'
                                                           },
                                           's_stb_i' => {
                                                          'intfc_name' => 'plug:wb_slave[0]',
                                                          'intfc_port' => 'stb_i',
                                                          'type' => 'input',
                                                          'range' => ''
                                                        },
                                           'm_wr_we_o' => {
                                                            'range' => '',
                                                            'intfc_name' => 'plug:wb_master[1]',
                                                            'type' => 'output',
                                                            'intfc_port' => 'we_o'
                                                          },
                                           'm_rd_cyc_o' => {
                                                             'range' => '',
                                                             'intfc_port' => 'cyc_o',
                                                             'type' => 'output',
                                                             'intfc_name' => 'plug:wb_master[0]'
                                                           },
                                           'm_rd_sel_o' => {
                                                             'range' => 'SELw-1          :   0',
                                                             'intfc_port' => 'sel_o',
                                                             'type' => 'output',
                                                             'intfc_name' => 'plug:wb_master[0]'
                                                           },
                                           'irq' => {
                                                      'type' => 'output',
                                                      'intfc_port' => 'int_o',
                                                      'intfc_name' => 'plug:interrupt_peripheral[0]',
                                                      'range' => ''
                                                    },
                                           'm_rd_ack_i' => {
                                                             'range' => '',
                                                             'type' => 'input',
                                                             'intfc_port' => 'ack_i',
                                                             'intfc_name' => 'plug:wb_master[0]'
                                                           }
                                         },
                              'parameters' => {
                                                'DEBUG_EN' => {
                                                                'info' => 'Parameter',
                                                                'content' => '',
                                                                'type' => 'Fixed',
                                                                'deafult' => '1',
                                                                'global_param' => 'Parameter',
                                                                'redefine_param' => 1
                                                              },
                                                'MAX_BURST_SIZE' => {
                                                                      'redefine_param' => 1,
                                                                      'type' => 'Combo-box',
                                                                      'content' => '\'2,4,8,16,32,64,128,256,512,1024,2048\'',
                                                                      'info' => 'Maximum burst size in words.
The wishbone bus will be released each time one burst is completed or when the internal FIFO becomes full.  The bus will be released for one clock cycle. Then in case, there are other active channels, another active channel will get access to the bus using round robin arbiter.  This process will be continued until all desired data is transferred. ',
                                                                      'global_param' => 'Parameter',
                                                                      'deafult' => '256'
                                                                    },
                                                'MAX_TRANSACTION_WIDTH' => {
                                                                             'global_param' => 'Parameter',
                                                                             'deafult' => '10',
                                                                             'content' => '2,32,1',
                                                                             'info' => 'The width of maximum transaction size in words.
The maximum data that can be sent via one DMA channel will be 2 power of MAX_DMA_TRANSACTION_WIDTH in words.',
                                                                             'type' => 'Spin-button',
                                                                             'redefine_param' => 1
                                                                           },
                                                'FIFO_B' => {
                                                              'redefine_param' => 1,
                                                              'global_param' => 'Parameter',
                                                              'deafult' => '4',
                                                              'info' => 'Channel  FIFO size in words.
All channels will share same FPGA block RAM. Hence, the total needed Block RAM words is the multiplication of channel num in channel FIFO size.
 
',
                                                              'content' => '\'2,4,8,16,32,64,128,256,512,1024,2048\'',
                                                              'type' => 'Combo-box'
                                                            },
                                                'Dw' => {
                                                          'redefine_param' => 1,
                                                          'deafult' => '32',
                                                          'global_param' => 'Parameter',
                                                          'info' => 'Wishbone bus Data size in bit',
                                                          'content' => '8,1024,8',
                                                          'type' => 'Spin-button'
                                                        },
                                                'TAGw' => {
                                                            'redefine_param' => 1,
                                                            'content' => '',
                                                            'info' => 'Parameter',
                                                            'type' => 'Fixed',
                                                            'deafult' => '3',
                                                            'global_param' => 'Parameter'
                                                          },
                                                'M_Aw' => {
                                                            'type' => 'Fixed',
                                                            'info' => 'Parameter',
                                                            'content' => '',
                                                            'global_param' => 'Parameter',
                                                            'deafult' => '32',
                                                            'redefine_param' => 1
                                                          },
                                                'CHANNEL' => {
                                                               'redefine_param' => 1,
                                                               'info' => 'Number of DMA channels.
In case there are multiple active DMA channels,  Each time one single active DMA channel get access to the wishbone bus using round robin arbiter. The Wishbone bus is granted for the winter channel until its FIFO is not full and the number od sent data is smaller than the burst size.',
                                                               'content' => '1,32,1',
                                                               'type' => 'Spin-button',
                                                               'global_param' => 'Parameter',
                                                               'deafult' => '1'
                                                             },
                                                'S_Aw' => {
                                                            'redefine_param' => 1,
                                                            'content' => '',
                                                            'info' => 'Parameter',
                                                            'type' => 'Fixed',
                                                            'global_param' => 'Parameter',
                                                            'deafult' => '8'
                                                          },
                                                'SELw' => {
                                                            'type' => 'Fixed',
                                                            'content' => '',
                                                            'info' => 'Parameter',
                                                            'global_param' => 'Parameter',
                                                            'deafult' => '4',
                                                            'redefine_param' => 1
                                                          }
                                              },
                              'plugs' => {
                                           'clk' => {
                                                      'clk' => {},
                                                      'type' => 'num',
                                                      '0' => {
                                                               'name' => 'clk'
                                                             },
                                                      'value' => 1
                                                    },
                                           'wb_master' => {
                                                            'value' => 2,
                                                            '0' => {
                                                                     'name' => 'wb_rd'
                                                                   },
                                                            '1' => {
                                                                     'name' => 'wb_wr'
                                                                   },
                                                            'wb_master' => {},
                                                            'type' => 'num'
                                                          },
                                           'interrupt_peripheral' => {
                                                                       'type' => 'num',
                                                                       'interrupt_peripheral' => {},
                                                                       '0' => {
                                                                                'name' => 'interrupt_peripheral'
                                                                              },
                                                                       'value' => 1
                                                                     },
                                           'wb_slave' => {
                                                           'type' => 'num',
                                                           'value' => 1,
                                                           'wb_slave' => {},
                                                           '0' => {
                                                                    'addr' => '0x9300_0000      0x93ff_ffff             Memory Controller',
                                                                    'name' => 'wb_slave',
                                                                    'width' => 10
                                                                  }
                                                         },
                                           'reset' => {
                                                        '0' => {
                                                                 'name' => 'reset'
                                                               },
                                                        'value' => 1,
                                                        'reset' => {},
                                                        'type' => 'num'
                                                      }
                                         },
                              'description' => 'A round robin based  multi channel DMA (no byte enable). support burst data transaction.',
                              'ip_name' => 'dma',
                              'file_name' => '/home/alireza/mywork/mpsoc/src_peripheral/DMA/dma_multi_channel_wb.v',
                              'category' => 'DMA',
                              'system_h' => '#define ${IP}_STATUS_REG   (*((volatile unsigned int *) ($BASE)))
#define ${IP}_BURST_SIZE_ADDR_REG  (*((volatile unsigned int *) ($BASE+4)))
 
 
#define ${IP}_CHANNEL   ${CHANNEL}
#define ${IP}_DATA_SIZE_ADDR_REG(channel)  (*((volatile unsigned int *) ($BASE+8+(channel<<5))))
#define ${IP}_RD_START_ADDR_REG(channel)   (*((volatile unsigned int *) ($BASE+12+(channel<<5))))
#define ${IP}_WR_START_ADDR_REG(channel)  (*((volatile unsigned int *) ($BASE+16+(channel<<5))))
 
 
// assign status= {rd_enable_binarry,wr_enable_binarry,channel_rd_is_active,channel_wr_is_active};
 
#define ${IP}_channel_is_busy(channel) ( (${IP}_STATUS_REG >> channel) & 0x1)
 
 
void ${IP}_initial (unsigned int burst_size) {
         ${IP}_BURST_SIZE_ADDR_REG  =  burst_size;
}
 
 
void ${IP}_transfer (unsigned int channel, unsigned int read_start_addr,  unsigned int data_size, unsigned int write_start_addr){
        while ( ${IP}_channel_is_busy(channel)); // wait until DMA  channel is busy
         ${IP}_RD_START_ADDR_REG(channel)  = read_start_addr;
         ${IP}_DATA_SIZE_ADDR_REG(channel)  =  data_size;
         ${IP}_WR_START_ADDR_REG(channel)  = write_start_addr;
}'
                            }, 'ip_gen' );

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Subversion Repositories an-fpga-implementation-of-low-latency-noc-based-mpsoc

[/] [an-fpga-implementation-of-low-latency-noc-based-mpsoc/] [trunk/] [mpsoc/] [perl_gui/] [lib/] [ip/] [DMA/] [dma.IP] - Blame information for rev 34

Line No.	Rev	Author	Line
1	34	alirezamon	`#######################################################################`
2			`## File: dma.IP`
3			`##`
4			`## Copyright (C) 2014-2016 Alireza Monemi`
5			`##`
6			`## This file is part of ProNoC 1.7.0`
7			`##`
8			`## WARNING: THIS IS AN AUTO-GENERATED FILE. CHANGES TO IT`
9			`## MAY CAUSE UNEXPECTED BEHAIVOR.`
10			`################################################################################`
11
12			`$dma_multi_chan_wb = bless( {`
13			`'parameters_order' => [`
14			`'CHANNEL',`
15			`'MAX_TRANSACTION_WIDTH',`
16			`'MAX_BURST_SIZE',`
17			`'FIFO_B',`
18			`'DEBUG_EN',`
19			`'Dw',`
20			`'S_Aw',`
21			`'M_Aw',`
22			`'TAGw',`
23			`'SELw'`
24			`],`
25			`'ports_order' => [`
26			`'reset',`
27			`'clk',`
28			`'s_dat_i',`
29			`'s_sel_i',`
30			`'s_addr_i',`
31			`'s_cti_i',`
32			`'s_stb_i',`
33			`'s_cyc_i',`
34			`'s_we_i',`
35			`'s_dat_o',`
36			`'s_ack_o',`
37			`'m_rd_sel_o',`
38			`'m_rd_addr_o',`
39			`'m_rd_cti_o',`
40			`'m_rd_stb_o',`
41			`'m_rd_cyc_o',`
42			`'m_rd_we_o',`
43			`'m_rd_dat_i',`
44			`'m_rd_ack_i',`
45			`'m_wr_sel_o',`
46			`'m_wr_dat_o',`
47			`'m_wr_addr_o',`
48			`'m_wr_cti_o',`
49			`'m_wr_stb_o',`
50			`'m_wr_cyc_o',`
51			`'m_wr_we_o',`
52			`'m_wr_ack_i',`
53			`'irq'`
54			`],`
55			`'module_name' => 'dma_multi_chan_wb',`
56			`'unused' => {`
57			`'plug:wb_master[0]' => [`
58			`'dat_o',`
59			`'bte_o',`
60			`'rty_i',`
61			`'err_i',`
62			`'tag_o'`
63			`],`
64			`'plug:wb_master[1]' => [`
65			`'bte_o',`
66			`'rty_i',`
67			`'err_i',`
68			`'tag_o',`
69			`'dat_i'`
70			`],`
71			`'plug:wb_slave[0]' => [`
72			`'bte_i',`
73			`'rty_o',`
74			`'tag_i',`
75			`'err_o'`
76			`]`
77			`},`
78			`'hdl_files' => [`
79			`'/mpsoc/src_noc/main_comp.v',`
80			`'/mpsoc/src_noc/arbiter.v',`
81			`'/mpsoc/src_peripheral/DMA/dma_multi_channel_wb.v',`
82			`'/mpsoc/src_noc/flit_buffer.v'`
83			`],`
84			`'modules' => {`
85			`'shared_mem_fifos' => {},`
86			`'dma_single_wb' => {},`
87			`'dma_multi_chan_wb' => {}`
88			`},`
89			`'gui_status' => {`
90			`'status' => 'ideal',`
91			`'timeout' => 0`
92			`},`
93			`'ports' => {`
94			`'s_cti_i' => {`
95			`'intfc_name' => 'plug:wb_slave[0]',`
96			`'intfc_port' => 'cti_i',`
97			`'type' => 'input',`
98			`'range' => 'TAGw-1 : 0'`
99			`},`
100			`'s_we_i' => {`
101			`'range' => '',`
102			`'intfc_port' => 'we_i',`
103			`'type' => 'input',`
104			`'intfc_name' => 'plug:wb_slave[0]'`
105			`},`
106			`'s_cyc_i' => {`
107			`'range' => '',`
108			`'intfc_port' => 'cyc_i',`
109			`'type' => 'input',`
110			`'intfc_name' => 'plug:wb_slave[0]'`
111			`},`
112			`'s_dat_o' => {`
113			`'range' => 'Dw-1 : 0',`
114			`'intfc_port' => 'dat_o',`
115			`'type' => 'output',`
116			`'intfc_name' => 'plug:wb_slave[0]'`
117			`},`
118			`'s_addr_i' => {`
119			`'range' => 'S_Aw-1 : 0',`
120			`'intfc_name' => 'plug:wb_slave[0]',`
121			`'type' => 'input',`
122			`'intfc_port' => 'adr_i'`
123			`},`
124			`'m_wr_cyc_o' => {`
125			`'type' => 'output',`
126			`'intfc_port' => 'cyc_o',`
127			`'intfc_name' => 'plug:wb_master[1]',`
128			`'range' => ''`
129			`},`
130			`'m_rd_dat_i' => {`
131			`'range' => 'Dw-1 : 0',`
132			`'type' => 'input',`
133			`'intfc_port' => 'dat_i',`
134			`'intfc_name' => 'plug:wb_master[0]'`
135			`},`
136			`'m_rd_cti_o' => {`
137			`'intfc_name' => 'plug:wb_master[0]',`
138			`'intfc_port' => 'cti_o',`
139			`'type' => 'output',`
140			`'range' => 'TAGw-1 : 0'`
141			`},`
142			`'s_ack_o' => {`
143			`'range' => '',`
144			`'intfc_name' => 'plug:wb_slave[0]',`
145			`'intfc_port' => 'ack_o',`
146			`'type' => 'output'`
147			`},`
148			`'clk' => {`
149			`'range' => '',`
150			`'intfc_name' => 'plug:clk[0]',`
151			`'type' => 'input',`
152			`'intfc_port' => 'clk_i'`
153			`},`
154			`'m_wr_cti_o' => {`
155			`'range' => 'TAGw-1 : 0',`
156			`'intfc_name' => 'plug:wb_master[1]',`
157			`'type' => 'output',`
158			`'intfc_port' => 'cti_o'`
159			`},`
160			`'s_dat_i' => {`
161			`'range' => 'Dw-1 : 0',`
162			`'intfc_name' => 'plug:wb_slave[0]',`
163			`'type' => 'input',`
164			`'intfc_port' => 'dat_i'`
165			`},`
166			`'m_rd_stb_o' => {`
167			`'intfc_name' => 'plug:wb_master[0]',`
168			`'intfc_port' => 'stb_o',`
169			`'type' => 'output',`
170			`'range' => ''`
171			`},`
172			`'s_sel_i' => {`
173			`'type' => 'input',`
174			`'intfc_port' => 'sel_i',`
175			`'intfc_name' => 'plug:wb_slave[0]',`
176			`'range' => 'SELw-1 : 0'`
177			`},`
178			`'m_rd_we_o' => {`
179			`'type' => 'output',`
180			`'intfc_port' => 'we_o',`
181			`'intfc_name' => 'plug:wb_master[0]',`
182			`'range' => ''`
183			`},`
184			`'m_wr_dat_o' => {`
185			`'range' => 'Dw-1 : 0',`
186			`'intfc_name' => 'plug:wb_master[1]',`
187			`'type' => 'output',`
188			`'intfc_port' => 'dat_o'`
189			`},`
190			`'m_wr_stb_o' => {`
191			`'intfc_name' => 'plug:wb_master[1]',`
192			`'type' => 'output',`
193			`'intfc_port' => 'stb_o',`
194			`'range' => ''`
195			`},`
196			`'reset' => {`
197			`'range' => '',`
198			`'intfc_name' => 'plug:reset[0]',`
199			`'type' => 'input',`
200			`'intfc_port' => 'reset_i'`
201			`},`
202			`'m_wr_addr_o' => {`
203			`'range' => 'M_Aw-1 : 0',`
204			`'intfc_port' => 'adr_o',`
205			`'type' => 'output',`
206			`'intfc_name' => 'plug:wb_master[1]'`
207			`},`
208			`'m_rd_addr_o' => {`
209			`'intfc_name' => 'plug:wb_master[0]',`
210			`'type' => 'output',`
211			`'intfc_port' => 'adr_o',`
212			`'range' => 'M_Aw-1 : 0'`
213			`},`
214			`'m_wr_sel_o' => {`
215			`'range' => 'SELw-1 : 0',`
216			`'intfc_name' => 'plug:wb_master[1]',`
217			`'type' => 'output',`
218			`'intfc_port' => 'sel_o'`
219			`},`
220			`'m_wr_ack_i' => {`
221			`'range' => '',`
222			`'intfc_port' => 'ack_i',`
223			`'type' => 'input',`
224			`'intfc_name' => 'plug:wb_master[1]'`
225			`},`
226			`'s_stb_i' => {`
227			`'intfc_name' => 'plug:wb_slave[0]',`
228			`'intfc_port' => 'stb_i',`
229			`'type' => 'input',`
230			`'range' => ''`
231			`},`
232			`'m_wr_we_o' => {`
233			`'range' => '',`
234			`'intfc_name' => 'plug:wb_master[1]',`
235			`'type' => 'output',`
236			`'intfc_port' => 'we_o'`
237			`},`
238			`'m_rd_cyc_o' => {`
239			`'range' => '',`
240			`'intfc_port' => 'cyc_o',`
241			`'type' => 'output',`
242			`'intfc_name' => 'plug:wb_master[0]'`
243			`},`
244			`'m_rd_sel_o' => {`
245			`'range' => 'SELw-1 : 0',`
246			`'intfc_port' => 'sel_o',`
247			`'type' => 'output',`
248			`'intfc_name' => 'plug:wb_master[0]'`
249			`},`
250			`'irq' => {`
251			`'type' => 'output',`
252			`'intfc_port' => 'int_o',`
253			`'intfc_name' => 'plug:interrupt_peripheral[0]',`
254			`'range' => ''`
255			`},`
256			`'m_rd_ack_i' => {`
257			`'range' => '',`
258			`'type' => 'input',`
259			`'intfc_port' => 'ack_i',`
260			`'intfc_name' => 'plug:wb_master[0]'`
261			`}`
262			`},`
263			`'parameters' => {`
264			`'DEBUG_EN' => {`
265			`'info' => 'Parameter',`
266			`'content' => '',`
267			`'type' => 'Fixed',`
268			`'deafult' => '1',`
269			`'global_param' => 'Parameter',`
270			`'redefine_param' => 1`
271			`},`
272			`'MAX_BURST_SIZE' => {`
273			`'redefine_param' => 1,`
274			`'type' => 'Combo-box',`
275			`'content' => '\'2,4,8,16,32,64,128,256,512,1024,2048\'',`
276			`'info' => 'Maximum burst size in words.`
277			`The wishbone bus will be released each time one burst is completed or when the internal FIFO becomes full. The bus will be released for one clock cycle. Then in case, there are other active channels, another active channel will get access to the bus using round robin arbiter. This process will be continued until all desired data is transferred. ',`
278			`'global_param' => 'Parameter',`
279			`'deafult' => '256'`
280			`},`
281			`'MAX_TRANSACTION_WIDTH' => {`
282			`'global_param' => 'Parameter',`
283			`'deafult' => '10',`
284			`'content' => '2,32,1',`
285			`'info' => 'The width of maximum transaction size in words.`
286			`The maximum data that can be sent via one DMA channel will be 2 power of MAX_DMA_TRANSACTION_WIDTH in words.',`
287			`'type' => 'Spin-button',`
288			`'redefine_param' => 1`
289			`},`
290			`'FIFO_B' => {`
291			`'redefine_param' => 1,`
292			`'global_param' => 'Parameter',`
293			`'deafult' => '4',`
294			`'info' => 'Channel FIFO size in words.`
295			`All channels will share same FPGA block RAM. Hence, the total needed Block RAM words is the multiplication of channel num in channel FIFO size.`
296
297			`',`
298			`'content' => '\'2,4,8,16,32,64,128,256,512,1024,2048\'',`
299			`'type' => 'Combo-box'`
300			`},`
301			`'Dw' => {`
302			`'redefine_param' => 1,`
303			`'deafult' => '32',`
304			`'global_param' => 'Parameter',`
305			`'info' => 'Wishbone bus Data size in bit',`
306			`'content' => '8,1024,8',`
307			`'type' => 'Spin-button'`
308			`},`
309			`'TAGw' => {`
310			`'redefine_param' => 1,`
311			`'content' => '',`
312			`'info' => 'Parameter',`
313			`'type' => 'Fixed',`
314			`'deafult' => '3',`
315			`'global_param' => 'Parameter'`
316			`},`
317			`'M_Aw' => {`
318			`'type' => 'Fixed',`
319			`'info' => 'Parameter',`
320			`'content' => '',`
321			`'global_param' => 'Parameter',`
322			`'deafult' => '32',`
323			`'redefine_param' => 1`
324			`},`
325			`'CHANNEL' => {`
326			`'redefine_param' => 1,`
327			`'info' => 'Number of DMA channels.`
328			`In case there are multiple active DMA channels, Each time one single active DMA channel get access to the wishbone bus using round robin arbiter. The Wishbone bus is granted for the winter channel until its FIFO is not full and the number od sent data is smaller than the burst size.',`
329			`'content' => '1,32,1',`
330			`'type' => 'Spin-button',`
331			`'global_param' => 'Parameter',`
332			`'deafult' => '1'`
333			`},`
334			`'S_Aw' => {`
335			`'redefine_param' => 1,`
336			`'content' => '',`
337			`'info' => 'Parameter',`
338			`'type' => 'Fixed',`
339			`'global_param' => 'Parameter',`
340			`'deafult' => '8'`
341			`},`
342			`'SELw' => {`
343			`'type' => 'Fixed',`
344			`'content' => '',`
345			`'info' => 'Parameter',`
346			`'global_param' => 'Parameter',`
347			`'deafult' => '4',`
348			`'redefine_param' => 1`
349			`}`
350			`},`
351			`'plugs' => {`
352			`'clk' => {`
353			`'clk' => {},`
354			`'type' => 'num',`
355			`'0' => {`
356			`'name' => 'clk'`
357			`},`
358			`'value' => 1`
359			`},`
360			`'wb_master' => {`
361			`'value' => 2,`
362			`'0' => {`
363			`'name' => 'wb_rd'`
364			`},`
365			`'1' => {`
366			`'name' => 'wb_wr'`
367			`},`
368			`'wb_master' => {},`
369			`'type' => 'num'`
370			`},`
371			`'interrupt_peripheral' => {`
372			`'type' => 'num',`
373			`'interrupt_peripheral' => {},`
374			`'0' => {`
375			`'name' => 'interrupt_peripheral'`
376			`},`
377			`'value' => 1`
378			`},`
379			`'wb_slave' => {`
380			`'type' => 'num',`
381			`'value' => 1,`
382			`'wb_slave' => {},`
383			`'0' => {`
384			`'addr' => '0x9300_0000 0x93ff_ffff Memory Controller',`
385			`'name' => 'wb_slave',`
386			`'width' => 10`
387			`}`
388			`},`
389			`'reset' => {`
390			`'0' => {`
391			`'name' => 'reset'`
392			`},`
393			`'value' => 1,`
394			`'reset' => {},`
395			`'type' => 'num'`
396			`}`
397			`},`
398			`'description' => 'A round robin based multi channel DMA (no byte enable). support burst data transaction.',`
399			`'ip_name' => 'dma',`
400			`'file_name' => '/home/alireza/mywork/mpsoc/src_peripheral/DMA/dma_multi_channel_wb.v',`
401			`'category' => 'DMA',`
402			`'system_h' => '#define ${IP}_STATUS_REG (((volatile unsigned int ) ($BASE)))`
403			`#define ${IP}_BURST_SIZE_ADDR_REG (((volatile unsigned int ) ($BASE+4)))`
404
405
406			`#define ${IP}_CHANNEL ${CHANNEL}`
407			`#define ${IP}_DATA_SIZE_ADDR_REG(channel) (((volatile unsigned int ) ($BASE+8+(channel<<5))))`
408			`#define ${IP}_RD_START_ADDR_REG(channel) (((volatile unsigned int ) ($BASE+12+(channel<<5))))`
409			`#define ${IP}_WR_START_ADDR_REG(channel) (((volatile unsigned int ) ($BASE+16+(channel<<5))))`
410
411
412			`// assign status= {rd_enable_binarry,wr_enable_binarry,channel_rd_is_active,channel_wr_is_active};`
413
414			`#define ${IP}_channel_is_busy(channel) ( (${IP}_STATUS_REG >> channel) & 0x1)`
415
416
417			`void ${IP}_initial (unsigned int burst_size) {`
418			`${IP}_BURST_SIZE_ADDR_REG = burst_size;`
419			`}`
420
421
422			`void ${IP}_transfer (unsigned int channel, unsigned int read_start_addr, unsigned int data_size, unsigned int write_start_addr){`
423			`while ( ${IP}_channel_is_busy(channel)); // wait until DMA channel is busy`
424			`${IP}_RD_START_ADDR_REG(channel) = read_start_addr;`
425			`${IP}_DATA_SIZE_ADDR_REG(channel) = data_size;`
426			`${IP}_WR_START_ADDR_REG(channel) = write_start_addr;`
427			`}'`
428			`}, 'ip_gen' );`