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[/] [an-fpga-implementation-of-low-latency-noc-based-mpsoc/] [trunk/] [mpsoc/] [perl_gui/] [lib/] [ip/] [DMA/] [dma.IP] - Blame information for rev 38

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#######################################################################
##      File: dma.IP
##
##      Copyright (C) 2014-2016  Alireza Monemi
##
##      This file is part of ProNoC 1.8.0
##
##      WARNING: THIS IS AN AUTO-GENERATED FILE. CHANGES TO IT
##      MAY CAUSE UNEXPECTED BEHAIVOR.
################################################################################
 
$ipgen = bless( {
                  'description' => 'A wishbone bus round robin-based  multi channel DMA (no byte enable is supported yet). The DMA supports burst data transaction.',
                  'modules' => {
                                 'dma_multi_chan_wb' => {},
                                 'shared_mem_fifos' => {},
                                 'dma_single_wb' => {}
                               },
                  'plugs' => {
                               'clk' => {
                                          'type' => 'num',
                                          'value' => 1,
                                          '0' => {
                                                   'name' => 'clk'
                                                 },
                                          'clk' => {}
                                        },
                               'wb_slave' => {
                                               'value' => 1,
                                               'wb_slave' => {},
                                               'type' => 'num',
                                               '0' => {
                                                        'width' => 10,
                                                        'addr' => '0x9300_0000  0x93ff_ffff             Memory Controller',
                                                        'name' => 'wb_slave'
                                                      }
                                             },
                               'interrupt_peripheral' => {
                                                           'value' => 1,
                                                           'interrupt_peripheral' => {},
                                                           'type' => 'num',
                                                           '0' => {
                                                                    'name' => 'interrupt_peripheral'
                                                                  }
                                                         },
                               'wb_master' => {
                                                '1' => {
                                                         'name' => 'wb_wr'
                                                       },
                                                'wb_master' => {},
                                                'value' => 2,
                                                'type' => 'num',
                                                '0' => {
                                                         'name' => 'wb_rd'
                                                       }
                                              },
                               'reset' => {
                                            'type' => 'num',
                                            'reset' => {},
                                            'value' => 1,
                                            '0' => {
                                                     'name' => 'reset'
                                                   }
                                          }
                             },
                  'ports_order' => [
                                     'reset',
                                     'clk',
                                     's_dat_i',
                                     's_sel_i',
                                     's_addr_i',
                                     's_cti_i',
                                     's_stb_i',
                                     's_cyc_i',
                                     's_we_i',
                                     's_dat_o',
                                     's_ack_o',
                                     'm_rd_sel_o',
                                     'm_rd_addr_o',
                                     'm_rd_cti_o',
                                     'm_rd_stb_o',
                                     'm_rd_cyc_o',
                                     'm_rd_we_o',
                                     'm_rd_dat_i',
                                     'm_rd_ack_i',
                                     'm_wr_sel_o',
                                     'm_wr_dat_o',
                                     'm_wr_addr_o',
                                     'm_wr_cti_o',
                                     'm_wr_stb_o',
                                     'm_wr_cyc_o',
                                     'm_wr_we_o',
                                     'm_wr_ack_i',
                                     'irq'
                                   ],
                  'parameters_order' => [
                                          'CHANNEL',
                                          'MAX_TRANSACTION_WIDTH',
                                          'MAX_BURST_SIZE',
                                          'FIFO_B',
                                          'DEBUG_EN',
                                          'Dw',
                                          'S_Aw',
                                          'M_Aw',
                                          'TAGw',
                                          'SELw'
                                        ],
                  'ip_name' => 'dma',
                  'file_name' => '/home/alireza/mywork/mpsoc/src_peripheral/DMA/dma_multi_channel_wb.v',
                  'hdl_files' => [
                                   '/mpsoc/src_noc/main_comp.v',
                                   '/mpsoc/src_noc/arbiter.v',
                                   '/mpsoc/src_peripheral/DMA/dma_multi_channel_wb.v',
                                   '/mpsoc/src_noc/flit_buffer.v'
                                 ],
                  'version' => 4,
                  'category' => 'DMA',
                  'module_name' => 'dma_multi_chan_wb',
                  'parameters' => {
                                    'M_Aw' => {
                                                'redefine_param' => 1,
                                                'type' => 'Fixed',
                                                'default' => '32',
                                                'content' => '',
                                                'info' => 'Parameter',
                                                'global_param' => 'Parameter'
                                              },
                                    'CHANNEL' => {
                                                   'global_param' => 'Parameter',
                                                   'info' => 'Number of DMA channels.
In case there are multiple active DMA channels,  Each time one single active DMA channel get access to the wishbone bus using round robin arbiter. The Wishbone bus is granted for the winter channel until its FIFO is not full and the number of sent data is smaller than the burst size.',
                                                   'redefine_param' => 1,
                                                   'type' => 'Spin-button',
                                                   'default' => '1',
                                                   'content' => '1,32,1'
                                                 },
                                    'SELw' => {
                                                'info' => 'Parameter',
                                                'global_param' => 'Parameter',
                                                'redefine_param' => 1,
                                                'default' => '4',
                                                'type' => 'Fixed',
                                                'content' => ''
                                              },
                                    'Dw' => {
                                              'global_param' => 'Parameter',
                                              'info' => 'Wishbone bus Data size in bit',
                                              'redefine_param' => 1,
                                              'type' => 'Spin-button',
                                              'default' => '32',
                                              'content' => '8,1024,8'
                                            },
                                    'FIFO_B' => {
                                                  'global_param' => 'Parameter',
                                                  'info' => 'Channel  FIFO size in words.
All channels will share same FPGA block RAM. Hence, the total needed Block RAM words is the multiplication of channel num in channel FIFO size.
 
',
                                                  'content' => '2,4,8,16,32,64,128,256,512,1024,2048',
                                                  'default' => '4',
                                                  'type' => 'Combo-box',
                                                  'redefine_param' => 1
                                                },
                                    'MAX_BURST_SIZE' => {
                                                          'global_param' => 'Parameter',
                                                          'info' => 'Maximum burst size in words.
The wishbone bus will be released each time one burst is completed or when the internal FIFO becomes full.  The bus will be released for one clock cycle. Then in case, there are other active channels, another active channel will get access to the bus using round robin arbiter.  This process will be continued until all desired data is transferred. ',
                                                          'content' => '2,4,8,16,32,64,128,256,512,1024,2048',
                                                          'redefine_param' => 1,
                                                          'type' => 'Combo-box',
                                                          'default' => '256'
                                                        },
                                    'DEBUG_EN' => {
                                                    'content' => '',
                                                    'redefine_param' => 1,
                                                    'type' => 'Fixed',
                                                    'default' => '1',
                                                    'global_param' => 'Parameter',
                                                    'info' => 'Parameter'
                                                  },
                                    'TAGw' => {
                                                'default' => '3',
                                                'type' => 'Fixed',
                                                'redefine_param' => 1,
                                                'content' => '',
                                                'info' => 'Parameter',
                                                'global_param' => 'Parameter'
                                              },
                                    'S_Aw' => {
                                                'info' => 'Parameter',
                                                'global_param' => 'Parameter',
                                                'type' => 'Fixed',
                                                'default' => '8',
                                                'redefine_param' => 1,
                                                'content' => ''
                                              },
                                    'MAX_TRANSACTION_WIDTH' => {
                                                                 'default' => '10',
                                                                 'type' => 'Spin-button',
                                                                 'redefine_param' => 1,
                                                                 'content' => '2,32,1',
                                                                 'info' => 'The width of maximum transaction size in words.
The maximum data that can be sent via one DMA channel will be 2 power of MAX_DMA_TRANSACTION_WIDTH in words.',
                                                                 'global_param' => 'Parameter'
                                                               }
                                  },
                  'gui_status' => {
                                    'timeout' => 0,
                                    'status' => 'ideal'
                                  },
                  'ports' => {
                               'm_rd_sel_o' => {
                                                 'intfc_name' => 'plug:wb_master[0]',
                                                 'intfc_port' => 'sel_o',
                                                 'range' => 'SELw-1          :   0',
                                                 'type' => 'output'
                                               },
                               'm_rd_stb_o' => {
                                                 'intfc_name' => 'plug:wb_master[0]',
                                                 'intfc_port' => 'stb_o',
                                                 'range' => '',
                                                 'type' => 'output'
                                               },
                               'irq' => {
                                          'type' => 'output',
                                          'range' => '',
                                          'intfc_port' => 'int_o',
                                          'intfc_name' => 'plug:interrupt_peripheral[0]'
                                        },
                               'm_rd_ack_i' => {
                                                 'range' => '',
                                                 'type' => 'input',
                                                 'intfc_name' => 'plug:wb_master[0]',
                                                 'intfc_port' => 'ack_i'
                                               },
                               's_cti_i' => {
                                              'intfc_port' => 'cti_i',
                                              'intfc_name' => 'plug:wb_slave[0]',
                                              'type' => 'input',
                                              'range' => 'TAGw-1     :   0'
                                            },
                               'm_wr_we_o' => {
                                                'intfc_name' => 'plug:wb_master[1]',
                                                'intfc_port' => 'we_o',
                                                'range' => '',
                                                'type' => 'output'
                                              },
                               'm_rd_cyc_o' => {
                                                 'range' => '',
                                                 'type' => 'output',
                                                 'intfc_name' => 'plug:wb_master[0]',
                                                 'intfc_port' => 'cyc_o'
                                               },
                               'm_wr_dat_o' => {
                                                 'intfc_port' => 'dat_o',
                                                 'intfc_name' => 'plug:wb_master[1]',
                                                 'type' => 'output',
                                                 'range' => 'Dw-1            :   0'
                                               },
                               's_cyc_i' => {
                                              'range' => '',
                                              'type' => 'input',
                                              'intfc_name' => 'plug:wb_slave[0]',
                                              'intfc_port' => 'cyc_i'
                                            },
                               'm_wr_ack_i' => {
                                                 'range' => '',
                                                 'type' => 'input',
                                                 'intfc_name' => 'plug:wb_master[1]',
                                                 'intfc_port' => 'ack_i'
                                               },
                               'clk' => {
                                          'intfc_port' => 'clk_i',
                                          'intfc_name' => 'plug:clk[0]',
                                          'type' => 'input',
                                          'range' => ''
                                        },
                               'm_rd_cti_o' => {
                                                 'range' => 'TAGw-1          :   0',
                                                 'type' => 'output',
                                                 'intfc_name' => 'plug:wb_master[0]',
                                                 'intfc_port' => 'cti_o'
                                               },
                               's_dat_o' => {
                                              'intfc_name' => 'plug:wb_slave[0]',
                                              'intfc_port' => 'dat_o',
                                              'range' => 'Dw-1       :   0',
                                              'type' => 'output'
                                            },
                               's_sel_i' => {
                                              'intfc_name' => 'plug:wb_slave[0]',
                                              'intfc_port' => 'sel_i',
                                              'range' => 'SELw-1     :   0',
                                              'type' => 'input'
                                            },
                               's_we_i' => {
                                             'type' => 'input',
                                             'range' => '',
                                             'intfc_port' => 'we_i',
                                             'intfc_name' => 'plug:wb_slave[0]'
                                           },
                               'm_wr_cyc_o' => {
                                                 'intfc_name' => 'plug:wb_master[1]',
                                                 'intfc_port' => 'cyc_o',
                                                 'range' => '',
                                                 'type' => 'output'
                                               },
                               'm_wr_cti_o' => {
                                                 'intfc_name' => 'plug:wb_master[1]',
                                                 'intfc_port' => 'cti_o',
                                                 'range' => 'TAGw-1          :   0',
                                                 'type' => 'output'
                                               },
                               'reset' => {
                                            'intfc_port' => 'reset_i',
                                            'intfc_name' => 'plug:reset[0]',
                                            'type' => 'input',
                                            'range' => ''
                                          },
                               'm_rd_dat_i' => {
                                                 'type' => 'input',
                                                 'range' => 'Dw-1           :  0',
                                                 'intfc_port' => 'dat_i',
                                                 'intfc_name' => 'plug:wb_master[0]'
                                               },
                               's_stb_i' => {
                                              'intfc_name' => 'plug:wb_slave[0]',
                                              'intfc_port' => 'stb_i',
                                              'range' => '',
                                              'type' => 'input'
                                            },
                               's_addr_i' => {
                                               'type' => 'input',
                                               'range' => 'S_Aw-1     :   0',
                                               'intfc_port' => 'adr_i',
                                               'intfc_name' => 'plug:wb_slave[0]'
                                             },
                               'm_rd_addr_o' => {
                                                  'range' => 'M_Aw-1          :   0',
                                                  'type' => 'output',
                                                  'intfc_name' => 'plug:wb_master[0]',
                                                  'intfc_port' => 'adr_o'
                                                },
                               's_dat_i' => {
                                              'range' => 'Dw-1       :   0',
                                              'type' => 'input',
                                              'intfc_name' => 'plug:wb_slave[0]',
                                              'intfc_port' => 'dat_i'
                                            },
                               'm_wr_stb_o' => {
                                                 'intfc_name' => 'plug:wb_master[1]',
                                                 'intfc_port' => 'stb_o',
                                                 'range' => '',
                                                 'type' => 'output'
                                               },
                               'm_wr_addr_o' => {
                                                  'intfc_port' => 'adr_o',
                                                  'intfc_name' => 'plug:wb_master[1]',
                                                  'type' => 'output',
                                                  'range' => 'M_Aw-1          :   0'
                                                },
                               'm_rd_we_o' => {
                                                'type' => 'output',
                                                'range' => '',
                                                'intfc_port' => 'we_o',
                                                'intfc_name' => 'plug:wb_master[0]'
                                              },
                               's_ack_o' => {
                                              'intfc_port' => 'ack_o',
                                              'intfc_name' => 'plug:wb_slave[0]',
                                              'type' => 'output',
                                              'range' => ''
                                            },
                               'm_wr_sel_o' => {
                                                 'intfc_name' => 'plug:wb_master[1]',
                                                 'intfc_port' => 'sel_o',
                                                 'range' => 'SELw-1          :   0',
                                                 'type' => 'output'
                                               }
                             },
                  'system_h' => '#define ${IP}_STATUS_REG   (*((volatile unsigned int *) ($BASE)))
#define ${IP}_BURST_SIZE_ADDR_REG  (*((volatile unsigned int *) ($BASE+4)))
 
 
#define ${IP}_CHANNEL   ${CHANNEL}
#define ${IP}_DATA_SIZE_ADDR_REG(channel)  (*((volatile unsigned int *) ($BASE+8+(channel<<5))))
#define ${IP}_RD_START_ADDR_REG(channel)   (*((volatile unsigned int *) ($BASE+12+(channel<<5))))
#define ${IP}_WR_START_ADDR_REG(channel)  (*((volatile unsigned int *) ($BASE+16+(channel<<5))))
 
 
// assign status= {rd_enable_binarry,wr_enable_binarry,channel_rd_is_active,channel_wr_is_active};
 
#define ${IP}_channel_is_busy(channel) ( (${IP}_STATUS_REG >> channel) & 0x1)
 
 
void ${IP}_initial (unsigned int burst_size) {
         ${IP}_BURST_SIZE_ADDR_REG  =  burst_size;
}
 
 
void ${IP}_transfer (unsigned int channel, unsigned int read_start_addr,  unsigned int data_size, unsigned int write_start_addr){
        while ( ${IP}_channel_is_busy(channel)); // wait until DMA  channel is busy
         ${IP}_RD_START_ADDR_REG(channel)  = read_start_addr;
         ${IP}_DATA_SIZE_ADDR_REG(channel)  =  data_size;
         ${IP}_WR_START_ADDR_REG(channel)  = write_start_addr;
}',
                  'description_pdf' => '/mpsoc/src_peripheral/DMA/DMA.pdf',
                  'unused' => {
                                'plug:wb_slave[0]' => [
                                                        'rty_o',
                                                        'bte_i',
                                                        'err_o',
                                                        'tag_i'
                                                      ],
                                'plug:wb_master[0]' => [
                                                         'err_i',
                                                         'dat_o',
                                                         'rty_i',
                                                         'bte_o',
                                                         'tag_o'
                                                       ],
                                'plug:wb_master[1]' => [
                                                         'err_i',
                                                         'dat_i',
                                                         'rty_i',
                                                         'bte_o',
                                                         'tag_o'
                                                       ]
                              }
                }, 'ip_gen' );

Line No.	Rev	Author	Line
1	34	alirezamon	`#######################################################################`
2			`## File: dma.IP`
3			`##`
4			`## Copyright (C) 2014-2016 Alireza Monemi`
5			`##`
6	38	alirezamon	`## This file is part of ProNoC 1.8.0`
7	34	alirezamon	`##`
8			`## WARNING: THIS IS AN AUTO-GENERATED FILE. CHANGES TO IT`
9			`## MAY CAUSE UNEXPECTED BEHAIVOR.`
10			`################################################################################`
11
12	38	alirezamon	`$ipgen = bless( {`
13			`'description' => 'A wishbone bus round robin-based multi channel DMA (no byte enable is supported yet). The DMA supports burst data transaction.',`
14			`'modules' => {`
15			`'dma_multi_chan_wb' => {},`
16			`'shared_mem_fifos' => {},`
17			`'dma_single_wb' => {}`
18			`},`
19			`'plugs' => {`
20			`'clk' => {`
21			`'type' => 'num',`
22			`'value' => 1,`
23			`'0' => {`
24			`'name' => 'clk'`
25			`},`
26			`'clk' => {}`
27			`},`
28			`'wb_slave' => {`
29			`'value' => 1,`
30			`'wb_slave' => {},`
31			`'type' => 'num',`
32			`'0' => {`
33			`'width' => 10,`
34			`'addr' => '0x9300_0000 0x93ff_ffff Memory Controller',`
35			`'name' => 'wb_slave'`
36			`}`
37			`},`
38			`'interrupt_peripheral' => {`
39			`'value' => 1,`
40			`'interrupt_peripheral' => {},`
41			`'type' => 'num',`
42			`'0' => {`
43			`'name' => 'interrupt_peripheral'`
44			`}`
45			`},`
46			`'wb_master' => {`
47			`'1' => {`
48			`'name' => 'wb_wr'`
49			`},`
50			`'wb_master' => {},`
51			`'value' => 2,`
52			`'type' => 'num',`
53			`'0' => {`
54			`'name' => 'wb_rd'`
55			`}`
56	34	alirezamon	`},`
57	38	alirezamon	`'reset' => {`
58			`'type' => 'num',`
59			`'reset' => {},`
60			`'value' => 1,`
61			`'0' => {`
62			`'name' => 'reset'`
63			`}`
64			`}`
65			`},`
66			`'ports_order' => [`
67			`'reset',`
68			`'clk',`
69			`'s_dat_i',`
70			`'s_sel_i',`
71			`'s_addr_i',`
72			`'s_cti_i',`
73			`'s_stb_i',`
74			`'s_cyc_i',`
75			`'s_we_i',`
76			`'s_dat_o',`
77			`'s_ack_o',`
78			`'m_rd_sel_o',`
79			`'m_rd_addr_o',`
80			`'m_rd_cti_o',`
81			`'m_rd_stb_o',`
82			`'m_rd_cyc_o',`
83			`'m_rd_we_o',`
84			`'m_rd_dat_i',`
85			`'m_rd_ack_i',`
86			`'m_wr_sel_o',`
87			`'m_wr_dat_o',`
88			`'m_wr_addr_o',`
89			`'m_wr_cti_o',`
90			`'m_wr_stb_o',`
91			`'m_wr_cyc_o',`
92			`'m_wr_we_o',`
93			`'m_wr_ack_i',`
94			`'irq'`
95			`],`
96			`'parameters_order' => [`
97			`'CHANNEL',`
98			`'MAX_TRANSACTION_WIDTH',`
99			`'MAX_BURST_SIZE',`
100			`'FIFO_B',`
101			`'DEBUG_EN',`
102			`'Dw',`
103			`'S_Aw',`
104			`'M_Aw',`
105			`'TAGw',`
106			`'SELw'`
107			`],`
108			`'ip_name' => 'dma',`
109			`'file_name' => '/home/alireza/mywork/mpsoc/src_peripheral/DMA/dma_multi_channel_wb.v',`
110			`'hdl_files' => [`
111			`'/mpsoc/src_noc/main_comp.v',`
112			`'/mpsoc/src_noc/arbiter.v',`
113			`'/mpsoc/src_peripheral/DMA/dma_multi_channel_wb.v',`
114			`'/mpsoc/src_noc/flit_buffer.v'`
115			`],`
116			`'version' => 4,`
117			`'category' => 'DMA',`
118			`'module_name' => 'dma_multi_chan_wb',`
119			`'parameters' => {`
120			`'M_Aw' => {`
121			`'redefine_param' => 1,`
122			`'type' => 'Fixed',`
123			`'default' => '32',`
124			`'content' => '',`
125			`'info' => 'Parameter',`
126			`'global_param' => 'Parameter'`
127			`},`
128			`'CHANNEL' => {`
129			`'global_param' => 'Parameter',`
130			`'info' => 'Number of DMA channels.`
131			`In case there are multiple active DMA channels, Each time one single active DMA channel get access to the wishbone bus using round robin arbiter. The Wishbone bus is granted for the winter channel until its FIFO is not full and the number of sent data is smaller than the burst size.',`
132			`'redefine_param' => 1,`
133			`'type' => 'Spin-button',`
134			`'default' => '1',`
135			`'content' => '1,32,1'`
136			`},`
137			`'SELw' => {`
138			`'info' => 'Parameter',`
139			`'global_param' => 'Parameter',`
140			`'redefine_param' => 1,`
141			`'default' => '4',`
142			`'type' => 'Fixed',`
143			`'content' => ''`
144			`},`
145			`'Dw' => {`
146			`'global_param' => 'Parameter',`
147			`'info' => 'Wishbone bus Data size in bit',`
148			`'redefine_param' => 1,`
149			`'type' => 'Spin-button',`
150			`'default' => '32',`
151			`'content' => '8,1024,8'`
152			`},`
153			`'FIFO_B' => {`
154			`'global_param' => 'Parameter',`
155			`'info' => 'Channel FIFO size in words.`
156	34	alirezamon	`All channels will share same FPGA block RAM. Hence, the total needed Block RAM words is the multiplication of channel num in channel FIFO size.`
157
158			`',`
159	38	alirezamon	`'content' => '2,4,8,16,32,64,128,256,512,1024,2048',`
160			`'default' => '4',`
161			`'type' => 'Combo-box',`
162			`'redefine_param' => 1`
163			`},`
164			`'MAX_BURST_SIZE' => {`
165			`'global_param' => 'Parameter',`
166			`'info' => 'Maximum burst size in words.`
167			`The wishbone bus will be released each time one burst is completed or when the internal FIFO becomes full. The bus will be released for one clock cycle. Then in case, there are other active channels, another active channel will get access to the bus using round robin arbiter. This process will be continued until all desired data is transferred. ',`
168			`'content' => '2,4,8,16,32,64,128,256,512,1024,2048',`
169	34	alirezamon	`'redefine_param' => 1,`
170	38	alirezamon	`'type' => 'Combo-box',`
171			`'default' => '256'`
172	34	alirezamon	`},`
173	38	alirezamon	`'DEBUG_EN' => {`
174			`'content' => '',`
175			`'redefine_param' => 1,`
176			`'type' => 'Fixed',`
177			`'default' => '1',`
178			`'global_param' => 'Parameter',`
179			`'info' => 'Parameter'`
180			`},`
181			`'TAGw' => {`
182			`'default' => '3',`
183			`'type' => 'Fixed',`
184			`'redefine_param' => 1,`
185			`'content' => '',`
186			`'info' => 'Parameter',`
187			`'global_param' => 'Parameter'`
188	34	alirezamon	`},`
189	38	alirezamon	`'S_Aw' => {`
190			`'info' => 'Parameter',`
191			`'global_param' => 'Parameter',`
192			`'type' => 'Fixed',`
193			`'default' => '8',`
194			`'redefine_param' => 1,`
195			`'content' => ''`
196			`},`
197			`'MAX_TRANSACTION_WIDTH' => {`
198			`'default' => '10',`
199			`'type' => 'Spin-button',`
200			`'redefine_param' => 1,`
201			`'content' => '2,32,1',`
202			`'info' => 'The width of maximum transaction size in words.`
203			`The maximum data that can be sent via one DMA channel will be 2 power of MAX_DMA_TRANSACTION_WIDTH in words.',`
204			`'global_param' => 'Parameter'`
205			`}`
206			`},`
207			`'gui_status' => {`
208			`'timeout' => 0,`
209			`'status' => 'ideal'`
210			`},`
211			`'ports' => {`
212			`'m_rd_sel_o' => {`
213			`'intfc_name' => 'plug:wb_master[0]',`
214			`'intfc_port' => 'sel_o',`
215			`'range' => 'SELw-1 : 0',`
216			`'type' => 'output'`
217			`},`
218			`'m_rd_stb_o' => {`
219			`'intfc_name' => 'plug:wb_master[0]',`
220			`'intfc_port' => 'stb_o',`
221			`'range' => '',`
222			`'type' => 'output'`
223			`},`
224			`'irq' => {`
225			`'type' => 'output',`
226			`'range' => '',`
227			`'intfc_port' => 'int_o',`
228			`'intfc_name' => 'plug:interrupt_peripheral[0]'`
229			`},`
230			`'m_rd_ack_i' => {`
231			`'range' => '',`
232			`'type' => 'input',`
233			`'intfc_name' => 'plug:wb_master[0]',`
234			`'intfc_port' => 'ack_i'`
235			`},`
236			`'s_cti_i' => {`
237			`'intfc_port' => 'cti_i',`
238			`'intfc_name' => 'plug:wb_slave[0]',`
239			`'type' => 'input',`
240			`'range' => 'TAGw-1 : 0'`
241			`},`
242			`'m_wr_we_o' => {`
243			`'intfc_name' => 'plug:wb_master[1]',`
244			`'intfc_port' => 'we_o',`
245			`'range' => '',`
246			`'type' => 'output'`
247			`},`
248			`'m_rd_cyc_o' => {`
249			`'range' => '',`
250			`'type' => 'output',`
251			`'intfc_name' => 'plug:wb_master[0]',`
252			`'intfc_port' => 'cyc_o'`
253			`},`
254			`'m_wr_dat_o' => {`
255			`'intfc_port' => 'dat_o',`
256			`'intfc_name' => 'plug:wb_master[1]',`
257			`'type' => 'output',`
258			`'range' => 'Dw-1 : 0'`
259			`},`
260			`'s_cyc_i' => {`
261			`'range' => '',`
262			`'type' => 'input',`
263			`'intfc_name' => 'plug:wb_slave[0]',`
264			`'intfc_port' => 'cyc_i'`
265			`},`
266			`'m_wr_ack_i' => {`
267			`'range' => '',`
268			`'type' => 'input',`
269			`'intfc_name' => 'plug:wb_master[1]',`
270			`'intfc_port' => 'ack_i'`
271			`},`
272			`'clk' => {`
273			`'intfc_port' => 'clk_i',`
274			`'intfc_name' => 'plug:clk[0]',`
275			`'type' => 'input',`
276			`'range' => ''`
277			`},`
278			`'m_rd_cti_o' => {`
279			`'range' => 'TAGw-1 : 0',`
280			`'type' => 'output',`
281			`'intfc_name' => 'plug:wb_master[0]',`
282			`'intfc_port' => 'cti_o'`
283			`},`
284			`'s_dat_o' => {`
285			`'intfc_name' => 'plug:wb_slave[0]',`
286			`'intfc_port' => 'dat_o',`
287			`'range' => 'Dw-1 : 0',`
288			`'type' => 'output'`
289			`},`
290			`'s_sel_i' => {`
291			`'intfc_name' => 'plug:wb_slave[0]',`
292			`'intfc_port' => 'sel_i',`
293			`'range' => 'SELw-1 : 0',`
294			`'type' => 'input'`
295			`},`
296			`'s_we_i' => {`
297			`'type' => 'input',`
298			`'range' => '',`
299			`'intfc_port' => 'we_i',`
300			`'intfc_name' => 'plug:wb_slave[0]'`
301			`},`
302			`'m_wr_cyc_o' => {`
303			`'intfc_name' => 'plug:wb_master[1]',`
304			`'intfc_port' => 'cyc_o',`
305			`'range' => '',`
306			`'type' => 'output'`
307			`},`
308			`'m_wr_cti_o' => {`
309			`'intfc_name' => 'plug:wb_master[1]',`
310			`'intfc_port' => 'cti_o',`
311			`'range' => 'TAGw-1 : 0',`
312			`'type' => 'output'`
313			`},`
314			`'reset' => {`
315			`'intfc_port' => 'reset_i',`
316			`'intfc_name' => 'plug:reset[0]',`
317			`'type' => 'input',`
318			`'range' => ''`
319			`},`
320			`'m_rd_dat_i' => {`
321			`'type' => 'input',`
322			`'range' => 'Dw-1 : 0',`
323			`'intfc_port' => 'dat_i',`
324			`'intfc_name' => 'plug:wb_master[0]'`
325			`},`
326			`'s_stb_i' => {`
327			`'intfc_name' => 'plug:wb_slave[0]',`
328			`'intfc_port' => 'stb_i',`
329			`'range' => '',`
330			`'type' => 'input'`
331			`},`
332			`'s_addr_i' => {`
333			`'type' => 'input',`
334			`'range' => 'S_Aw-1 : 0',`
335			`'intfc_port' => 'adr_i',`
336			`'intfc_name' => 'plug:wb_slave[0]'`
337			`},`
338			`'m_rd_addr_o' => {`
339			`'range' => 'M_Aw-1 : 0',`
340			`'type' => 'output',`
341			`'intfc_name' => 'plug:wb_master[0]',`
342			`'intfc_port' => 'adr_o'`
343			`},`
344			`'s_dat_i' => {`
345			`'range' => 'Dw-1 : 0',`
346			`'type' => 'input',`
347			`'intfc_name' => 'plug:wb_slave[0]',`
348			`'intfc_port' => 'dat_i'`
349			`},`
350			`'m_wr_stb_o' => {`
351			`'intfc_name' => 'plug:wb_master[1]',`
352			`'intfc_port' => 'stb_o',`
353			`'range' => '',`
354			`'type' => 'output'`
355			`},`
356			`'m_wr_addr_o' => {`
357			`'intfc_port' => 'adr_o',`
358			`'intfc_name' => 'plug:wb_master[1]',`
359			`'type' => 'output',`
360			`'range' => 'M_Aw-1 : 0'`
361			`},`
362			`'m_rd_we_o' => {`
363			`'type' => 'output',`
364			`'range' => '',`
365			`'intfc_port' => 'we_o',`
366			`'intfc_name' => 'plug:wb_master[0]'`
367			`},`
368			`'s_ack_o' => {`
369			`'intfc_port' => 'ack_o',`
370			`'intfc_name' => 'plug:wb_slave[0]',`
371			`'type' => 'output',`
372			`'range' => ''`
373			`},`
374			`'m_wr_sel_o' => {`
375			`'intfc_name' => 'plug:wb_master[1]',`
376			`'intfc_port' => 'sel_o',`
377			`'range' => 'SELw-1 : 0',`
378			`'type' => 'output'`
379			`}`
380			`},`
381			`'system_h' => '#define ${IP}_STATUS_REG (((volatile unsigned int ) ($BASE)))`
382	34	alirezamon	`#define ${IP}_BURST_SIZE_ADDR_REG (((volatile unsigned int ) ($BASE+4)))`
383
384
385			`#define ${IP}_CHANNEL ${CHANNEL}`
386			`#define ${IP}_DATA_SIZE_ADDR_REG(channel) (((volatile unsigned int ) ($BASE+8+(channel<<5))))`
387			`#define ${IP}_RD_START_ADDR_REG(channel) (((volatile unsigned int ) ($BASE+12+(channel<<5))))`
388			`#define ${IP}_WR_START_ADDR_REG(channel) (((volatile unsigned int ) ($BASE+16+(channel<<5))))`
389
390
391			`// assign status= {rd_enable_binarry,wr_enable_binarry,channel_rd_is_active,channel_wr_is_active};`
392
393			`#define ${IP}_channel_is_busy(channel) ( (${IP}_STATUS_REG >> channel) & 0x1)`
394
395
396			`void ${IP}_initial (unsigned int burst_size) {`
397			`${IP}_BURST_SIZE_ADDR_REG = burst_size;`
398			`}`
399
400
401			`void ${IP}_transfer (unsigned int channel, unsigned int read_start_addr, unsigned int data_size, unsigned int write_start_addr){`
402			`while ( ${IP}_channel_is_busy(channel)); // wait until DMA channel is busy`
403			`${IP}_RD_START_ADDR_REG(channel) = read_start_addr;`
404			`${IP}_DATA_SIZE_ADDR_REG(channel) = data_size;`
405			`${IP}_WR_START_ADDR_REG(channel) = write_start_addr;`
406	38	alirezamon	`}',`
407			`'description_pdf' => '/mpsoc/src_peripheral/DMA/DMA.pdf',`
408			`'unused' => {`
409			`'plug:wb_slave[0]' => [`
410			`'rty_o',`
411			`'bte_i',`
412			`'err_o',`
413			`'tag_i'`
414			`],`
415			`'plug:wb_master[0]' => [`
416			`'err_i',`
417			`'dat_o',`
418			`'rty_i',`
419			`'bte_o',`
420			`'tag_o'`
421			`],`
422			`'plug:wb_master[1]' => [`
423			`'err_i',`
424			`'dat_i',`
425			`'rty_i',`
426			`'bte_o',`
427			`'tag_o'`
428			`]`
429			`}`
430			`}, 'ip_gen' );`

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[/] [an-fpga-implementation-of-low-latency-noc-based-mpsoc/] [trunk/] [mpsoc/] [perl_gui/] [lib/] [ip/] [DMA/] [dma.IP] - Blame information for rev 38