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[/] [an-fpga-implementation-of-low-latency-noc-based-mpsoc/] [trunk/] [mpsoc/] [perl_gui/] [lib/] [ip/] [DMA/] [dma.IP] - Blame information for rev 54

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#######################################################################
##      File: dma.IP
##
##      Copyright (C) 2014-2019  Alireza Monemi
##
##      This file is part of ProNoC 1.9.1
##
##      WARNING: THIS IS AN AUTO-GENERATED FILE. CHANGES TO IT
##      MAY CAUSE UNEXPECTED BEHAIVOR.
################################################################################
 
$ipgen = bless( {
                  'system_h' => '#define ${IP}_STATUS_REG   (*((volatile unsigned int *) ($BASE)))
#define ${IP}_BURST_SIZE_ADDR_REG  (*((volatile unsigned int *) ($BASE+4)))
 
#define ${IP}_chanel    ${chanel}
#define ${IP}_DATA_SIZE_ADDR_REG(chanel)  (*((volatile unsigned int *) ($BASE+8+(chanel<<5))))
#define ${IP}_RD_START_ADDR_REG(chanel)   (*((volatile unsigned int *) ($BASE+12+(chanel<<5))))
#define ${IP}_WR_START_ADDR_REG(chanel)  (*((volatile unsigned int *) ($BASE+16+(chanel<<5))))
 
// assign status= {rd_enable_binarry,wr_enable_binarry,chanel_rd_is_active,chanel_wr_is_active};
 
#define ${IP}_chanel_is_busy(chanel) ( (${IP}_STATUS_REG >> chanel) & 0x1)
 
void ${IP}_initial (unsigned int burst_size) ;
void ${IP}_transfer (unsigned int chanel, unsigned int read_start_addr,  unsigned int data_size, unsigned int write_start_addr);',
                  'ports_order' => [
                                     'reset',
                                     'clk',
                                     's_dat_i',
                                     's_sel_i',
                                     's_addr_i',
                                     's_cti_i',
                                     's_stb_i',
                                     's_cyc_i',
                                     's_we_i',
                                     's_dat_o',
                                     's_ack_o',
                                     'm_rd_sel_o',
                                     'm_rd_addr_o',
                                     'm_rd_cti_o',
                                     'm_rd_stb_o',
                                     'm_rd_cyc_o',
                                     'm_rd_we_o',
                                     'm_rd_dat_i',
                                     'm_rd_ack_i',
                                     'm_wr_sel_o',
                                     'm_wr_dat_o',
                                     'm_wr_addr_o',
                                     'm_wr_cti_o',
                                     'm_wr_stb_o',
                                     'm_wr_cyc_o',
                                     'm_wr_we_o',
                                     'm_wr_ack_i',
                                     'irq'
                                   ],
                  'file_name' => 'mpsoc/rtl/src_peripheral/DMA/dma_multi_chanel_wb.v',
                  'unused' => {
                                'plug:wb_slave[0]' => [
                                                        'bte_i',
                                                        'rty_o',
                                                        'err_o',
                                                        'tag_i'
                                                      ],
                                'plug:wb_master[1]' => [
                                                         'tag_o',
                                                         'err_i',
                                                         'dat_i',
                                                         'bte_o',
                                                         'rty_i'
                                                       ],
                                'plug:wb_master[0]' => [
                                                         'tag_o',
                                                         'err_i',
                                                         'dat_o',
                                                         'bte_o',
                                                         'rty_i'
                                                       ]
                              },
                  'parameters_order' => [
                                          'chanel',
                                          'MAX_TRANSACTION_WIDTH',
                                          'MAX_BURST_SIZE',
                                          'FIFO_B',
                                          'DEBUG_EN',
                                          'Dw',
                                          'S_Aw',
                                          'M_Aw',
                                          'TAGw',
                                          'SELw'
                                        ],
                  'module_name' => 'dma_multi_chan_wb',
                  'description_pdf' => '/mpsoc/rtl/src_peripheral/DMA/DMA.pdf',
                  'category' => 'DMA',
                  'plugs' => {
                               'interrupt_peripheral' => {
                                                           'value' => 1,
                                                           'type' => 'num',
                                                           '0' => {
                                                                    'name' => 'interrupt_peripheral'
                                                                  },
                                                           'interrupt_peripheral' => {}
                                                         },
                               'clk' => {
                                          'clk' => {},
                                          '0' => {
                                                   'name' => 'clk'
                                                 },
                                          'type' => 'num',
                                          'value' => 1
                                        },
                               'reset' => {
                                            'value' => 1,
                                            '0' => {
                                                     'name' => 'reset'
                                                   },
                                            'type' => 'num',
                                            'reset' => {}
                                          },
                               'wb_master' => {
                                                'wb_master' => {},
                                                'value' => 2,
                                                '1' => {
                                                         'name' => 'wb_wr'
                                                       },
                                                '0' => {
                                                         'name' => 'wb_rd'
                                                       },
                                                'type' => 'num'
                                              },
                               'wb_slave' => {
                                               'wb_slave' => {},
                                               'value' => 1,
                                               '0' => {
                                                        'addr' => '0x9300_0000  0x93ff_ffff             Memory Controller',
                                                        'name' => 'wb_slave',
                                                        'width' => 10
                                                      },
                                               'type' => 'num'
                                             }
                             },
                  'modules' => {
                                 'shared_mem_fifos' => {},
                                 'dma_multi_chan_wb' => {},
                                 'dma_single_wb' => {}
                               },
                  'ports' => {
                               'm_wr_addr_o' => {
                                                  'range' => 'M_Aw-1          :   0',
                                                  'type' => 'output',
                                                  'intfc_port' => 'adr_o',
                                                  'intfc_name' => 'plug:wb_master[1]'
                                                },
                               'irq' => {
                                          'intfc_name' => 'plug:interrupt_peripheral[0]',
                                          'type' => 'output',
                                          'intfc_port' => 'int_o',
                                          'range' => ''
                                        },
                               's_stb_i' => {
                                              'range' => '',
                                              'intfc_port' => 'stb_i',
                                              'type' => 'input',
                                              'intfc_name' => 'plug:wb_slave[0]'
                                            },
                               'm_rd_ack_i' => {
                                                 'range' => '',
                                                 'intfc_port' => 'ack_i',
                                                 'type' => 'input',
                                                 'intfc_name' => 'plug:wb_master[0]'
                                               },
                               's_cyc_i' => {
                                              'intfc_name' => 'plug:wb_slave[0]',
                                              'range' => '',
                                              'type' => 'input',
                                              'intfc_port' => 'cyc_i'
                                            },
                               'm_rd_dat_i' => {
                                                 'type' => 'input',
                                                 'intfc_port' => 'dat_i',
                                                 'range' => 'Dw-1           :  0',
                                                 'intfc_name' => 'plug:wb_master[0]'
                                               },
                               's_ack_o' => {
                                              'range' => '',
                                              'type' => 'output',
                                              'intfc_port' => 'ack_o',
                                              'intfc_name' => 'plug:wb_slave[0]'
                                            },
                               's_dat_o' => {
                                              'range' => 'Dw-1       :   0',
                                              'type' => 'output',
                                              'intfc_port' => 'dat_o',
                                              'intfc_name' => 'plug:wb_slave[0]'
                                            },
                               'm_rd_cti_o' => {
                                                 'intfc_name' => 'plug:wb_master[0]',
                                                 'type' => 'output',
                                                 'intfc_port' => 'cti_o',
                                                 'range' => 'TAGw-1          :   0'
                                               },
                               's_cti_i' => {
                                              'intfc_name' => 'plug:wb_slave[0]',
                                              'type' => 'input',
                                              'intfc_port' => 'cti_i',
                                              'range' => 'TAGw-1     :   0'
                                            },
                               's_sel_i' => {
                                              'intfc_port' => 'sel_i',
                                              'type' => 'input',
                                              'range' => 'SELw-1     :   0',
                                              'intfc_name' => 'plug:wb_slave[0]'
                                            },
                               's_dat_i' => {
                                              'intfc_name' => 'plug:wb_slave[0]',
                                              'range' => 'Dw-1       :   0',
                                              'intfc_port' => 'dat_i',
                                              'type' => 'input'
                                            },
                               'm_wr_stb_o' => {
                                                 'intfc_port' => 'stb_o',
                                                 'type' => 'output',
                                                 'range' => '',
                                                 'intfc_name' => 'plug:wb_master[1]'
                                               },
                               's_we_i' => {
                                             'type' => 'input',
                                             'intfc_port' => 'we_i',
                                             'range' => '',
                                             'intfc_name' => 'plug:wb_slave[0]'
                                           },
                               'm_wr_we_o' => {
                                                'range' => '',
                                                'intfc_port' => 'we_o',
                                                'type' => 'output',
                                                'intfc_name' => 'plug:wb_master[1]'
                                              },
                               'm_wr_dat_o' => {
                                                 'intfc_name' => 'plug:wb_master[1]',
                                                 'range' => 'Dw-1            :   0',
                                                 'type' => 'output',
                                                 'intfc_port' => 'dat_o'
                                               },
                               'clk' => {
                                          'range' => '',
                                          'type' => 'input',
                                          'intfc_port' => 'clk_i',
                                          'intfc_name' => 'plug:clk[0]'
                                        },
                               'm_wr_ack_i' => {
                                                 'intfc_name' => 'plug:wb_master[1]',
                                                 'range' => '',
                                                 'intfc_port' => 'ack_i',
                                                 'type' => 'input'
                                               },
                               'm_rd_cyc_o' => {
                                                 'range' => '',
                                                 'type' => 'output',
                                                 'intfc_port' => 'cyc_o',
                                                 'intfc_name' => 'plug:wb_master[0]'
                                               },
                               'm_wr_cyc_o' => {
                                                 'intfc_name' => 'plug:wb_master[1]',
                                                 'intfc_port' => 'cyc_o',
                                                 'type' => 'output',
                                                 'range' => ''
                                               },
                               's_addr_i' => {
                                               'type' => 'input',
                                               'intfc_port' => 'adr_i',
                                               'range' => 'S_Aw-1     :   0',
                                               'intfc_name' => 'plug:wb_slave[0]'
                                             },
                               'm_rd_sel_o' => {
                                                 'intfc_port' => 'sel_o',
                                                 'type' => 'output',
                                                 'range' => 'SELw-1          :   0',
                                                 'intfc_name' => 'plug:wb_master[0]'
                                               },
                               'm_wr_sel_o' => {
                                                 'intfc_port' => 'sel_o',
                                                 'type' => 'output',
                                                 'range' => 'SELw-1          :   0',
                                                 'intfc_name' => 'plug:wb_master[1]'
                                               },
                               'm_rd_we_o' => {
                                                'range' => '',
                                                'intfc_port' => 'we_o',
                                                'type' => 'output',
                                                'intfc_name' => 'plug:wb_master[0]'
                                              },
                               'm_wr_cti_o' => {
                                                 'intfc_name' => 'plug:wb_master[1]',
                                                 'range' => 'TAGw-1          :   0',
                                                 'intfc_port' => 'cti_o',
                                                 'type' => 'output'
                                               },
                               'm_rd_stb_o' => {
                                                 'range' => '',
                                                 'intfc_port' => 'stb_o',
                                                 'type' => 'output',
                                                 'intfc_name' => 'plug:wb_master[0]'
                                               },
                               'reset' => {
                                            'intfc_name' => 'plug:reset[0]',
                                            'range' => '',
                                            'intfc_port' => 'reset_i',
                                            'type' => 'input'
                                          },
                               'm_rd_addr_o' => {
                                                  'intfc_name' => 'plug:wb_master[0]',
                                                  'range' => 'M_Aw-1          :   0',
                                                  'intfc_port' => 'adr_o',
                                                  'type' => 'output'
                                                }
                             },
                  'version' => 6,
                  'hdl_files' => [
                                   '/mpsoc/rtl/main_comp.v',
                                   '/mpsoc/rtl/arbiter.v',
                                                                   '/mpsoc/rtl/pronoc_def.v',
                                   '/mpsoc/rtl/src_peripheral/DMA/dma_multi_chanel_wb.v'
                                 ],
                  'ip_name' => 'dma',
                  'parameters' => {
                                    'TAGw' => {
                                                'global_param' => 'Localparam',
                                                'redefine_param' => 1,
                                                'info' => 'Parameter',
                                                'default' => '3',
                                                'type' => 'Fixed',
                                                'content' => ''
                                              },
                                    'M_Aw' => {
                                                'redefine_param' => 1,
                                                'global_param' => 'Localparam',
                                                'info' => 'Parameter',
                                                'default' => '32',
                                                'content' => '',
                                                'type' => 'Fixed'
                                              },
                                    'FIFO_B' => {
                                                  'default' => '4',
                                                  'content' => '2,4,8,16,32,64,128,256,512,1024,2048',
                                                  'type' => 'Combo-box',
                                                  'redefine_param' => 1,
                                                  'global_param' => 'Localparam',
                                                  'info' => 'chanel  FIFO size in words.
All chanels will share same FPGA block RAM. Hence, the total needed Block RAM words is the multiplication of chanel num in chanel FIFO size.
 
'
                                                },
                                    'MAX_BURST_SIZE' => {
                                                          'content' => '2,4,8,16,32,64,128,256,512,1024,2048',
                                                          'type' => 'Combo-box',
                                                          'default' => '256',
                                                          'info' => 'Maximum burst size in words.
The wishbone bus will be released each time one burst is completed or when the internal FIFO becomes full.  The bus will be released for one clock cycle. Then in case, there are other active chanels, another active chanel will get access to the bus using round robin arbiter.  This process will be continued until all desired data is transferred. ',
                                                          'redefine_param' => 1,
                                                          'global_param' => 'Localparam'
                                                        },
                                    'S_Aw' => {
                                                'global_param' => 'Localparam',
                                                'redefine_param' => 1,
                                                'info' => 'Parameter',
                                                'default' => '8',
                                                'type' => 'Fixed',
                                                'content' => ''
                                              },
                                    'MAX_TRANSACTION_WIDTH' => {
                                                                 'info' => 'The width of maximum transaction size in words.
The maximum data that can be sent via one DMA chanel will be 2 power of MAX_DMA_TRANSACTION_WIDTH in words.',
                                                                 'global_param' => 'Localparam',
                                                                 'redefine_param' => 1,
                                                                 'type' => 'Spin-button',
                                                                 'content' => '2,32,1',
                                                                 'default' => '10'
                                                               },
                                    'DEBUG_EN' => {
                                                    'default' => '1',
                                                    'type' => 'Fixed',
                                                    'content' => '',
                                                    'global_param' => 'Localparam',
                                                    'redefine_param' => 1,
                                                    'info' => 'Parameter'
                                                  },
                                    'chanel' => {
                                                   'content' => '1,32,1',
                                                   'type' => 'Spin-button',
                                                   'default' => '1',
                                                   'info' => 'Number of DMA chanels.
In case there are multiple active DMA chanels,  Each time one single active DMA chanel get access to the wishbone bus using round robin arbiter. The Wishbone bus is granted for the winter chanel until its FIFO is not full and the number of sent data is smaller than the burst size.',
                                                   'redefine_param' => 1,
                                                   'global_param' => 'Localparam'
                                                 },
                                    'SELw' => {
                                                'global_param' => 'Localparam',
                                                'redefine_param' => 1,
                                                'info' => 'Parameter',
                                                'default' => '4',
                                                'type' => 'Fixed',
                                                'content' => ''
                                              },
                                    'Dw' => {
                                              'info' => 'Wishbone bus Data size in bit',
                                              'redefine_param' => 1,
                                              'global_param' => 'Localparam',
                                              'content' => '8,1024,8',
                                              'type' => 'Spin-button',
                                              'default' => '32'
                                            }
                                  },
                  'system_c' => 'void ${IP}_initial (unsigned int burst_size) {
         ${IP}_BURST_SIZE_ADDR_REG  =  burst_size;
}
 
 
void ${IP}_transfer (unsigned int chanel, unsigned int read_start_addr,  unsigned int data_size, unsigned int write_start_addr){
        while ( ${IP}_chanel_is_busy(chanel)); // wait until DMA  chanel is busy
         ${IP}_RD_START_ADDR_REG(chanel)  = read_start_addr;
         ${IP}_DATA_SIZE_ADDR_REG(chanel)  =  data_size;
         ${IP}_WR_START_ADDR_REG(chanel)  = write_start_addr;
}',
                  'gui_status' => {
                                    'status' => 'ideal',
                                    'timeout' => 0
                                  },
                  'description' => 'A wishbone bus round robin-based  multi chanel DMA (no byte enable is supported yet). The DMA supports burst data transaction.'
                }, 'ip_gen' );

Line No.	Rev	Author	Line
1	34	alirezamon	`#######################################################################`
2			`## File: dma.IP`
3			`##`
4	48	alirezamon	`## Copyright (C) 2014-2019 Alireza Monemi`
5	34	alirezamon	`##`
6	48	alirezamon	`## This file is part of ProNoC 1.9.1`
7	34	alirezamon	`##`
8			`## WARNING: THIS IS AN AUTO-GENERATED FILE. CHANGES TO IT`
9			`## MAY CAUSE UNEXPECTED BEHAIVOR.`
10			`################################################################################`
11
12	38	alirezamon	`$ipgen = bless( {`
13	48	alirezamon	`'system_h' => '#define ${IP}_STATUS_REG (((volatile unsigned int ) ($BASE)))`
14			`#define ${IP}_BURST_SIZE_ADDR_REG (((volatile unsigned int ) ($BASE+4)))`
15
16			`#define ${IP}_chanel ${chanel}`
17			`#define ${IP}_DATA_SIZE_ADDR_REG(chanel) (((volatile unsigned int ) ($BASE+8+(chanel<<5))))`
18			`#define ${IP}_RD_START_ADDR_REG(chanel) (((volatile unsigned int ) ($BASE+12+(chanel<<5))))`
19			`#define ${IP}_WR_START_ADDR_REG(chanel) (((volatile unsigned int ) ($BASE+16+(chanel<<5))))`
20
21			`// assign status= {rd_enable_binarry,wr_enable_binarry,chanel_rd_is_active,chanel_wr_is_active};`
22
23			`#define ${IP}_chanel_is_busy(chanel) ( (${IP}_STATUS_REG >> chanel) & 0x1)`
24
25			`void ${IP}_initial (unsigned int burst_size) ;`
26			`void ${IP}_transfer (unsigned int chanel, unsigned int read_start_addr, unsigned int data_size, unsigned int write_start_addr);',`
27	38	alirezamon	`'ports_order' => [`
28			`'reset',`
29			`'clk',`
30			`'s_dat_i',`
31			`'s_sel_i',`
32			`'s_addr_i',`
33			`'s_cti_i',`
34			`'s_stb_i',`
35			`'s_cyc_i',`
36			`'s_we_i',`
37			`'s_dat_o',`
38			`'s_ack_o',`
39			`'m_rd_sel_o',`
40			`'m_rd_addr_o',`
41			`'m_rd_cti_o',`
42			`'m_rd_stb_o',`
43			`'m_rd_cyc_o',`
44			`'m_rd_we_o',`
45			`'m_rd_dat_i',`
46			`'m_rd_ack_i',`
47			`'m_wr_sel_o',`
48			`'m_wr_dat_o',`
49			`'m_wr_addr_o',`
50			`'m_wr_cti_o',`
51			`'m_wr_stb_o',`
52			`'m_wr_cyc_o',`
53			`'m_wr_we_o',`
54			`'m_wr_ack_i',`
55			`'irq'`
56			`],`
57	48	alirezamon	`'file_name' => 'mpsoc/rtl/src_peripheral/DMA/dma_multi_chanel_wb.v',`
58			`'unused' => {`
59			`'plug:wb_slave[0]' => [`
60			`'bte_i',`
61			`'rty_o',`
62			`'err_o',`
63			`'tag_i'`
64			`],`
65			`'plug:wb_master[1]' => [`
66			`'tag_o',`
67			`'err_i',`
68			`'dat_i',`
69			`'bte_o',`
70			`'rty_i'`
71			`],`
72			`'plug:wb_master[0]' => [`
73			`'tag_o',`
74			`'err_i',`
75			`'dat_o',`
76			`'bte_o',`
77			`'rty_i'`
78			`]`
79			`},`
80	38	alirezamon	`'parameters_order' => [`
81	48	alirezamon	`'chanel',`
82	38	alirezamon	`'MAX_TRANSACTION_WIDTH',`
83			`'MAX_BURST_SIZE',`
84			`'FIFO_B',`
85			`'DEBUG_EN',`
86			`'Dw',`
87			`'S_Aw',`
88			`'M_Aw',`
89			`'TAGw',`
90			`'SELw'`
91			`],`
92	48	alirezamon	`'module_name' => 'dma_multi_chan_wb',`
93			`'description_pdf' => '/mpsoc/rtl/src_peripheral/DMA/DMA.pdf',`
94	38	alirezamon	`'category' => 'DMA',`
95	48	alirezamon	`'plugs' => {`
96			`'interrupt_peripheral' => {`
97			`'value' => 1,`
98			`'type' => 'num',`
99			`'0' => {`
100			`'name' => 'interrupt_peripheral'`
101			`},`
102			`'interrupt_peripheral' => {}`
103			`},`
104			`'clk' => {`
105			`'clk' => {},`
106			`'0' => {`
107			`'name' => 'clk'`
108	38	alirezamon	`},`
109	48	alirezamon	`'type' => 'num',`
110			`'value' => 1`
111			`},`
112			`'reset' => {`
113			`'value' => 1,`
114			`'0' => {`
115			`'name' => 'reset'`
116			`},`
117			`'type' => 'num',`
118			`'reset' => {}`
119			`},`
120			`'wb_master' => {`
121			`'wb_master' => {},`
122			`'value' => 2,`
123			`'1' => {`
124			`'name' => 'wb_wr'`
125			`},`
126			`'0' => {`
127			`'name' => 'wb_rd'`
128			`},`
129			`'type' => 'num'`
130	38	alirezamon	`},`
131	48	alirezamon	`'wb_slave' => {`
132			`'wb_slave' => {},`
133			`'value' => 1,`
134			`'0' => {`
135			`'addr' => '0x9300_0000 0x93ff_ffff Memory Controller',`
136			`'name' => 'wb_slave',`
137			`'width' => 10`
138			`},`
139			`'type' => 'num'`
140			`}`
141			`},`
142			`'modules' => {`
143			`'shared_mem_fifos' => {},`
144			`'dma_multi_chan_wb' => {},`
145			`'dma_single_wb' => {}`
146			`},`
147			`'ports' => {`
148			`'m_wr_addr_o' => {`
149			`'range' => 'M_Aw-1 : 0',`
150			`'type' => 'output',`
151			`'intfc_port' => 'adr_o',`
152			`'intfc_name' => 'plug:wb_master[1]'`
153	38	alirezamon	`},`
154			`'irq' => {`
155	48	alirezamon	`'intfc_name' => 'plug:interrupt_peripheral[0]',`
156	38	alirezamon	`'type' => 'output',`
157			`'intfc_port' => 'int_o',`
158	48	alirezamon	`'range' => ''`
159	38	alirezamon	`},`
160	48	alirezamon	`'s_stb_i' => {`
161			`'range' => '',`
162			`'intfc_port' => 'stb_i',`
163			`'type' => 'input',`
164			`'intfc_name' => 'plug:wb_slave[0]'`
165			`},`
166	38	alirezamon	`'m_rd_ack_i' => {`
167			`'range' => '',`
168	48	alirezamon	`'intfc_port' => 'ack_i',`
169	38	alirezamon	`'type' => 'input',`
170	48	alirezamon	`'intfc_name' => 'plug:wb_master[0]'`
171	38	alirezamon	`},`
172	48	alirezamon	`'s_cyc_i' => {`
173	38	alirezamon	`'intfc_name' => 'plug:wb_slave[0]',`
174			`'range' => '',`
175			`'type' => 'input',`
176			`'intfc_port' => 'cyc_i'`
177			`},`
178	48	alirezamon	`'m_rd_dat_i' => {`
179	38	alirezamon	`'type' => 'input',`
180	48	alirezamon	`'intfc_port' => 'dat_i',`
181			`'range' => 'Dw-1 : 0',`
182			`'intfc_name' => 'plug:wb_master[0]'`
183	38	alirezamon	`},`
184	48	alirezamon	`'s_ack_o' => {`
185			`'range' => '',`
186			`'type' => 'output',`
187			`'intfc_port' => 'ack_o',`
188			`'intfc_name' => 'plug:wb_slave[0]'`
189			`},`
190			`'s_dat_o' => {`
191			`'range' => 'Dw-1 : 0',`
192			`'type' => 'output',`
193			`'intfc_port' => 'dat_o',`
194			`'intfc_name' => 'plug:wb_slave[0]'`
195			`},`
196	38	alirezamon	`'m_rd_cti_o' => {`
197	48	alirezamon	`'intfc_name' => 'plug:wb_master[0]',`
198	38	alirezamon	`'type' => 'output',`
199	48	alirezamon	`'intfc_port' => 'cti_o',`
200			`'range' => 'TAGw-1 : 0'`
201	38	alirezamon	`},`
202	48	alirezamon	`'s_cti_i' => {`
203	38	alirezamon	`'intfc_name' => 'plug:wb_slave[0]',`
204	48	alirezamon	`'type' => 'input',`
205			`'intfc_port' => 'cti_i',`
206			`'range' => 'TAGw-1 : 0'`
207	38	alirezamon	`},`
208			`'s_sel_i' => {`
209			`'intfc_port' => 'sel_i',`
210	48	alirezamon	`'type' => 'input',`
211	38	alirezamon	`'range' => 'SELw-1 : 0',`
212	48	alirezamon	`'intfc_name' => 'plug:wb_slave[0]'`
213			`},`
214			`'s_dat_i' => {`
215			`'intfc_name' => 'plug:wb_slave[0]',`
216			`'range' => 'Dw-1 : 0',`
217			`'intfc_port' => 'dat_i',`
218	38	alirezamon	`'type' => 'input'`
219			`},`
220	48	alirezamon	`'m_wr_stb_o' => {`
221			`'intfc_port' => 'stb_o',`
222			`'type' => 'output',`
223			`'range' => '',`
224			`'intfc_name' => 'plug:wb_master[1]'`
225			`},`
226	38	alirezamon	`'s_we_i' => {`
227			`'type' => 'input',`
228	48	alirezamon	`'intfc_port' => 'we_i',`
229	38	alirezamon	`'range' => '',`
230			`'intfc_name' => 'plug:wb_slave[0]'`
231			`},`
232	48	alirezamon	`'m_wr_we_o' => {`
233			`'range' => '',`
234			`'intfc_port' => 'we_o',`
235			`'type' => 'output',`
236			`'intfc_name' => 'plug:wb_master[1]'`
237			`},`
238			`'m_wr_dat_o' => {`
239	38	alirezamon	`'intfc_name' => 'plug:wb_master[1]',`
240	48	alirezamon	`'range' => 'Dw-1 : 0',`
241			`'type' => 'output',`
242			`'intfc_port' => 'dat_o'`
243	38	alirezamon	`},`
244	48	alirezamon	`'clk' => {`
245			`'range' => '',`
246			`'type' => 'input',`
247			`'intfc_port' => 'clk_i',`
248			`'intfc_name' => 'plug:clk[0]'`
249			`},`
250			`'m_wr_ack_i' => {`
251	38	alirezamon	`'intfc_name' => 'plug:wb_master[1]',`
252	48	alirezamon	`'range' => '',`
253			`'intfc_port' => 'ack_i',`
254			`'type' => 'input'`
255	38	alirezamon	`},`
256	48	alirezamon	`'m_rd_cyc_o' => {`
257			`'range' => '',`
258			`'type' => 'output',`
259			`'intfc_port' => 'cyc_o',`
260	38	alirezamon	`'intfc_name' => 'plug:wb_master[0]'`
261			`},`
262	48	alirezamon	`'m_wr_cyc_o' => {`
263			`'intfc_name' => 'plug:wb_master[1]',`
264			`'intfc_port' => 'cyc_o',`
265			`'type' => 'output',`
266			`'range' => ''`
267			`},`
268	38	alirezamon	`'s_addr_i' => {`
269			`'type' => 'input',`
270	48	alirezamon	`'intfc_port' => 'adr_i',`
271	38	alirezamon	`'range' => 'S_Aw-1 : 0',`
272			`'intfc_name' => 'plug:wb_slave[0]'`
273			`},`
274	48	alirezamon	`'m_rd_sel_o' => {`
275			`'intfc_port' => 'sel_o',`
276			`'type' => 'output',`
277			`'range' => 'SELw-1 : 0',`
278			`'intfc_name' => 'plug:wb_master[0]'`
279	38	alirezamon	`},`
280	48	alirezamon	`'m_wr_sel_o' => {`
281			`'intfc_port' => 'sel_o',`
282			`'type' => 'output',`
283			`'range' => 'SELw-1 : 0',`
284			`'intfc_name' => 'plug:wb_master[1]'`
285			`},`
286	38	alirezamon	`'m_rd_we_o' => {`
287			`'range' => '',`
288			`'intfc_port' => 'we_o',`
289	48	alirezamon	`'type' => 'output',`
290	38	alirezamon	`'intfc_name' => 'plug:wb_master[0]'`
291			`},`
292	48	alirezamon	`'m_wr_cti_o' => {`
293	38	alirezamon	`'intfc_name' => 'plug:wb_master[1]',`
294	48	alirezamon	`'range' => 'TAGw-1 : 0',`
295			`'intfc_port' => 'cti_o',`
296	38	alirezamon	`'type' => 'output'`
297	48	alirezamon	`},`
298			`'m_rd_stb_o' => {`
299			`'range' => '',`
300			`'intfc_port' => 'stb_o',`
301			`'type' => 'output',`
302			`'intfc_name' => 'plug:wb_master[0]'`
303			`},`
304			`'reset' => {`
305			`'intfc_name' => 'plug:reset[0]',`
306			`'range' => '',`
307			`'intfc_port' => 'reset_i',`
308			`'type' => 'input'`
309			`},`
310			`'m_rd_addr_o' => {`
311			`'intfc_name' => 'plug:wb_master[0]',`
312			`'range' => 'M_Aw-1 : 0',`
313			`'intfc_port' => 'adr_o',`
314			`'type' => 'output'`
315			`}`
316	38	alirezamon	`},`
317	48	alirezamon	`'version' => 6,`
318			`'hdl_files' => [`
319			`'/mpsoc/rtl/main_comp.v',`
320			`'/mpsoc/rtl/arbiter.v',`
321	54	alirezamon	`'/mpsoc/rtl/pronoc_def.v',`
322	48	alirezamon	`'/mpsoc/rtl/src_peripheral/DMA/dma_multi_chanel_wb.v'`
323			`],`
324			`'ip_name' => 'dma',`
325			`'parameters' => {`
326			`'TAGw' => {`
327			`'global_param' => 'Localparam',`
328			`'redefine_param' => 1,`
329			`'info' => 'Parameter',`
330			`'default' => '3',`
331			`'type' => 'Fixed',`
332			`'content' => ''`
333			`},`
334			`'M_Aw' => {`
335			`'redefine_param' => 1,`
336			`'global_param' => 'Localparam',`
337			`'info' => 'Parameter',`
338			`'default' => '32',`
339			`'content' => '',`
340			`'type' => 'Fixed'`
341			`},`
342			`'FIFO_B' => {`
343			`'default' => '4',`
344			`'content' => '2,4,8,16,32,64,128,256,512,1024,2048',`
345			`'type' => 'Combo-box',`
346			`'redefine_param' => 1,`
347			`'global_param' => 'Localparam',`
348			`'info' => 'chanel FIFO size in words.`
349			`All chanels will share same FPGA block RAM. Hence, the total needed Block RAM words is the multiplication of chanel num in chanel FIFO size.`
350	34	alirezamon
351	48	alirezamon	`'`
352			`},`
353			`'MAX_BURST_SIZE' => {`
354			`'content' => '2,4,8,16,32,64,128,256,512,1024,2048',`
355			`'type' => 'Combo-box',`
356			`'default' => '256',`
357			`'info' => 'Maximum burst size in words.`
358			`The wishbone bus will be released each time one burst is completed or when the internal FIFO becomes full. The bus will be released for one clock cycle. Then in case, there are other active chanels, another active chanel will get access to the bus using round robin arbiter. This process will be continued until all desired data is transferred. ',`
359			`'redefine_param' => 1,`
360			`'global_param' => 'Localparam'`
361			`},`
362			`'S_Aw' => {`
363			`'global_param' => 'Localparam',`
364			`'redefine_param' => 1,`
365			`'info' => 'Parameter',`
366			`'default' => '8',`
367			`'type' => 'Fixed',`
368			`'content' => ''`
369			`},`
370			`'MAX_TRANSACTION_WIDTH' => {`
371			`'info' => 'The width of maximum transaction size in words.`
372			`The maximum data that can be sent via one DMA chanel will be 2 power of MAX_DMA_TRANSACTION_WIDTH in words.',`
373			`'global_param' => 'Localparam',`
374			`'redefine_param' => 1,`
375			`'type' => 'Spin-button',`
376			`'content' => '2,32,1',`
377			`'default' => '10'`
378			`},`
379			`'DEBUG_EN' => {`
380			`'default' => '1',`
381			`'type' => 'Fixed',`
382			`'content' => '',`
383			`'global_param' => 'Localparam',`
384			`'redefine_param' => 1,`
385			`'info' => 'Parameter'`
386			`},`
387			`'chanel' => {`
388			`'content' => '1,32,1',`
389			`'type' => 'Spin-button',`
390			`'default' => '1',`
391			`'info' => 'Number of DMA chanels.`
392			`In case there are multiple active DMA chanels, Each time one single active DMA chanel get access to the wishbone bus using round robin arbiter. The Wishbone bus is granted for the winter chanel until its FIFO is not full and the number of sent data is smaller than the burst size.',`
393			`'redefine_param' => 1,`
394			`'global_param' => 'Localparam'`
395			`},`
396			`'SELw' => {`
397			`'global_param' => 'Localparam',`
398			`'redefine_param' => 1,`
399			`'info' => 'Parameter',`
400			`'default' => '4',`
401			`'type' => 'Fixed',`
402			`'content' => ''`
403			`},`
404			`'Dw' => {`
405			`'info' => 'Wishbone bus Data size in bit',`
406			`'redefine_param' => 1,`
407			`'global_param' => 'Localparam',`
408			`'content' => '8,1024,8',`
409			`'type' => 'Spin-button',`
410			`'default' => '32'`
411			`}`
412			`},`
413			`'system_c' => 'void ${IP}_initial (unsigned int burst_size) {`
414	34	alirezamon	`${IP}_BURST_SIZE_ADDR_REG = burst_size;`
415			`}`
416
417
418	48	alirezamon	`void ${IP}_transfer (unsigned int chanel, unsigned int read_start_addr, unsigned int data_size, unsigned int write_start_addr){`
419			`while ( ${IP}_chanel_is_busy(chanel)); // wait until DMA chanel is busy`
420			`${IP}_RD_START_ADDR_REG(chanel) = read_start_addr;`
421			`${IP}_DATA_SIZE_ADDR_REG(chanel) = data_size;`
422			`${IP}_WR_START_ADDR_REG(chanel) = write_start_addr;`
423	38	alirezamon	`}',`
424	48	alirezamon	`'gui_status' => {`
425			`'status' => 'ideal',`
426			`'timeout' => 0`
427			`},`
428			`'description' => 'A wishbone bus round robin-based multi chanel DMA (no byte enable is supported yet). The DMA supports burst data transaction.'`
429	38	alirezamon	`}, 'ip_gen' );`

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[/] [an-fpga-implementation-of-low-latency-noc-based-mpsoc/] [trunk/] [mpsoc/] [perl_gui/] [lib/] [ip/] [DMA/] [dma.IP] - Blame information for rev 54