URL https://opencores.org/ocsvn/an-fpga-implementation-of-low-latency-noc-based-mpsoc/an-fpga-implementation-of-low-latency-noc-based-mpsoc/trunk

Subversion Repositories an-fpga-implementation-of-low-latency-noc-based-mpsoc

[/] [an-fpga-implementation-of-low-latency-noc-based-mpsoc/] [trunk/] [mpsoc/] [perl_gui/] [lib/] [ip/] [Other/] [fout_sim.IP] - Blame information for rev 48

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#######################################################################
##      File: fout_sim.IP
##
##      Copyright (C) 2014-2019  Alireza Monemi
##
##      This file is part of ProNoC 1.9.1
##
##      WARNING: THIS IS AN AUTO-GENERATED FILE. CHANGES TO IT
##      MAY CAUSE UNEXPECTED BEHAVIOR.
################################################################################
 
$ipgen = bless( {
                  'version' => 29,
                  'sw_files' => [
                                  '/mpsoc/src_processor/src_lib/simple-printf'
                                ],
                  'modules' => {
                                 'fout_simulator' => {}
                               },
                  'ip_name' => 'fout_sim',
                  'module_name' => 'fout_simulator',
                  'parameters' => {
                                    'BUFFER_SIZE' => {
                                                       'content' => '10,1024,1',
                                                       'global_param' => 'Parameter',
                                                       'redefine_param' => 1,
                                                       'info' => 'Buffer width for getting for getting fle name.',
                                                       'type' => 'Spin-button',
                                                       'default' => '255  '
                                                     }
                                  },
                  'hdl_files_ticked' => [],
                  'ports' => {
                               's_we_i' => {
                                             'type' => 'input',
                                             'intfc_name' => 'plug:wb_slave[0]',
                                             'intfc_port' => 'we_i',
                                             'range' => ''
                                           },
                               's_cyc_i' => {
                                              'intfc_port' => 'cyc_i',
                                              'type' => 'input',
                                              'intfc_name' => 'plug:wb_slave[0]',
                                              'range' => ''
                                            },
                               's_ack_o' => {
                                              'intfc_port' => 'ack_o',
                                              'intfc_name' => 'plug:wb_slave[0]',
                                              'type' => 'output',
                                              'range' => ''
                                            },
                               's_addr_i' => {
                                               'range' => '2 : 0',
                                               'intfc_port' => 'adr_i',
                                               'intfc_name' => 'plug:wb_slave[0]',
                                               'type' => 'input'
                                             },
                               's_dat_o' => {
                                              'range' => '31       :   0',
                                              'intfc_port' => 'dat_o',
                                              'intfc_name' => 'plug:wb_slave[0]',
                                              'type' => 'output'
                                            },
                               'clk' => {
                                          'intfc_name' => 'plug:clk[0]',
                                          'type' => 'input',
                                          'intfc_port' => 'clk_i',
                                          'range' => ''
                                        },
                               's_dat_i' => {
                                              'range' => '31       :   0',
                                              'intfc_port' => 'dat_i',
                                              'intfc_name' => 'plug:wb_slave[0]',
                                              'type' => 'input'
                                            },
                               's_cti_i' => {
                                              'intfc_port' => 'cti_i',
                                              'intfc_name' => 'plug:wb_slave[0]',
                                              'type' => 'input',
                                              'range' => '2     :   0'
                                            },
                               'reset' => {
                                            'intfc_port' => 'reset_i',
                                            'intfc_name' => 'plug:reset[0]',
                                            'type' => 'input',
                                            'range' => ''
                                          },
                               's_sel_i' => {
                                              'intfc_port' => 'sel_i',
                                              'intfc_name' => 'plug:wb_slave[0]',
                                              'type' => 'input',
                                              'range' => '3     :   0'
                                            },
                               's_stb_i' => {
                                              'range' => '',
                                              'intfc_port' => 'stb_i',
                                              'intfc_name' => 'plug:wb_slave[0]',
                                              'type' => 'input'
                                            }
                             },
                  'gui_status' => {
                                    'status' => 'ideal',
                                    'timeout' => 0
                                  },
                  'system_c' => '#define MODE_NOT_SOPPRTED 0
#define MODE_CLOSE  1
#define MODE_W      2
#define MODE_WB     3
#define MODE_A      4
#define MODE_AB     5
 
FILE file_ptr [50]={0};
FILE *  fopen   (const char *filename, const char *mode){
        //alloacte a new pointer;
        int i=0;
        while(file_ptr [i]!=0 && i<50) i++;
        if(i==50) return ((FILE *)0) ;
        //set file ,ode
        if (mode[0] == \'w\' ){
                if(mode[1]==\'b\') ${IP}_FILE_MODE = MODE_WB;
                else ${IP}_FILE_MODE = MODE_W;
        }else if (mode[0] == \'a\' ){
                if(mode[1]==\'b\') ${IP}_FILE_MODE = MODE_AB;
                else ${IP}_FILE_MODE = MODE_A;
        }else { // not supported mode
                //${IP}_FILE_MODE = MODE_NOT_SOPPRTED;
                return ((FILE *)0);
        }
 
 
        file_ptr [i]=i+1;
        //send file pointer
        ${IP}_GET_FLE_PTR = file_ptr [i];
        //send file name
        do{
                 ${IP}_GET_FILE_NAME = *filename;
                 filename++;
        }while(*filename!=0);
        // activate the Verilog Fwrite command once sending zero
        ${IP}_GET_FILE_NAME = 0;
        return (& file_ptr[i]);
}
 
 
 
void fclose(FILE * f){
        //write file pointer
        ${IP}_GET_FLE_PTR = *f;
        ${IP}_FILE_MODE = MODE_CLOSE; // activate the Verilog fclose
        *f = 0; //set free the pointer
}
 
void foutbyte( char c){
        //write content
        ${IP}_GET_FILE_CONTENT = c;
}
 
void fout_select (FILE *f){
        //write file pointer
        ${IP}_GET_FLE_PTR = *f;
}
 
#include "simple-printf/sim_fprintf.c"
',
                  'category' => 'Other',
                  'description' => 'A simple module to replicate the fprintf/fopen  instructions in simulator enviremets. ',
                  'file_name' => '/home/alireza/work/git/hca_git/ProNoC/mpsoc/rtl/src_peripheral/Other/fout_simulator.v',
                  'unused' => {
                                'plug:wb_slave[0]' => [
                                                        'tag_i',
                                                        'rty_o',
                                                        'bte_i',
                                                        'err_o'
                                                      ]
                              },
                  'ports_order' => [
                                     'reset',
                                     'clk',
                                     's_dat_i',
                                     's_sel_i',
                                     's_addr_i',
                                     's_cti_i',
                                     's_stb_i',
                                     's_cyc_i',
                                     's_we_i',
                                     's_dat_o',
                                     's_ack_o'
                                   ],
                  'plugs' => {
                               'reset' => {
                                            'type' => 'num',
                                            'value' => 1,
                                            '0' => {
                                                     'name' => 'reset'
                                                   }
                                          },
                               'wb_slave' => {
                                               '0' => {
                                                        'name' => 'wb_slave',
                                                        'width' => 5,
                                                        'addr' => '0x9000_0000  0x90ff_ffff             UART16550 Controller'
                                                      },
                                               'type' => 'num',
                                               'value' => 1
                                             },
                               'clk' => {
                                          'value' => 1,
                                          'type' => 'num',
                                          '0' => {
                                                   'name' => 'clk'
                                                 }
                                        }
                             },
                  'parameters_order' => [
                                          'BUFFER_SIZE'
                                        ],
                  'hdl_files' => [
                                   '/mpsoc/rtl/src_peripheral/Other/fout_simulator.v'
                                 ],
                  'system_h' => '#include "simple-printf/sim_fprintf.h"
 
#define ${IP}_GET_FLE_PTR                                       (*((volatile unsigned int *) ($BASE)))
#define ${IP}_GET_FILE_NAME                             (*((volatile unsigned int *) ($BASE+4)))
#define ${IP}_GET_FILE_CONTENT                  (*((volatile unsigned int *) ($BASE+8)))
#define ${IP}_FILE_MODE                                 (*((volatile unsigned int *) ($BASE+12)))
 
#define FILE  char
 
FILE * fopen   (const char *filename, const char *mode);
void fclose(FILE * f);
void foutbyte(char c);
void fout_select(FILE * f);'
                }, 'ip_gen' );

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Subversion Repositories an-fpga-implementation-of-low-latency-noc-based-mpsoc

[/] [an-fpga-implementation-of-low-latency-noc-based-mpsoc/] [trunk/] [mpsoc/] [perl_gui/] [lib/] [ip/] [Other/] [fout_sim.IP] - Blame information for rev 48

Line No.	Rev	Author	Line
1	48	alirezamon	`#######################################################################`
2			`## File: fout_sim.IP`
3			`##`
4			`## Copyright (C) 2014-2019 Alireza Monemi`
5			`##`
6			`## This file is part of ProNoC 1.9.1`
7			`##`
8			`## WARNING: THIS IS AN AUTO-GENERATED FILE. CHANGES TO IT`
9			`## MAY CAUSE UNEXPECTED BEHAVIOR.`
10			`################################################################################`
11
12			`$ipgen = bless( {`
13			`'version' => 29,`
14			`'sw_files' => [`
15			`'/mpsoc/src_processor/src_lib/simple-printf'`
16			`],`
17			`'modules' => {`
18			`'fout_simulator' => {}`
19			`},`
20			`'ip_name' => 'fout_sim',`
21			`'module_name' => 'fout_simulator',`
22			`'parameters' => {`
23			`'BUFFER_SIZE' => {`
24			`'content' => '10,1024,1',`
25			`'global_param' => 'Parameter',`
26			`'redefine_param' => 1,`
27			`'info' => 'Buffer width for getting for getting fle name.',`
28			`'type' => 'Spin-button',`
29			`'default' => '255 '`
30			`}`
31			`},`
32			`'hdl_files_ticked' => [],`
33			`'ports' => {`
34			`'s_we_i' => {`
35			`'type' => 'input',`
36			`'intfc_name' => 'plug:wb_slave[0]',`
37			`'intfc_port' => 'we_i',`
38			`'range' => ''`
39			`},`
40			`'s_cyc_i' => {`
41			`'intfc_port' => 'cyc_i',`
42			`'type' => 'input',`
43			`'intfc_name' => 'plug:wb_slave[0]',`
44			`'range' => ''`
45			`},`
46			`'s_ack_o' => {`
47			`'intfc_port' => 'ack_o',`
48			`'intfc_name' => 'plug:wb_slave[0]',`
49			`'type' => 'output',`
50			`'range' => ''`
51			`},`
52			`'s_addr_i' => {`
53			`'range' => '2 : 0',`
54			`'intfc_port' => 'adr_i',`
55			`'intfc_name' => 'plug:wb_slave[0]',`
56			`'type' => 'input'`
57			`},`
58			`'s_dat_o' => {`
59			`'range' => '31 : 0',`
60			`'intfc_port' => 'dat_o',`
61			`'intfc_name' => 'plug:wb_slave[0]',`
62			`'type' => 'output'`
63			`},`
64			`'clk' => {`
65			`'intfc_name' => 'plug:clk[0]',`
66			`'type' => 'input',`
67			`'intfc_port' => 'clk_i',`
68			`'range' => ''`
69			`},`
70			`'s_dat_i' => {`
71			`'range' => '31 : 0',`
72			`'intfc_port' => 'dat_i',`
73			`'intfc_name' => 'plug:wb_slave[0]',`
74			`'type' => 'input'`
75			`},`
76			`'s_cti_i' => {`
77			`'intfc_port' => 'cti_i',`
78			`'intfc_name' => 'plug:wb_slave[0]',`
79			`'type' => 'input',`
80			`'range' => '2 : 0'`
81			`},`
82			`'reset' => {`
83			`'intfc_port' => 'reset_i',`
84			`'intfc_name' => 'plug:reset[0]',`
85			`'type' => 'input',`
86			`'range' => ''`
87			`},`
88			`'s_sel_i' => {`
89			`'intfc_port' => 'sel_i',`
90			`'intfc_name' => 'plug:wb_slave[0]',`
91			`'type' => 'input',`
92			`'range' => '3 : 0'`
93			`},`
94			`'s_stb_i' => {`
95			`'range' => '',`
96			`'intfc_port' => 'stb_i',`
97			`'intfc_name' => 'plug:wb_slave[0]',`
98			`'type' => 'input'`
99			`}`
100			`},`
101			`'gui_status' => {`
102			`'status' => 'ideal',`
103			`'timeout' => 0`
104			`},`
105			`'system_c' => '#define MODE_NOT_SOPPRTED 0`
106			`#define MODE_CLOSE 1`
107			`#define MODE_W 2`
108			`#define MODE_WB 3`
109			`#define MODE_A 4`
110			`#define MODE_AB 5`
111
112			`FILE file_ptr [50]={0};`
113			`FILE * fopen (const char filename, const char mode){`
114			`//alloacte a new pointer;`
115			`int i=0;`
116			`while(file_ptr [i]!=0 && i<50) i++;`
117			`if(i==50) return ((FILE *)0) ;`
118			`//set file ,ode`
119			`if (mode[0] == \'w\' ){`
120			`if(mode[1]==\'b\') ${IP}_FILE_MODE = MODE_WB;`
121			`else ${IP}_FILE_MODE = MODE_W;`
122			`}else if (mode[0] == \'a\' ){`
123			`if(mode[1]==\'b\') ${IP}_FILE_MODE = MODE_AB;`
124			`else ${IP}_FILE_MODE = MODE_A;`
125			`}else { // not supported mode`
126			`//${IP}_FILE_MODE = MODE_NOT_SOPPRTED;`
127			`return ((FILE *)0);`
128			`}`
129
130
131			`file_ptr [i]=i+1;`
132			`//send file pointer`
133			`${IP}_GET_FLE_PTR = file_ptr [i];`
134			`//send file name`
135			`do{`
136			`${IP}_GET_FILE_NAME = *filename;`
137			`filename++;`
138			`}while(*filename!=0);`
139			`// activate the Verilog Fwrite command once sending zero`
140			`${IP}_GET_FILE_NAME = 0;`
141			`return (& file_ptr[i]);`
142			`}`
143
144
145
146			`void fclose(FILE * f){`
147			`//write file pointer`
148			`${IP}_GET_FLE_PTR = *f;`
149			`${IP}_FILE_MODE = MODE_CLOSE; // activate the Verilog fclose`
150			`*f = 0; //set free the pointer`
151			`}`
152
153			`void foutbyte( char c){`
154			`//write content`
155			`${IP}_GET_FILE_CONTENT = c;`
156			`}`
157
158			`void fout_select (FILE *f){`
159			`//write file pointer`
160			`${IP}_GET_FLE_PTR = *f;`
161			`}`
162
163			`#include "simple-printf/sim_fprintf.c"`
164			`',`
165			`'category' => 'Other',`
166			`'description' => 'A simple module to replicate the fprintf/fopen instructions in simulator enviremets. ',`
167			`'file_name' => '/home/alireza/work/git/hca_git/ProNoC/mpsoc/rtl/src_peripheral/Other/fout_simulator.v',`
168			`'unused' => {`
169			`'plug:wb_slave[0]' => [`
170			`'tag_i',`
171			`'rty_o',`
172			`'bte_i',`
173			`'err_o'`
174			`]`
175			`},`
176			`'ports_order' => [`
177			`'reset',`
178			`'clk',`
179			`'s_dat_i',`
180			`'s_sel_i',`
181			`'s_addr_i',`
182			`'s_cti_i',`
183			`'s_stb_i',`
184			`'s_cyc_i',`
185			`'s_we_i',`
186			`'s_dat_o',`
187			`'s_ack_o'`
188			`],`
189			`'plugs' => {`
190			`'reset' => {`
191			`'type' => 'num',`
192			`'value' => 1,`
193			`'0' => {`
194			`'name' => 'reset'`
195			`}`
196			`},`
197			`'wb_slave' => {`
198			`'0' => {`
199			`'name' => 'wb_slave',`
200			`'width' => 5,`
201			`'addr' => '0x9000_0000 0x90ff_ffff UART16550 Controller'`
202			`},`
203			`'type' => 'num',`
204			`'value' => 1`
205			`},`
206			`'clk' => {`
207			`'value' => 1,`
208			`'type' => 'num',`
209			`'0' => {`
210			`'name' => 'clk'`
211			`}`
212			`}`
213			`},`
214			`'parameters_order' => [`
215			`'BUFFER_SIZE'`
216			`],`
217			`'hdl_files' => [`
218			`'/mpsoc/rtl/src_peripheral/Other/fout_simulator.v'`
219			`],`
220			`'system_h' => '#include "simple-printf/sim_fprintf.h"`
221
222			`#define ${IP}_GET_FLE_PTR (((volatile unsigned int ) ($BASE)))`
223			`#define ${IP}_GET_FILE_NAME (((volatile unsigned int ) ($BASE+4)))`
224			`#define ${IP}_GET_FILE_CONTENT (((volatile unsigned int ) ($BASE+8)))`
225			`#define ${IP}_FILE_MODE (((volatile unsigned int ) ($BASE+12)))`
226
227			`#define FILE char`
228
229			`FILE * fopen (const char filename, const char mode);`
230			`void fclose(FILE * f);`
231			`void foutbyte(char c);`
232			`void fout_select(FILE * f);'`
233			`}, 'ip_gen' );`