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alirezamon |
#######################################################################
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## File: Or1200.IP
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##
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## Copyright (C) 2014-2016 Alireza Monemi
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##
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## This file is part of ProNoC 1.7.0
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##
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## WARNING: THIS IS AN AUTO-GENERATED FILE. CHANGES TO IT
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## MAY CAUSE UNEXPECTED BEHAIVOR.
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################################################################################
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$or1200 = bless( {
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'system_h' => ' #include "or1200/system.h"
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inline void nop (){
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__asm__("l.nop 1");
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}',
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'category' => 'Processor',
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'sw_files' => [
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'/mpsoc/src_processor/or1200/sw/Makefile',
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'/mpsoc/src_processor/or1200/sw/or1200',
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'/mpsoc/src_processor/or1200/sw/link.ld',
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'/mpsoc/src_processor/or1200/sw/define_printf.h',
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'/mpsoc/src_processor/src_lib/simple-printf'
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],
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'file_name' => '/home/alireza/mywork/mpsoc/src_processor/or1200/verilog/or1200.v',
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'hdl_files' => [
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'/mpsoc/src_processor/or1200/verilog/or1200.v',
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'/mpsoc/src_processor/or1200/verilog/src/or1200_alu.v',
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'/mpsoc/src_processor/or1200/verilog/src/or1200_amultp2_32x32.v',
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'/mpsoc/src_processor/or1200/verilog/src/or1200_cfgr.v',
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'/mpsoc/src_processor/or1200/verilog/src/or1200_cpu.v',
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'/mpsoc/src_processor/or1200/verilog/src/or1200_ctrl.v',
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'/mpsoc/src_processor/or1200/verilog/src/or1200_dc_fsm.v',
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'/mpsoc/src_processor/or1200/verilog/src/or1200_dc_ram.v',
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'/mpsoc/src_processor/or1200/verilog/src/or1200_dc_tag.v',
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'/mpsoc/src_processor/or1200/verilog/src/or1200_dc_top.v',
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'/mpsoc/src_processor/or1200/verilog/src/or1200_dmmu_tlb.v',
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'/mpsoc/src_processor/or1200/verilog/src/or1200_dmmu_top.v',
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'/mpsoc/src_processor/or1200/verilog/src/or1200_dpram.v',
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'/mpsoc/src_processor/or1200/verilog/src/or1200_dpram_32x32.v',
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'/mpsoc/src_processor/or1200/verilog/src/or1200_dpram_256x32.v',
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'/mpsoc/src_processor/or1200/verilog/src/or1200_du.v',
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'/mpsoc/src_processor/or1200/verilog/src/or1200_except.v',
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'/mpsoc/src_processor/or1200/verilog/src/or1200_fpu.v',
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'/mpsoc/src_processor/or1200/verilog/src/or1200_fpu_addsub.v',
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'/mpsoc/src_processor/or1200/verilog/src/or1200_fpu_arith.v',
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'/mpsoc/src_processor/or1200/verilog/src/or1200_fpu_div.v',
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'/mpsoc/src_processor/or1200/verilog/src/or1200_fpu_fcmp.v',
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'/mpsoc/src_processor/or1200/verilog/src/or1200_fpu_intfloat_conv.v',
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'/mpsoc/src_processor/or1200/verilog/src/or1200_fpu_intfloat_conv_except.v',
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'/mpsoc/src_processor/or1200/verilog/src/or1200_fpu_mul.v',
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'/mpsoc/src_processor/or1200/verilog/src/or1200_fpu_post_norm_addsub.v',
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'/mpsoc/src_processor/or1200/verilog/src/or1200_fpu_post_norm_div.v',
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'/mpsoc/src_processor/or1200/verilog/src/or1200_fpu_post_norm_intfloat_conv.v',
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'/mpsoc/src_processor/or1200/verilog/src/or1200_fpu_post_norm_mul.v',
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'/mpsoc/src_processor/or1200/verilog/src/or1200_fpu_pre_norm_addsub.v',
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'/mpsoc/src_processor/or1200/verilog/src/or1200_fpu_pre_norm_div.v',
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'/mpsoc/src_processor/or1200/verilog/src/or1200_fpu_pre_norm_mul.v',
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'/mpsoc/src_processor/or1200/verilog/src/or1200_freeze.v',
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'/mpsoc/src_processor/or1200/verilog/src/or1200_genpc.v',
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'/mpsoc/src_processor/or1200/verilog/src/or1200_gmultp2_32x32.v',
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'/mpsoc/src_processor/or1200/verilog/src/or1200_ic_fsm.v',
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'/mpsoc/src_processor/or1200/verilog/src/or1200_ic_ram.v',
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'/mpsoc/src_processor/or1200/verilog/src/or1200_ic_tag.v',
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'/mpsoc/src_processor/or1200/verilog/src/or1200_ic_top.v',
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'/mpsoc/src_processor/or1200/verilog/src/or1200_if.v',
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'/mpsoc/src_processor/or1200/verilog/src/or1200_immu_tlb.v',
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'/mpsoc/src_processor/or1200/verilog/src/or1200_immu_top.v',
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'/mpsoc/src_processor/or1200/verilog/src/or1200_iwb_biu.v',
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'/mpsoc/src_processor/or1200/verilog/src/or1200_lsu.v',
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'/mpsoc/src_processor/or1200/verilog/src/or1200_mem2reg.v',
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'/mpsoc/src_processor/or1200/verilog/src/or1200_mult_mac.v',
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'/mpsoc/src_processor/or1200/verilog/src/or1200_operandmuxes.v',
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'/mpsoc/src_processor/or1200/verilog/src/or1200_pic.v',
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'/mpsoc/src_processor/or1200/verilog/src/or1200_pm.v',
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'/mpsoc/src_processor/or1200/verilog/src/or1200_qmem_top.v',
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'/mpsoc/src_processor/or1200/verilog/src/or1200_reg2mem.v',
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'/mpsoc/src_processor/or1200/verilog/src/or1200_rf.v',
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'/mpsoc/src_processor/or1200/verilog/src/or1200_rfram_generic.v',
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'/mpsoc/src_processor/or1200/verilog/src/or1200_sb.v',
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'/mpsoc/src_processor/or1200/verilog/src/or1200_sb_fifo.v',
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'/mpsoc/src_processor/or1200/verilog/src/or1200_spram.v',
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'/mpsoc/src_processor/or1200/verilog/src/or1200_spram_32_bw.v',
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'/mpsoc/src_processor/or1200/verilog/src/or1200_spram_32x24.v',
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'/mpsoc/src_processor/or1200/verilog/src/or1200_spram_64x14.v',
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'/mpsoc/src_processor/or1200/verilog/src/or1200_spram_64x22.v',
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'/mpsoc/src_processor/or1200/verilog/src/or1200_spram_64x24.v',
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'/mpsoc/src_processor/or1200/verilog/src/or1200_spram_128x32.v',
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'/mpsoc/src_processor/or1200/verilog/src/or1200_spram_256x21.v',
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'/mpsoc/src_processor/or1200/verilog/src/or1200_spram_512x20.v',
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'/mpsoc/src_processor/or1200/verilog/src/or1200_spram_1024x8.v',
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'/mpsoc/src_processor/or1200/verilog/src/or1200_spram_1024x32.v',
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'/mpsoc/src_processor/or1200/verilog/src/or1200_spram_1024x32_bw.v',
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| 96 |
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'/mpsoc/src_processor/or1200/verilog/src/or1200_spram_2048x8.v',
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| 97 |
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'/mpsoc/src_processor/or1200/verilog/src/or1200_spram_2048x32.v',
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| 98 |
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'/mpsoc/src_processor/or1200/verilog/src/or1200_spram_2048x32_bw.v',
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| 99 |
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'/mpsoc/src_processor/or1200/verilog/src/or1200_sprs.v',
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| 100 |
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'/mpsoc/src_processor/or1200/verilog/src/or1200_top.v',
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'/mpsoc/src_processor/or1200/verilog/src/or1200_tpram_32x32.v',
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| 102 |
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'/mpsoc/src_processor/or1200/verilog/src/or1200_tt.v',
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| 103 |
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'/mpsoc/src_processor/or1200/verilog/src/or1200_wb_biu.v',
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| 104 |
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'/mpsoc/src_processor/or1200/verilog/src/or1200_wbmux.v',
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| 105 |
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'/mpsoc/src_processor/or1200/verilog/src/or1200_xcv_ram32x8d.v',
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| 106 |
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'/mpsoc/src_processor/or1200/verilog/src/timescale.v'
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],
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'ip_name' => 'Or1200',
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'plugs' => {
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'reset' => {
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'type' => 'num',
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'value' => 1,
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'0' => {
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'name' => 'reset'
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}
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},
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'enable' => {
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'0' => {
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'name' => 'enable'
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},
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| 121 |
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'enable' => {},
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'value' => 1,
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'type' => 'num'
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},
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| 125 |
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'wb_master' => {
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| 126 |
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'0' => {
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| 127 |
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'name' => 'iwb'
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| 128 |
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},
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| 129 |
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'type' => 'num',
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| 130 |
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'value' => 2,
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| 131 |
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'1' => {
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| 132 |
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'name' => 'dwb'
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| 133 |
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}
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| 134 |
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},
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| 135 |
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'clk' => {
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| 136 |
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'0' => {
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| 137 |
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'name' => 'clk'
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| 138 |
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},
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| 139 |
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'type' => 'num',
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| 140 |
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'value' => 1
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| 141 |
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}
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| 142 |
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},
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| 143 |
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'ports' => {
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| 144 |
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'reset' => {
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| 145 |
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'intfc_port' => 'reset_i',
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| 146 |
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'intfc_name' => 'plug:reset[0]',
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| 147 |
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'type' => 'input'
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| 148 |
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},
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| 149 |
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'dwb_sel_o' => {
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| 150 |
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'type' => 'output',
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| 151 |
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'range' => '3:0',
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| 152 |
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'intfc_port' => 'sel_o',
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| 153 |
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'intfc_name' => 'plug:wb_master[1]'
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| 154 |
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},
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| 155 |
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'dwb_cti_o' => {
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| 156 |
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'intfc_port' => 'cti_o',
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| 157 |
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'intfc_name' => 'plug:wb_master[1]',
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| 158 |
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'type' => 'output',
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| 159 |
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'range' => '2:0'
|
| 160 |
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},
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| 161 |
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'dwb_bte_o' => {
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| 162 |
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'type' => 'output',
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| 163 |
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'range' => '1:0',
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| 164 |
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'intfc_port' => 'bte_o',
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| 165 |
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'intfc_name' => 'plug:wb_master[1]'
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| 166 |
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},
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| 167 |
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'iwb_cyc_o' => {
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| 168 |
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'intfc_port' => 'cyc_o',
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| 169 |
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'intfc_name' => 'plug:wb_master[0]',
|
| 170 |
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'type' => 'output',
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| 171 |
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'range' => ''
|
| 172 |
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},
|
| 173 |
|
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'dwb_adr_o' => {
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| 174 |
|
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'intfc_port' => 'adr_o',
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| 175 |
|
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'intfc_name' => 'plug:wb_master[1]',
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| 176 |
|
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'range' => 'aw-1:0',
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| 177 |
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'type' => 'output'
|
| 178 |
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},
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| 179 |
|
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'iwb_err_i' => {
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| 180 |
|
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'intfc_port' => 'err_i',
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| 181 |
|
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'intfc_name' => 'plug:wb_master[0]',
|
| 182 |
|
|
'range' => '',
|
| 183 |
|
|
'type' => 'input'
|
| 184 |
|
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},
|
| 185 |
|
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'dwb_we_o' => {
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| 186 |
|
|
'range' => '',
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| 187 |
|
|
'type' => 'output',
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| 188 |
|
|
'intfc_name' => 'plug:wb_master[1]',
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| 189 |
|
|
'intfc_port' => 'we_o'
|
| 190 |
|
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},
|
| 191 |
|
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'dwb_rty_i' => {
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| 192 |
|
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'intfc_name' => 'plug:wb_master[1]',
|
| 193 |
|
|
'intfc_port' => 'rty_i',
|
| 194 |
|
|
'type' => 'input',
|
| 195 |
|
|
'range' => ''
|
| 196 |
|
|
},
|
| 197 |
|
|
'dwb_dat_o' => {
|
| 198 |
|
|
'intfc_port' => 'dat_o',
|
| 199 |
|
|
'intfc_name' => 'plug:wb_master[1]',
|
| 200 |
|
|
'type' => 'output',
|
| 201 |
|
|
'range' => 'dw-1:0'
|
| 202 |
|
|
},
|
| 203 |
|
|
'iwb_dat_o' => {
|
| 204 |
|
|
'intfc_port' => 'dat_o',
|
| 205 |
|
|
'intfc_name' => 'plug:wb_master[0]',
|
| 206 |
|
|
'type' => 'output',
|
| 207 |
|
|
'range' => 'dw-1:0'
|
| 208 |
|
|
},
|
| 209 |
|
|
'iwb_rty_i' => {
|
| 210 |
|
|
'intfc_port' => 'rty_i',
|
| 211 |
|
|
'intfc_name' => 'plug:wb_master[0]',
|
| 212 |
|
|
'type' => 'input',
|
| 213 |
|
|
'range' => ''
|
| 214 |
|
|
},
|
| 215 |
|
|
'iwb_sel_o' => {
|
| 216 |
|
|
'intfc_name' => 'plug:wb_master[0]',
|
| 217 |
|
|
'intfc_port' => 'sel_o',
|
| 218 |
|
|
'type' => 'output',
|
| 219 |
|
|
'range' => '3:0'
|
| 220 |
|
|
},
|
| 221 |
|
|
'clk' => {
|
| 222 |
|
|
'range' => '',
|
| 223 |
|
|
'type' => 'input',
|
| 224 |
|
|
'intfc_port' => 'clk_i',
|
| 225 |
|
|
'intfc_name' => 'plug:clk[0]'
|
| 226 |
|
|
},
|
| 227 |
|
|
'en_i' => {
|
| 228 |
|
|
'intfc_port' => 'enable_i',
|
| 229 |
|
|
'intfc_name' => 'plug:enable[0]',
|
| 230 |
|
|
'type' => 'input',
|
| 231 |
|
|
'range' => ''
|
| 232 |
|
|
},
|
| 233 |
|
|
'dwb_cyc_o' => {
|
| 234 |
|
|
'type' => 'output',
|
| 235 |
|
|
'range' => '',
|
| 236 |
|
|
'intfc_port' => 'cyc_o',
|
| 237 |
|
|
'intfc_name' => 'plug:wb_master[1]'
|
| 238 |
|
|
},
|
| 239 |
|
|
'iwb_dat_i' => {
|
| 240 |
|
|
'range' => 'dw-1:0',
|
| 241 |
|
|
'type' => 'input',
|
| 242 |
|
|
'intfc_port' => 'dat_i',
|
| 243 |
|
|
'intfc_name' => 'plug:wb_master[0]'
|
| 244 |
|
|
},
|
| 245 |
|
|
'iwb_stb_o' => {
|
| 246 |
|
|
'type' => 'output',
|
| 247 |
|
|
'range' => '',
|
| 248 |
|
|
'intfc_name' => 'plug:wb_master[0]',
|
| 249 |
|
|
'intfc_port' => 'stb_o'
|
| 250 |
|
|
},
|
| 251 |
|
|
'dwb_ack_i' => {
|
| 252 |
|
|
'type' => 'input',
|
| 253 |
|
|
'range' => '',
|
| 254 |
|
|
'intfc_name' => 'plug:wb_master[1]',
|
| 255 |
|
|
'intfc_port' => 'ack_i'
|
| 256 |
|
|
},
|
| 257 |
|
|
'dwb_dat_i' => {
|
| 258 |
|
|
'type' => 'input',
|
| 259 |
|
|
'range' => 'dw-1:0',
|
| 260 |
|
|
'intfc_name' => 'plug:wb_master[1]',
|
| 261 |
|
|
'intfc_port' => 'dat_i'
|
| 262 |
|
|
},
|
| 263 |
|
|
'iwb_cti_o' => {
|
| 264 |
|
|
'intfc_name' => 'plug:wb_master[0]',
|
| 265 |
|
|
'intfc_port' => 'cti_o',
|
| 266 |
|
|
'type' => 'output',
|
| 267 |
|
|
'range' => '2:0'
|
| 268 |
|
|
},
|
| 269 |
|
|
'iwb_we_o' => {
|
| 270 |
|
|
'intfc_port' => 'we_o',
|
| 271 |
|
|
'intfc_name' => 'plug:wb_master[0]',
|
| 272 |
|
|
'range' => '',
|
| 273 |
|
|
'type' => 'output'
|
| 274 |
|
|
},
|
| 275 |
|
|
'iwb_adr_o' => {
|
| 276 |
|
|
'range' => 'aw-1:0',
|
| 277 |
|
|
'type' => 'output',
|
| 278 |
|
|
'intfc_name' => 'plug:wb_master[0]',
|
| 279 |
|
|
'intfc_port' => 'adr_o'
|
| 280 |
|
|
},
|
| 281 |
|
|
'dwb_err_i' => {
|
| 282 |
|
|
'range' => '',
|
| 283 |
|
|
'type' => 'input',
|
| 284 |
|
|
'intfc_port' => 'err_i',
|
| 285 |
|
|
'intfc_name' => 'plug:wb_master[1]'
|
| 286 |
|
|
},
|
| 287 |
|
|
'iwb_bte_o' => {
|
| 288 |
|
|
'intfc_name' => 'plug:wb_master[0]',
|
| 289 |
|
|
'intfc_port' => 'bte_o',
|
| 290 |
|
|
'type' => 'output',
|
| 291 |
|
|
'range' => '1:0'
|
| 292 |
|
|
},
|
| 293 |
|
|
'dwb_stb_o' => {
|
| 294 |
|
|
'intfc_port' => 'stb_o',
|
| 295 |
|
|
'intfc_name' => 'plug:wb_master[1]',
|
| 296 |
|
|
'type' => 'output',
|
| 297 |
|
|
'range' => ''
|
| 298 |
|
|
},
|
| 299 |
|
|
'iwb_ack_i' => {
|
| 300 |
|
|
'range' => '',
|
| 301 |
|
|
'type' => 'input',
|
| 302 |
|
|
'intfc_port' => 'ack_i',
|
| 303 |
|
|
'intfc_name' => 'plug:wb_master[0]'
|
| 304 |
|
|
},
|
| 305 |
|
|
'pic_ints_i' => {
|
| 306 |
|
|
'intfc_port' => 'int_i',
|
| 307 |
|
|
'intfc_name' => 'socket:interrupt_peripheral[array]',
|
| 308 |
|
|
'range' => 'ppic_ints-1:0',
|
| 309 |
|
|
'type' => 'input'
|
| 310 |
|
|
}
|
| 311 |
|
|
},
|
| 312 |
|
|
'parameters_order' => [
|
| 313 |
|
|
'dw',
|
| 314 |
|
|
'aw',
|
| 315 |
|
|
'ppic_ints',
|
| 316 |
|
|
'boot_adr',
|
| 317 |
|
|
'Data_cashe_size',
|
| 318 |
|
|
'Instruction_cashe_size',
|
| 319 |
|
|
'Data_cashe_enable',
|
| 320 |
|
|
'Instruction_cashe_enable',
|
| 321 |
|
|
'Data_MMU_enable',
|
| 322 |
|
|
'Instruction_MMU_enable',
|
| 323 |
|
|
'implementation_addc',
|
| 324 |
|
|
'implement_sub',
|
| 325 |
|
|
'implement_cy',
|
| 326 |
|
|
'implement_0v',
|
| 327 |
|
|
'implement_OVE',
|
| 328 |
|
|
'implement_alu_rotate',
|
| 329 |
|
|
'implement_alu_compare',
|
| 330 |
|
|
'implement_alu_ext',
|
| 331 |
|
|
'multiplier_type',
|
| 332 |
|
|
'divider_type'
|
| 333 |
|
|
],
|
| 334 |
|
|
'unused' => {
|
| 335 |
|
|
'plug:wb_master[1]' => [
|
| 336 |
|
|
'tag_o'
|
| 337 |
|
|
],
|
| 338 |
|
|
'plug:wb_master[0]' => [
|
| 339 |
|
|
'tag_o'
|
| 340 |
|
|
]
|
| 341 |
|
|
},
|
| 342 |
|
|
'parameters' => {
|
| 343 |
|
|
'implement_0v' => {
|
| 344 |
|
|
'content' => '0V,NO_0V',
|
| 345 |
|
|
'redefine_param' => 0,
|
| 346 |
|
|
'global_param' => 'Don\'t include',
|
| 347 |
|
|
'info' => 'Implement carry bit SR[OV]
|
| 348 |
|
|
Compiler doesn\'t use this, but other code may like to.',
|
| 349 |
|
|
'default' => '0V',
|
| 350 |
|
|
'type' => 'Combo-box'
|
| 351 |
|
|
},
|
| 352 |
|
|
'implement_alu_ext' => {
|
| 353 |
|
|
'global_param' => 'Don\'t include',
|
| 354 |
|
|
'content' => 'EXT,NO_EXT',
|
| 355 |
|
|
'redefine_param' => 0,
|
| 356 |
|
|
'type' => 'Combo-box',
|
| 357 |
|
|
'info' => 'Implement l.extXs and l.extXz instructions',
|
| 358 |
|
|
'default' => 'NO_EXT'
|
| 359 |
|
|
},
|
| 360 |
|
|
'Data_MMU_enable' => {
|
| 361 |
|
|
'content' => 'NO,YES',
|
| 362 |
|
|
'redefine_param' => 0,
|
| 363 |
|
|
'global_param' => 'Don\'t include',
|
| 364 |
|
|
'default' => 'YES',
|
| 365 |
|
|
'info' => undef,
|
| 366 |
|
|
'type' => 'Combo-box'
|
| 367 |
|
|
},
|
| 368 |
|
|
'aw' => {
|
| 369 |
|
|
'type' => 'Fixed',
|
| 370 |
|
|
'info' => 'Parameter',
|
| 371 |
|
|
'default' => '32',
|
| 372 |
|
|
'global_param' => 'Parameter',
|
| 373 |
|
|
'content' => '',
|
| 374 |
|
|
'redefine_param' => 1
|
| 375 |
|
|
},
|
| 376 |
|
|
'Data_cashe_enable' => {
|
| 377 |
|
|
'info' => undef,
|
| 378 |
|
|
'default' => 'YES',
|
| 379 |
|
|
'type' => 'Combo-box',
|
| 380 |
|
|
'redefine_param' => 0,
|
| 381 |
|
|
'content' => 'NO,YES',
|
| 382 |
|
|
'global_param' => 'Don\'t include'
|
| 383 |
|
|
},
|
| 384 |
|
|
'implement_OVE' => {
|
| 385 |
|
|
'redefine_param' => 0,
|
| 386 |
|
|
'content' => 'OVE,NO_OVE',
|
| 387 |
|
|
'global_param' => 'Don\'t include',
|
| 388 |
|
|
'info' => 'Implement carry bit SR[OVE]
|
| 389 |
|
|
Overflow interrupt indicator. When enabled, SR[OV] flag does not remain asserted after exception.',
|
| 390 |
|
|
'default' => 'NO_OVE',
|
| 391 |
|
|
'type' => 'Combo-box'
|
| 392 |
|
|
},
|
| 393 |
|
|
'implementation_addc' => {
|
| 394 |
|
|
'global_param' => 'Don\'t include',
|
| 395 |
|
|
'content' => 'ADDC,NO_ADDC',
|
| 396 |
|
|
'redefine_param' => 0,
|
| 397 |
|
|
'type' => 'Combo-box',
|
| 398 |
|
|
'default' => 'ADDC',
|
| 399 |
|
|
'info' => 'Implement l.addc/l.addic instructions
|
| 400 |
|
|
By default implementation of l.addc/l.addic instructions is enabled in case you need them.
|
| 401 |
|
|
If you don\'t use them, then disable implementation to save area.'
|
| 402 |
|
|
},
|
| 403 |
|
|
'implement_sub' => {
|
| 404 |
|
|
'type' => 'Combo-box',
|
| 405 |
|
|
'default' => 'SUB',
|
| 406 |
|
|
'info' => 'Implement l.sub instruction
|
| 407 |
|
|
By default implementation of l.sub instructions is enabled to be compliant with the simulator.
|
| 408 |
|
|
If you don\'t use carry bit, then disable implementation to save area.',
|
| 409 |
|
|
'global_param' => 'Don\'t include',
|
| 410 |
|
|
'content' => 'SUB,NO_SUB',
|
| 411 |
|
|
'redefine_param' => 0
|
| 412 |
|
|
},
|
| 413 |
|
|
'divider_type' => {
|
| 414 |
|
|
'type' => 'Combo-box',
|
| 415 |
|
|
'default' => 'SERIAL',
|
| 416 |
|
|
'info' => undef,
|
| 417 |
|
|
'global_param' => 'Don\'t include',
|
| 418 |
|
|
'redefine_param' => 0,
|
| 419 |
|
|
'content' => 'SERIAL,PARALLEL'
|
| 420 |
|
|
},
|
| 421 |
|
|
'Instruction_MMU_enable' => {
|
| 422 |
|
|
'global_param' => 'Don\'t include',
|
| 423 |
|
|
'content' => 'NO,YES',
|
| 424 |
|
|
'redefine_param' => 0,
|
| 425 |
|
|
'type' => 'Combo-box',
|
| 426 |
|
|
'default' => 'YES',
|
| 427 |
|
|
'info' => undef
|
| 428 |
|
|
},
|
| 429 |
|
|
'implement_alu_rotate' => {
|
| 430 |
|
|
'global_param' => 'Don\'t include',
|
| 431 |
|
|
'redefine_param' => 0,
|
| 432 |
|
|
'content' => 'ROTATE,NO_ROTATE',
|
| 433 |
|
|
'type' => 'Combo-box',
|
| 434 |
|
|
'info' => 'Implement rotate in the ALU
|
| 435 |
|
|
At the time of writing this, or32 C/C++ compiler doesn\'t generate rotate instructions. However or32 assembler can assemble code that uses rotate insn.
|
| 436 |
|
|
This means that rotate instructions must be used manually inserted.
|
| 437 |
|
|
By default implementation of rotate is disabled to save area and increase is disabled to save area and increase clock frequency.',
|
| 438 |
|
|
'default' => 'ROTATE'
|
| 439 |
|
|
},
|
| 440 |
|
|
'multiplier_type' => {
|
| 441 |
|
|
'global_param' => 'Don\'t include',
|
| 442 |
|
|
'redefine_param' => 0,
|
| 443 |
|
|
'content' => 'SERIAL,PARALLEL',
|
| 444 |
|
|
'type' => 'Combo-box',
|
| 445 |
|
|
'info' => undef,
|
| 446 |
|
|
'default' => 'SERIAL'
|
| 447 |
|
|
},
|
| 448 |
|
|
'boot_adr' => {
|
| 449 |
|
|
'content' => '',
|
| 450 |
|
|
'redefine_param' => 1,
|
| 451 |
|
|
'global_param' => 'Parameter',
|
| 452 |
|
|
'info' => 'Parameter',
|
| 453 |
|
|
'default' => '32\'h00000100',
|
| 454 |
|
|
'type' => 'Fixed'
|
| 455 |
|
|
},
|
| 456 |
|
|
'Instruction_cashe_enable' => {
|
| 457 |
|
|
'global_param' => 'Don\'t include',
|
| 458 |
|
|
'redefine_param' => 0,
|
| 459 |
|
|
'content' => 'NO,YES',
|
| 460 |
|
|
'type' => 'Combo-box',
|
| 461 |
|
|
'info' => undef,
|
| 462 |
|
|
'default' => 'YES'
|
| 463 |
|
|
},
|
| 464 |
|
|
'ppic_ints' => {
|
| 465 |
|
|
'content' => '3,31,1',
|
| 466 |
|
|
'redefine_param' => 1,
|
| 467 |
|
|
'global_param' => 'Parameter',
|
| 468 |
|
|
'info' => 'Number of interrupts',
|
| 469 |
|
|
'default' => '20',
|
| 470 |
|
|
'type' => 'Spin-button'
|
| 471 |
|
|
},
|
| 472 |
|
|
'Data_cashe_size' => {
|
| 473 |
|
|
'content' => '512,4K,8K,16K,32K',
|
| 474 |
|
|
'redefine_param' => 0,
|
| 475 |
|
|
'global_param' => 'Don\'t include',
|
| 476 |
|
|
'info' => 'Data Cashe Size in B',
|
| 477 |
|
|
'default' => '8K',
|
| 478 |
|
|
'type' => 'Combo-box'
|
| 479 |
|
|
},
|
| 480 |
|
|
'Instruction_cashe_size' => {
|
| 481 |
|
|
'default' => '8K',
|
| 482 |
|
|
'info' => 'Instruction Cashe Size in B',
|
| 483 |
|
|
'type' => 'Combo-box',
|
| 484 |
|
|
'content' => '512,4K,8K,16K,32K',
|
| 485 |
|
|
'redefine_param' => 0,
|
| 486 |
|
|
'global_param' => 'Don\'t include'
|
| 487 |
|
|
},
|
| 488 |
|
|
'implement_alu_compare' => {
|
| 489 |
|
|
'global_param' => 'Don\'t include',
|
| 490 |
|
|
'redefine_param' => 0,
|
| 491 |
|
|
'content' => '1,2,3',
|
| 492 |
|
|
'type' => 'Combo-box',
|
| 493 |
|
|
'default' => '2',
|
| 494 |
|
|
'info' => 'Type of ALU compare to implement
|
| 495 |
|
|
Try to find which synthesizes with most efficient logic use or highest speed.'
|
| 496 |
|
|
},
|
| 497 |
|
|
'dw' => {
|
| 498 |
|
|
'default' => '32',
|
| 499 |
|
|
'info' => 'Parameter',
|
| 500 |
|
|
'type' => 'Fixed',
|
| 501 |
|
|
'redefine_param' => 1,
|
| 502 |
|
|
'content' => '',
|
| 503 |
|
|
'global_param' => 'Parameter'
|
| 504 |
|
|
},
|
| 505 |
|
|
'implement_cy' => {
|
| 506 |
|
|
'type' => 'Combo-box',
|
| 507 |
|
|
'info' => 'Implement carry bit SR[CY]
|
| 508 |
|
|
By default implementation of SR[CY] is enabled to be compliant with the simulator. However SR[CY] is explicitly only used by l.addc/l.addic/l.sub instructions and if these three insns are not implemented there is not much point having SR[CY].',
|
| 509 |
|
|
'default' => 'CY',
|
| 510 |
|
|
'global_param' => 'Don\'t include',
|
| 511 |
|
|
'redefine_param' => 0,
|
| 512 |
|
|
'content' => 'CY,NO_CY'
|
| 513 |
|
|
}
|
| 514 |
|
|
},
|
| 515 |
|
|
'modules' => {
|
| 516 |
|
|
'or1200' => {}
|
| 517 |
|
|
},
|
| 518 |
|
|
'sockets' => {
|
| 519 |
|
|
'interrupt_peripheral' => {
|
| 520 |
|
|
'type' => 'param',
|
| 521 |
|
|
'value' => 'ppic_ints',
|
| 522 |
|
|
'connection_num' => 'single connection',
|
| 523 |
|
|
'0' => {
|
| 524 |
|
|
'name' => 'interrupt'
|
| 525 |
|
|
}
|
| 526 |
|
|
}
|
| 527 |
|
|
},
|
| 528 |
|
|
'ports_order' => [
|
| 529 |
|
|
'clk',
|
| 530 |
|
|
'reset',
|
| 531 |
|
|
'en_i',
|
| 532 |
|
|
'pic_ints_i',
|
| 533 |
|
|
'iwb_ack_i',
|
| 534 |
|
|
'iwb_err_i',
|
| 535 |
|
|
'iwb_rty_i',
|
| 536 |
|
|
'iwb_dat_i',
|
| 537 |
|
|
'iwb_cyc_o',
|
| 538 |
|
|
'iwb_adr_o',
|
| 539 |
|
|
'iwb_stb_o',
|
| 540 |
|
|
'iwb_we_o',
|
| 541 |
|
|
'iwb_sel_o',
|
| 542 |
|
|
'iwb_dat_o',
|
| 543 |
|
|
'iwb_cti_o',
|
| 544 |
|
|
'iwb_bte_o',
|
| 545 |
|
|
'dwb_ack_i',
|
| 546 |
|
|
'dwb_err_i',
|
| 547 |
|
|
'dwb_rty_i',
|
| 548 |
|
|
'dwb_dat_i',
|
| 549 |
|
|
'dwb_cyc_o',
|
| 550 |
|
|
'dwb_adr_o',
|
| 551 |
|
|
'dwb_stb_o',
|
| 552 |
|
|
'dwb_we_o',
|
| 553 |
|
|
'dwb_sel_o',
|
| 554 |
|
|
'dwb_dat_o',
|
| 555 |
|
|
'dwb_cti_o',
|
| 556 |
|
|
'dwb_bte_o'
|
| 557 |
|
|
],
|
| 558 |
|
|
'module_name' => 'or1200',
|
| 559 |
|
|
'gen_hw_files' => [
|
| 560 |
|
|
'/mpsoc/src_processor/or1200/verilog/or1200_definesfrename_sep_tlib/or1200_defines.v'
|
| 561 |
|
|
],
|
| 562 |
|
|
'gui_status' => {
|
| 563 |
|
|
'timeout' => 0,
|
| 564 |
|
|
'status' => 'ideal'
|
| 565 |
|
|
},
|
| 566 |
|
|
'version' => 32
|
| 567 |
|
|
}, 'ip_gen' );
|
