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[/] [an-fpga-implementation-of-low-latency-noc-based-mpsoc/] [trunk/] [mpsoc/] [perl_gui/] [lib/] [ip/] [Processor/] [lm32.IP] - Blame information for rev 38

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#######################################################################
##      File: lm32.IP
##
##      Copyright (C) 2014-2016  Alireza Monemi
##
##      This file is part of ProNoC 1.7.0
##
##      WARNING: THIS IS AN AUTO-GENERATED FILE. CHANGES TO IT
##      MAY CAUSE UNEXPECTED BEHAIVOR.
################################################################################
 
$lm32 = bless( {
                 'hdl_files' => [
                                  '/mpsoc/src_processor/lm32/verilog/src/er1.v',
                                  '/mpsoc/src_processor/lm32/verilog/src/JTAGB.v',
                                  '/mpsoc/src_processor/lm32/verilog/src/jtag_lm32.v',
                                  '/mpsoc/src_processor/lm32/verilog/src/lm32.v',
                                  '/mpsoc/src_processor/lm32/verilog/src/lm32_adder.v',
                                  '/mpsoc/src_processor/lm32/verilog/src/lm32_addsub.v',
                                  '/mpsoc/src_processor/lm32/verilog/src/lm32_cpu.v',
                                  '/mpsoc/src_processor/lm32/verilog/src/lm32_dcache.v',
                                  '/mpsoc/src_processor/lm32/verilog/src/lm32_debug.v',
                                  '/mpsoc/src_processor/lm32/verilog/src/lm32_decoder.v',
                                  '/mpsoc/src_processor/lm32/verilog/src/lm32_functions.v',
                                  '/mpsoc/src_processor/lm32/verilog/src/lm32_icache.v',
                                  '/mpsoc/src_processor/lm32/verilog/src/lm32_include.v',
                                  '/mpsoc/src_processor/lm32/verilog/src/lm32_instruction_unit.v',
                                  '/mpsoc/src_processor/lm32/verilog/src/lm32_interrupt.v',
                                  '/mpsoc/src_processor/lm32/verilog/src/lm32_jtag.v',
                                  '/mpsoc/src_processor/lm32/verilog/src/lm32_load_store_unit.v',
                                  '/mpsoc/src_processor/lm32/verilog/src/lm32_logic_op.v',
                                  '/mpsoc/src_processor/lm32/verilog/src/lm32_mc_arithmetic.v',
                                  '/mpsoc/src_processor/lm32/verilog/src/lm32_monitor.v',
                                  '/mpsoc/src_processor/lm32/verilog/src/lm32_multiplier.v',
                                  '/mpsoc/src_processor/lm32/verilog/src/lm32_ram.v',
                                  '/mpsoc/src_processor/lm32/verilog/src/lm32_shifter.v',
                                  '/mpsoc/src_processor/lm32/verilog/src/lm32_simtrace.v',
                                  '/mpsoc/src_processor/lm32/verilog/src/lm32_top.v',
                                  '/mpsoc/src_processor/lm32/verilog/src/spiprog.v',
                                  '/mpsoc/src_processor/lm32/verilog/src/system_conf.v',
                                  '/mpsoc/src_processor/lm32/verilog/src/typea.v',
                                  '/mpsoc/src_processor/lm32/verilog/src/typeb.v'
                                ],
                 'category' => 'Processor',
                 'sockets' => {
                                'interrupt_peripheral' => {
                                                            'type' => 'param',
                                                            'interrupt_peripheral' => {},
                                                            '0' => {
                                                                     'name' => 'interrupt_peripheral'
                                                                   },
                                                            'value' => 'INTR_NUM',
                                                            'connection_num' => 'single connection'
                                                          }
                              },
                 'sw_files' => [
                                 '/mpsoc/src_processor/lm32/sw/crt0ram.S',
                                 '/mpsoc/src_processor/lm32/sw/linker.ld',
                                 '/mpsoc/src_processor/lm32/sw/lm32_system.h',
                                 '/mpsoc/src_processor/lm32/sw/Makefile',
                                 '/mpsoc/src_processor/lm32/sw/program',
                                 '/mpsoc/src_processor/program.sh',
                                 '/mpsoc/src_processor/lm32/sw/define_printf.h',
                                 '/mpsoc/src_processor/src_lib/simple-printf'
                               ],
                 'unused' => {
                               'plug:wb_master[0]' => [
                                                        'tag_o'
                                                      ],
                               'plug:wb_master[1]' => [
                                                        'tag_o'
                                                      ]
                             },
                 'module_name' => 'lm32',
                 'parameters_order' => [
                                         'INTR_NUM',
                                         'CFG_PL_MULTIPLY',
                                         'CFG_PL_BARREL_SHIFT',
                                         'CFG_SIGN_EXTEND',
                                         'CFG_MC_DIVIDE'
                                       ],
                 'system_h' => '#include "lm32_system.h"
inline void nop (void) {
        asm volatile ("nop");
}',
                 'modules' => {
                                'lm32' => {}
                              },
                 'ip_name' => 'lm32',
                 'plugs' => {
                              'reset' => {
                                           '0' => {
                                                    'name' => 'reset'
                                                  },
                                           'type' => 'num',
                                           'reset' => {},
                                           '1' => {
                                                    'name' => 'reset_1'
                                                  },
                                           'value' => 1
                                         },
                              'clk' => {
                                         '0' => {
                                                  'name' => 'clk'
                                                },
                                         'type' => 'num',
                                         'clk' => {},
                                         'value' => 1
                                       },
                              'enable' => {
                                            'enable' => {},
                                            'type' => 'num',
                                            '0' => {
                                                     'name' => 'enable'
                                                   },
                                            'value' => 1
                                          },
                              'wb_master' => {
                                               '1' => {
                                                        'name' => 'dwb'
                                                      },
                                               'value' => 2,
                                               '0' => {
                                                        'name' => 'iwb'
                                                      },
                                               'type' => 'num',
                                               'wb_master' => {}
                                             }
                            },
                 'ports' => {
                              'interrupt' => {
                                               'intfc_port' => 'int_i',
                                               'type' => 'input',
                                               'range' => '(32-1):0',
                                               'intfc_name' => 'socket:interrupt_peripheral[array]'
                                             },
                              'D_ACK_I' => {
                                             'intfc_port' => 'ack_i',
                                             'type' => 'input',
                                             'range' => '',
                                             'intfc_name' => 'plug:wb_master[1]'
                                           },
                              'D_RTY_I' => {
                                             'intfc_name' => 'plug:wb_master[1]',
                                             'intfc_port' => 'rty_i',
                                             'range' => '',
                                             'type' => 'input'
                                           },
                              'I_CTI_O' => {
                                             'intfc_name' => 'plug:wb_master[0]',
                                             'type' => 'output',
                                             'range' => '(3-1):0',
                                             'intfc_port' => 'cti_o'
                                           },
                              'I_DAT_O' => {
                                             'type' => 'output',
                                             'range' => '(32-1):0',
                                             'intfc_port' => 'dat_o',
                                             'intfc_name' => 'plug:wb_master[0]'
                                           },
                              'I_DAT_I' => {
                                             'type' => 'input',
                                             'range' => '(32-1):0',
                                             'intfc_port' => 'dat_i',
                                             'intfc_name' => 'plug:wb_master[0]'
                                           },
                              'D_ADR_O' => {
                                             'intfc_name' => 'plug:wb_master[1]',
                                             'intfc_port' => 'adr_o',
                                             'type' => 'output',
                                             'range' => '(32-1):0'
                                           },
                              'I_ACK_I' => {
                                             'intfc_port' => 'ack_i',
                                             'type' => 'input',
                                             'range' => '',
                                             'intfc_name' => 'plug:wb_master[0]'
                                           },
                              'I_BTE_O' => {
                                             'intfc_port' => 'bte_o',
                                             'type' => 'output',
                                             'range' => '(2-1):0',
                                             'intfc_name' => 'plug:wb_master[0]'
                                           },
                              'I_RTY_I' => {
                                             'intfc_name' => 'plug:wb_master[0]',
                                             'range' => '',
                                             'type' => 'input',
                                             'intfc_port' => 'rty_i'
                                           },
                              'clk_i' => {
                                           'type' => 'input',
                                           'range' => '',
                                           'intfc_port' => 'clk_i',
                                           'intfc_name' => 'plug:clk[0]'
                                         },
                              'D_CTI_O' => {
                                             'intfc_name' => 'plug:wb_master[1]',
                                             'range' => '(3-1):0',
                                             'type' => 'output',
                                             'intfc_port' => 'cti_o'
                                           },
                              'D_DAT_I' => {
                                             'intfc_name' => 'plug:wb_master[1]',
                                             'type' => 'input',
                                             'range' => '(32-1):0',
                                             'intfc_port' => 'dat_i'
                                           },
                              'D_WE_O' => {
                                            'intfc_name' => 'plug:wb_master[1]',
                                            'intfc_port' => 'we_o',
                                            'range' => '',
                                            'type' => 'output'
                                          },
                              'rst_i' => {
                                           'intfc_name' => 'plug:reset[0]',
                                           'type' => 'input',
                                           'range' => '',
                                           'intfc_port' => 'reset_i'
                                         },
                              'en_i' => {
                                          'type' => 'input',
                                          'range' => '',
                                          'intfc_port' => 'enable_i',
                                          'intfc_name' => 'plug:enable[0]'
                                        },
                              'D_BTE_O' => {
                                             'intfc_name' => 'plug:wb_master[1]',
                                             'intfc_port' => 'bte_o',
                                             'type' => 'output',
                                             'range' => '(2-1):0'
                                           },
                              'I_SEL_O' => {
                                             'intfc_name' => 'plug:wb_master[0]',
                                             'range' => '(4-1):0',
                                             'type' => 'output',
                                             'intfc_port' => 'sel_o'
                                           },
                              'D_DAT_O' => {
                                             'intfc_name' => 'plug:wb_master[1]',
                                             'type' => 'output',
                                             'range' => '(32-1):0',
                                             'intfc_port' => 'dat_o'
                                           },
                              'D_ERR_I' => {
                                             'intfc_name' => 'plug:wb_master[1]',
                                             'intfc_port' => 'err_i',
                                             'range' => '',
                                             'type' => 'input'
                                           },
                              'I_STB_O' => {
                                             'type' => 'output',
                                             'range' => '',
                                             'intfc_port' => 'stb_o',
                                             'intfc_name' => 'plug:wb_master[0]'
                                           },
                              'I_WE_O' => {
                                            'intfc_name' => 'plug:wb_master[0]',
                                            'intfc_port' => 'we_o',
                                            'range' => '',
                                            'type' => 'output'
                                          },
                              'I_ADR_O' => {
                                             'intfc_name' => 'plug:wb_master[0]',
                                             'type' => 'output',
                                             'range' => '(32-1):0',
                                             'intfc_port' => 'adr_o'
                                           },
                              'I_ERR_I' => {
                                             'intfc_name' => 'plug:wb_master[0]',
                                             'type' => 'input',
                                             'range' => '',
                                             'intfc_port' => 'err_i'
                                           },
                              'D_STB_O' => {
                                             'intfc_name' => 'plug:wb_master[1]',
                                             'intfc_port' => 'stb_o',
                                             'range' => '',
                                             'type' => 'output'
                                           },
                              'D_CYC_O' => {
                                             'intfc_name' => 'plug:wb_master[1]',
                                             'intfc_port' => 'cyc_o',
                                             'range' => '',
                                             'type' => 'output'
                                           },
                              'D_SEL_O' => {
                                             'range' => '(4-1):0',
                                             'type' => 'output',
                                             'intfc_port' => 'sel_o',
                                             'intfc_name' => 'plug:wb_master[1]'
                                           },
                              'I_CYC_O' => {
                                             'intfc_name' => 'plug:wb_master[0]',
                                             'intfc_port' => 'cyc_o',
                                             'type' => 'output',
                                             'range' => ''
                                           }
                            },
                 'description' => 'The LatticeMico32 is a 32-bit Harvard, RISC architecture "soft" microprocessor, available for free with an open IP core licensing agreement.
 
for more information vist: http://www.latticesemi.com/en/Products/DesignSoftwareAndIP/IntellectualProperty/IPCore/IPCores02/LatticeMico32.aspx',
                 'ports_order' => [
                                    'clk_i',
                                    'rst_i',
                                    'en_i',
                                    'interrupt',
                                    'I_DAT_I',
                                    'I_ACK_I',
                                    'I_ERR_I',
                                    'I_RTY_I',
                                    'I_DAT_O',
                                    'I_ADR_O',
                                    'I_CYC_O',
                                    'I_SEL_O',
                                    'I_STB_O',
                                    'I_WE_O',
                                    'I_CTI_O',
                                    'I_BTE_O',
                                    'D_DAT_I',
                                    'D_ACK_I',
                                    'D_ERR_I',
                                    'D_RTY_I',
                                    'D_DAT_O',
                                    'D_ADR_O',
                                    'D_CYC_O',
                                    'D_SEL_O',
                                    'D_STB_O',
                                    'D_WE_O',
                                    'D_CTI_O',
                                    'D_BTE_O'
                                  ],
                 'file_name' => '/home/alireza/Mywork/mpsoc/src_processor/lm32/verilog/src/lm32.v',
                 'version' => 2,
                 'parameters' => {
                                   'CFG_MC_DIVIDE' => {
                                                        'global_param' => 0,
                                                        'content' => '"ENABLED","DISABLED"',
                                                        'info' => undef,
                                                        'redefine_param' => 1,
                                                        'default' => '"DISABLED"',
                                                        'type' => 'Fixed'
                                                      },
                                   'INTR_NUM' => {
                                                   'redefine_param' => 1,
                                                   'info' => undef,
                                                   'type' => 'Fixed',
                                                   'default' => '32',
                                                   'content' => '',
                                                   'global_param' => 0
                                                 },
                                   'CFG_SIGN_EXTEND' => {
                                                          'type' => 'Fixed',
                                                          'default' => '"ENABLED"',
                                                          'redefine_param' => 1,
                                                          'info' => undef,
                                                          'content' => '"ENABLED","DISABLED"',
                                                          'global_param' => 0
                                                        },
                                   'CFG_PL_MULTIPLY' => {
                                                          'content' => '"ENABLED","DISABLED"',
                                                          'global_param' => 0,
                                                          'redefine_param' => 1,
                                                          'info' => undef,
                                                          'type' => 'Fixed',
                                                          'default' => '"ENABLED"'
                                                        },
                                   'CFG_PL_BARREL_SHIFT' => {
                                                              'content' => '"ENABLED","DISABLED"',
                                                              'global_param' => 0,
                                                              'type' => 'Fixed',
                                                              'default' => '"ENABLED"',
                                                              'redefine_param' => 1,
                                                              'info' => undef
                                                            }
                                 },
                 'gui_status' => {
                                   'status' => 'ideal',
                                   'timeout' => 0
                                 }
               }, 'ip_gen' );

Line No.	Rev	Author	Line
1	25	alirezamon	`#######################################################################`
2			`## File: lm32.IP`
3			`##`
4			`## Copyright (C) 2014-2016 Alireza Monemi`
5			`##`
6	38	alirezamon	`## This file is part of ProNoC 1.7.0`
7	25	alirezamon	`##`
8			`## WARNING: THIS IS AN AUTO-GENERATED FILE. CHANGES TO IT`
9			`## MAY CAUSE UNEXPECTED BEHAIVOR.`
10			`################################################################################`
11
12			`$lm32 = bless( {`
13			`'hdl_files' => [`
14			`'/mpsoc/src_processor/lm32/verilog/src/er1.v',`
15			`'/mpsoc/src_processor/lm32/verilog/src/JTAGB.v',`
16			`'/mpsoc/src_processor/lm32/verilog/src/jtag_lm32.v',`
17			`'/mpsoc/src_processor/lm32/verilog/src/lm32.v',`
18			`'/mpsoc/src_processor/lm32/verilog/src/lm32_adder.v',`
19			`'/mpsoc/src_processor/lm32/verilog/src/lm32_addsub.v',`
20			`'/mpsoc/src_processor/lm32/verilog/src/lm32_cpu.v',`
21			`'/mpsoc/src_processor/lm32/verilog/src/lm32_dcache.v',`
22			`'/mpsoc/src_processor/lm32/verilog/src/lm32_debug.v',`
23			`'/mpsoc/src_processor/lm32/verilog/src/lm32_decoder.v',`
24			`'/mpsoc/src_processor/lm32/verilog/src/lm32_functions.v',`
25			`'/mpsoc/src_processor/lm32/verilog/src/lm32_icache.v',`
26			`'/mpsoc/src_processor/lm32/verilog/src/lm32_include.v',`
27			`'/mpsoc/src_processor/lm32/verilog/src/lm32_instruction_unit.v',`
28			`'/mpsoc/src_processor/lm32/verilog/src/lm32_interrupt.v',`
29			`'/mpsoc/src_processor/lm32/verilog/src/lm32_jtag.v',`
30			`'/mpsoc/src_processor/lm32/verilog/src/lm32_load_store_unit.v',`
31			`'/mpsoc/src_processor/lm32/verilog/src/lm32_logic_op.v',`
32			`'/mpsoc/src_processor/lm32/verilog/src/lm32_mc_arithmetic.v',`
33			`'/mpsoc/src_processor/lm32/verilog/src/lm32_monitor.v',`
34			`'/mpsoc/src_processor/lm32/verilog/src/lm32_multiplier.v',`
35			`'/mpsoc/src_processor/lm32/verilog/src/lm32_ram.v',`
36			`'/mpsoc/src_processor/lm32/verilog/src/lm32_shifter.v',`
37			`'/mpsoc/src_processor/lm32/verilog/src/lm32_simtrace.v',`
38			`'/mpsoc/src_processor/lm32/verilog/src/lm32_top.v',`
39			`'/mpsoc/src_processor/lm32/verilog/src/spiprog.v',`
40			`'/mpsoc/src_processor/lm32/verilog/src/system_conf.v',`
41			`'/mpsoc/src_processor/lm32/verilog/src/typea.v',`
42			`'/mpsoc/src_processor/lm32/verilog/src/typeb.v'`
43			`],`
44	38	alirezamon	`'category' => 'Processor',`
45	25	alirezamon	`'sockets' => {`
46			`'interrupt_peripheral' => {`
47	38	alirezamon	`'type' => 'param',`
48	25	alirezamon	`'interrupt_peripheral' => {},`
49			`'0' => {`
50			`'name' => 'interrupt_peripheral'`
51			`},`
52	38	alirezamon	`'value' => 'INTR_NUM',`
53			`'connection_num' => 'single connection'`
54	25	alirezamon	`}`
55			`},`
56			`'sw_files' => [`
57			`'/mpsoc/src_processor/lm32/sw/crt0ram.S',`
58			`'/mpsoc/src_processor/lm32/sw/linker.ld',`
59			`'/mpsoc/src_processor/lm32/sw/lm32_system.h',`
60			`'/mpsoc/src_processor/lm32/sw/Makefile',`
61			`'/mpsoc/src_processor/lm32/sw/program',`
62	38	alirezamon	`'/mpsoc/src_processor/program.sh',`
63			`'/mpsoc/src_processor/lm32/sw/define_printf.h',`
64			`'/mpsoc/src_processor/src_lib/simple-printf'`
65	25	alirezamon	`],`
66	38	alirezamon	`'unused' => {`
67			`'plug:wb_master[0]' => [`
68			`'tag_o'`
69			`],`
70			`'plug:wb_master[1]' => [`
71			`'tag_o'`
72			`]`
73			`},`
74			`'module_name' => 'lm32',`
75			`'parameters_order' => [`
76			`'INTR_NUM',`
77			`'CFG_PL_MULTIPLY',`
78			`'CFG_PL_BARREL_SHIFT',`
79			`'CFG_SIGN_EXTEND',`
80			`'CFG_MC_DIVIDE'`
81			`],`
82			`'system_h' => '#include "lm32_system.h"`
83			`inline void nop (void) {`
84			`asm volatile ("nop");`
85			`}',`
86			`'modules' => {`
87			`'lm32' => {}`
88			`},`
89			`'ip_name' => 'lm32',`
90	25	alirezamon	`'plugs' => {`
91			`'reset' => {`
92	38	alirezamon	`'0' => {`
93			`'name' => 'reset'`
94			`},`
95			`'type' => 'num',`
96			`'reset' => {},`
97	25	alirezamon	`'1' => {`
98			`'name' => 'reset_1'`
99			`},`
100	38	alirezamon	`'value' => 1`
101	25	alirezamon	`},`
102			`'clk' => {`
103			`'0' => {`
104			`'name' => 'clk'`
105			`},`
106	38	alirezamon	`'type' => 'num',`
107			`'clk' => {},`
108			`'value' => 1`
109			`},`
110			`'enable' => {`
111			`'enable' => {},`
112			`'type' => 'num',`
113			`'0' => {`
114			`'name' => 'enable'`
115			`},`
116			`'value' => 1`
117			`},`
118			`'wb_master' => {`
119			`'1' => {`
120			`'name' => 'dwb'`
121			`},`
122			`'value' => 2,`
123			`'0' => {`
124			`'name' => 'iwb'`
125			`},`
126			`'type' => 'num',`
127			`'wb_master' => {}`
128			`}`
129	25	alirezamon	`},`
130			`'ports' => {`
131	38	alirezamon	`'interrupt' => {`
132			`'intfc_port' => 'int_i',`
133			`'type' => 'input',`
134			`'range' => '(32-1):0',`
135			`'intfc_name' => 'socket:interrupt_peripheral[array]'`
136			`},`
137			`'D_ACK_I' => {`
138			`'intfc_port' => 'ack_i',`
139			`'type' => 'input',`
140			`'range' => '',`
141			`'intfc_name' => 'plug:wb_master[1]'`
142	25	alirezamon	`},`
143	38	alirezamon	`'D_RTY_I' => {`
144			`'intfc_name' => 'plug:wb_master[1]',`
145			`'intfc_port' => 'rty_i',`
146			`'range' => '',`
147	25	alirezamon	`'type' => 'input'`
148			`},`
149			`'I_CTI_O' => {`
150			`'intfc_name' => 'plug:wb_master[0]',`
151	38	alirezamon	`'type' => 'output',`
152	25	alirezamon	`'range' => '(3-1):0',`
153	38	alirezamon	`'intfc_port' => 'cti_o'`
154	25	alirezamon	`},`
155	38	alirezamon	`'I_DAT_O' => {`
156			`'type' => 'output',`
157			`'range' => '(32-1):0',`
158			`'intfc_port' => 'dat_o',`
159			`'intfc_name' => 'plug:wb_master[0]'`
160	25	alirezamon	`},`
161	38	alirezamon	`'I_DAT_I' => {`
162			`'type' => 'input',`
163	25	alirezamon	`'range' => '(32-1):0',`
164	38	alirezamon	`'intfc_port' => 'dat_i',`
165			`'intfc_name' => 'plug:wb_master[0]'`
166	25	alirezamon	`},`
167	38	alirezamon	`'D_ADR_O' => {`
168	25	alirezamon	`'intfc_name' => 'plug:wb_master[1]',`
169	38	alirezamon	`'intfc_port' => 'adr_o',`
170			`'type' => 'output',`
171			`'range' => '(32-1):0'`
172	25	alirezamon	`},`
173	38	alirezamon	`'I_ACK_I' => {`
174			`'intfc_port' => 'ack_i',`
175			`'type' => 'input',`
176	25	alirezamon	`'range' => '',`
177	38	alirezamon	`'intfc_name' => 'plug:wb_master[0]'`
178	25	alirezamon	`},`
179	38	alirezamon	`'I_BTE_O' => {`
180			`'intfc_port' => 'bte_o',`
181			`'type' => 'output',`
182			`'range' => '(2-1):0',`
183			`'intfc_name' => 'plug:wb_master[0]'`
184			`},`
185			`'I_RTY_I' => {`
186	25	alirezamon	`'intfc_name' => 'plug:wb_master[0]',`
187			`'range' => '',`
188	38	alirezamon	`'type' => 'input',`
189			`'intfc_port' => 'rty_i'`
190	25	alirezamon	`},`
191	38	alirezamon	`'clk_i' => {`
192			`'type' => 'input',`
193			`'range' => '',`
194			`'intfc_port' => 'clk_i',`
195			`'intfc_name' => 'plug:clk[0]'`
196			`},`
197			`'D_CTI_O' => {`
198	25	alirezamon	`'intfc_name' => 'plug:wb_master[1]',`
199	38	alirezamon	`'range' => '(3-1):0',`
200			`'type' => 'output',`
201			`'intfc_port' => 'cti_o'`
202	25	alirezamon	`},`
203	38	alirezamon	`'D_DAT_I' => {`
204	25	alirezamon	`'intfc_name' => 'plug:wb_master[1]',`
205	38	alirezamon	`'type' => 'input',`
206	25	alirezamon	`'range' => '(32-1):0',`
207	38	alirezamon	`'intfc_port' => 'dat_i'`
208	25	alirezamon	`},`
209	38	alirezamon	`'D_WE_O' => {`
210			`'intfc_name' => 'plug:wb_master[1]',`
211	25	alirezamon	`'intfc_port' => 'we_o',`
212			`'range' => '',`
213			`'type' => 'output'`
214			`},`
215			`'rst_i' => {`
216			`'intfc_name' => 'plug:reset[0]',`
217	38	alirezamon	`'type' => 'input',`
218	25	alirezamon	`'range' => '',`
219	38	alirezamon	`'intfc_port' => 'reset_i'`
220	25	alirezamon	`},`
221	38	alirezamon	`'en_i' => {`
222			`'type' => 'input',`
223			`'range' => '',`
224			`'intfc_port' => 'enable_i',`
225			`'intfc_name' => 'plug:enable[0]'`
226			`},`
227	25	alirezamon	`'D_BTE_O' => {`
228	38	alirezamon	`'intfc_name' => 'plug:wb_master[1]',`
229	25	alirezamon	`'intfc_port' => 'bte_o',`
230	38	alirezamon	`'type' => 'output',`
231			`'range' => '(2-1):0'`
232			`},`
233			`'I_SEL_O' => {`
234			`'intfc_name' => 'plug:wb_master[0]',`
235			`'range' => '(4-1):0',`
236			`'type' => 'output',`
237			`'intfc_port' => 'sel_o'`
238			`},`
239			`'D_DAT_O' => {`
240	25	alirezamon	`'intfc_name' => 'plug:wb_master[1]',`
241	38	alirezamon	`'type' => 'output',`
242			`'range' => '(32-1):0',`
243			`'intfc_port' => 'dat_o'`
244	25	alirezamon	`},`
245	38	alirezamon	`'D_ERR_I' => {`
246	25	alirezamon	`'intfc_name' => 'plug:wb_master[1]',`
247	38	alirezamon	`'intfc_port' => 'err_i',`
248	25	alirezamon	`'range' => '',`
249	38	alirezamon	`'type' => 'input'`
250	25	alirezamon	`},`
251			`'I_STB_O' => {`
252	38	alirezamon	`'type' => 'output',`
253			`'range' => '',`
254	25	alirezamon	`'intfc_port' => 'stb_o',`
255	38	alirezamon	`'intfc_name' => 'plug:wb_master[0]'`
256	25	alirezamon	`},`
257	38	alirezamon	`'I_WE_O' => {`
258			`'intfc_name' => 'plug:wb_master[0]',`
259			`'intfc_port' => 'we_o',`
260			`'range' => '',`
261			`'type' => 'output'`
262			`},`
263			`'I_ADR_O' => {`
264	25	alirezamon	`'intfc_name' => 'plug:wb_master[0]',`
265	38	alirezamon	`'type' => 'output',`
266	25	alirezamon	`'range' => '(32-1):0',`
267	38	alirezamon	`'intfc_port' => 'adr_o'`
268	25	alirezamon	`},`
269	38	alirezamon	`'I_ERR_I' => {`
270			`'intfc_name' => 'plug:wb_master[0]',`
271			`'type' => 'input',`
272	25	alirezamon	`'range' => '',`
273	38	alirezamon	`'intfc_port' => 'err_i'`
274	25	alirezamon	`},`
275	38	alirezamon	`'D_STB_O' => {`
276	25	alirezamon	`'intfc_name' => 'plug:wb_master[1]',`
277	38	alirezamon	`'intfc_port' => 'stb_o',`
278	25	alirezamon	`'range' => '',`
279	38	alirezamon	`'type' => 'output'`
280	25	alirezamon	`},`
281	38	alirezamon	`'D_CYC_O' => {`
282			`'intfc_name' => 'plug:wb_master[1]',`
283			`'intfc_port' => 'cyc_o',`
284	25	alirezamon	`'range' => '',`
285	38	alirezamon	`'type' => 'output'`
286	25	alirezamon	`},`
287	38	alirezamon	`'D_SEL_O' => {`
288			`'range' => '(4-1):0',`
289			`'type' => 'output',`
290			`'intfc_port' => 'sel_o',`
291			`'intfc_name' => 'plug:wb_master[1]'`
292			`},`
293			`'I_CYC_O' => {`
294	25	alirezamon	`'intfc_name' => 'plug:wb_master[0]',`
295	38	alirezamon	`'intfc_port' => 'cyc_o',`
296			`'type' => 'output',`
297			`'range' => ''`
298			`}`
299			`},`
300			`'description' => 'The LatticeMico32 is a 32-bit Harvard, RISC architecture "soft" microprocessor, available for free with an open IP core licensing agreement.`
301
302			`for more information vist: http://www.latticesemi.com/en/Products/DesignSoftwareAndIP/IntellectualProperty/IPCore/IPCores02/LatticeMico32.aspx',`
303			`'ports_order' => [`
304			`'clk_i',`
305			`'rst_i',`
306			`'en_i',`
307			`'interrupt',`
308			`'I_DAT_I',`
309			`'I_ACK_I',`
310			`'I_ERR_I',`
311			`'I_RTY_I',`
312			`'I_DAT_O',`
313			`'I_ADR_O',`
314			`'I_CYC_O',`
315			`'I_SEL_O',`
316			`'I_STB_O',`
317			`'I_WE_O',`
318			`'I_CTI_O',`
319			`'I_BTE_O',`
320			`'D_DAT_I',`
321			`'D_ACK_I',`
322			`'D_ERR_I',`
323			`'D_RTY_I',`
324			`'D_DAT_O',`
325			`'D_ADR_O',`
326			`'D_CYC_O',`
327			`'D_SEL_O',`
328			`'D_STB_O',`
329			`'D_WE_O',`
330			`'D_CTI_O',`
331			`'D_BTE_O'`
332			`],`
333			`'file_name' => '/home/alireza/Mywork/mpsoc/src_processor/lm32/verilog/src/lm32.v',`
334			`'version' => 2,`
335			`'parameters' => {`
336			`'CFG_MC_DIVIDE' => {`
337			`'global_param' => 0,`
338			`'content' => '"ENABLED","DISABLED"',`
339			`'info' => undef,`
340			`'redefine_param' => 1,`
341			`'default' => '"DISABLED"',`
342			`'type' => 'Fixed'`
343			`},`
344			`'INTR_NUM' => {`
345			`'redefine_param' => 1,`
346			`'info' => undef,`
347			`'type' => 'Fixed',`
348			`'default' => '32',`
349			`'content' => '',`
350			`'global_param' => 0`
351			`},`
352			`'CFG_SIGN_EXTEND' => {`
353			`'type' => 'Fixed',`
354			`'default' => '"ENABLED"',`
355			`'redefine_param' => 1,`
356			`'info' => undef,`
357			`'content' => '"ENABLED","DISABLED"',`
358			`'global_param' => 0`
359			`},`
360			`'CFG_PL_MULTIPLY' => {`
361			`'content' => '"ENABLED","DISABLED"',`
362			`'global_param' => 0,`
363			`'redefine_param' => 1,`
364			`'info' => undef,`
365			`'type' => 'Fixed',`
366			`'default' => '"ENABLED"'`
367			`},`
368			`'CFG_PL_BARREL_SHIFT' => {`
369			`'content' => '"ENABLED","DISABLED"',`
370			`'global_param' => 0,`
371			`'type' => 'Fixed',`
372			`'default' => '"ENABLED"',`
373			`'redefine_param' => 1,`
374			`'info' => undef`
375			`}`
376			`},`
377			`'gui_status' => {`
378			`'status' => 'ideal',`
379			`'timeout' => 0`
380			`}`
381	25	alirezamon	`}, 'ip_gen' );`

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[/] [an-fpga-implementation-of-low-latency-noc-based-mpsoc/] [trunk/] [mpsoc/] [perl_gui/] [lib/] [ip/] [Processor/] [lm32.IP] - Blame information for rev 38