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[/] [an-fpga-implementation-of-low-latency-noc-based-mpsoc/] [trunk/] [mpsoc/] [perl_gui/] [lib/] [ip/] [RAM/] [dual_port_ram.IP] - Blame information for rev 34

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#######################################################################
##      File: dual_port_ram.IP
##
##      Copyright (C) 2014-2016  Alireza Monemi
##
##      This file is part of ProNoC 1.6.0
##
##      WARNING: THIS IS AN AUTO-GENERATED FILE. CHANGES TO IT
##      MAY CAUSE UNEXPECTED BEHAIVOR.
################################################################################
 
$wb_dual_port_ram = bless( {
                             'hdl_files' => [
                                              '/mpsoc/src_peripheral/ram/generic_ram.v',
                                              '/mpsoc/src_peripheral/ram/byte_enabled_generic_ram.sv',
                                              '/mpsoc/src_peripheral/ram/wb_dual_port_ram.v',
                                              '/mpsoc/src_peripheral/ram/wb_bram_ctrl.v'
                                            ],
                             'module_name' => 'wb_dual_port_ram',
                             'category' => 'RAM',
                             'plugs' => {
                                          'clk' => {
                                                     'clk' => {},
                                                     'value' => 1,
                                                     'type' => 'num',
                                                     '0' => {
                                                              'name' => 'clk'
                                                            }
                                                   },
                                          'reset' => {
                                                       '0' => {
                                                                'name' => 'reset'
                                                              },
                                                       'type' => 'num',
                                                       'value' => 1,
                                                       'reset' => {}
                                                     },
                                          'wb_slave' => {
                                                          'value' => 2,
                                                          '1' => {
                                                                   'addr' => '0x0000_0000       0x3fff_ffff             RAM',
                                                                   'width' => 'WB_Aw',
                                                                   'name' => 'wb_b'
                                                                 },
                                                          'type' => 'num',
                                                          'wb_slave' => {},
                                                          '0' => {
                                                                   'addr' => '0x0000_0000       0x3fff_ffff             RAM',
                                                                   'width' => 'WB_Aw',
                                                                   'name' => 'wb_a'
                                                                 }
                                                        }
                                        },
                             'ports' => {
                                          'sb_err_o' => {
                                                          'range' => '',
                                                          'intfc_port' => 'err_o',
                                                          'intfc_name' => 'plug:wb_slave[1]',
                                                          'type' => 'output'
                                                        },
                                          'sa_stb_i' => {
                                                          'type' => 'input',
                                                          'intfc_name' => 'plug:wb_slave[0]',
                                                          'intfc_port' => 'stb_i',
                                                          'range' => ''
                                                        },
                                          'sb_addr_i' => {
                                                           'intfc_name' => 'plug:wb_slave[1]',
                                                           'type' => 'input',
                                                           'intfc_port' => 'adr_i',
                                                           'range' => 'Aw-1       :   0'
                                                         },
                                          'sb_rty_o' => {
                                                          'type' => 'output',
                                                          'intfc_name' => 'plug:wb_slave[1]',
                                                          'intfc_port' => 'rty_o',
                                                          'range' => ''
                                                        },
                                          'sb_cyc_i' => {
                                                          'intfc_port' => 'cyc_i',
                                                          'range' => '',
                                                          'type' => 'input',
                                                          'intfc_name' => 'plug:wb_slave[1]'
                                                        },
                                          'sa_we_i' => {
                                                         'intfc_port' => 'we_i',
                                                         'range' => '',
                                                         'intfc_name' => 'plug:wb_slave[0]',
                                                         'type' => 'input'
                                                       },
                                          'sb_we_i' => {
                                                         'intfc_port' => 'we_i',
                                                         'range' => '',
                                                         'intfc_name' => 'plug:wb_slave[1]',
                                                         'type' => 'input'
                                                       },
                                          'sb_dat_i' => {
                                                          'type' => 'input',
                                                          'intfc_name' => 'plug:wb_slave[1]',
                                                          'range' => 'Dw-1       :   0',
                                                          'intfc_port' => 'dat_i'
                                                        },
                                          'sa_err_o' => {
                                                          'type' => 'output',
                                                          'intfc_name' => 'plug:wb_slave[0]',
                                                          'range' => '',
                                                          'intfc_port' => 'err_o'
                                                        },
                                          'sb_sel_i' => {
                                                          'type' => 'input',
                                                          'intfc_name' => 'plug:wb_slave[1]',
                                                          'range' => 'SELw-1     :   0',
                                                          'intfc_port' => 'sel_i'
                                                        },
                                          'sb_ack_o' => {
                                                          'type' => 'output',
                                                          'intfc_name' => 'plug:wb_slave[1]',
                                                          'range' => '',
                                                          'intfc_port' => 'ack_o'
                                                        },
                                          'sb_cti_i' => {
                                                          'intfc_port' => 'cti_i',
                                                          'range' => 'CTIw-1     :   0',
                                                          'type' => 'input',
                                                          'intfc_name' => 'plug:wb_slave[1]'
                                                        },
                                          'sb_stb_i' => {
                                                          'intfc_port' => 'stb_i',
                                                          'range' => '',
                                                          'intfc_name' => 'plug:wb_slave[1]',
                                                          'type' => 'input'
                                                        },
                                          'sa_cti_i' => {
                                                          'type' => 'input',
                                                          'intfc_name' => 'plug:wb_slave[0]',
                                                          'intfc_port' => 'cti_i',
                                                          'range' => 'CTIw-1     :   0'
                                                        },
                                          'sb_bte_i' => {
                                                          'type' => 'input',
                                                          'intfc_name' => 'plug:wb_slave[1]',
                                                          'range' => 'BTEw-1     :   0',
                                                          'intfc_port' => 'bte_i'
                                                        },
                                          'sa_rty_o' => {
                                                          'intfc_name' => 'plug:wb_slave[0]',
                                                          'type' => 'output',
                                                          'range' => '',
                                                          'intfc_port' => 'rty_o'
                                                        },
                                          'clk' => {
                                                     'intfc_port' => 'clk_i',
                                                     'range' => '',
                                                     'type' => 'input',
                                                     'intfc_name' => 'plug:clk[0]'
                                                   },
                                          'sa_dat_o' => {
                                                          'type' => 'output',
                                                          'intfc_name' => 'plug:wb_slave[0]',
                                                          'range' => 'Dw-1       :   0',
                                                          'intfc_port' => 'dat_o'
                                                        },
                                          'sa_dat_i' => {
                                                          'type' => 'input',
                                                          'intfc_name' => 'plug:wb_slave[0]',
                                                          'intfc_port' => 'dat_i',
                                                          'range' => 'Dw-1       :   0'
                                                        },
                                          'sa_bte_i' => {
                                                          'intfc_name' => 'plug:wb_slave[0]',
                                                          'type' => 'input',
                                                          'intfc_port' => 'bte_i',
                                                          'range' => 'BTEw-1     :   0'
                                                        },
                                          'sa_ack_o' => {
                                                          'range' => '',
                                                          'intfc_port' => 'ack_o',
                                                          'type' => 'output',
                                                          'intfc_name' => 'plug:wb_slave[0]'
                                                        },
                                          'sa_sel_i' => {
                                                          'type' => 'input',
                                                          'intfc_name' => 'plug:wb_slave[0]',
                                                          'intfc_port' => 'sel_i',
                                                          'range' => 'SELw-1     :   0'
                                                        },
                                          'reset' => {
                                                       'intfc_name' => 'plug:reset[0]',
                                                       'type' => 'input',
                                                       'range' => '',
                                                       'intfc_port' => 'reset_i'
                                                     },
                                          'sa_cyc_i' => {
                                                          'range' => '',
                                                          'intfc_port' => 'cyc_i',
                                                          'type' => 'input',
                                                          'intfc_name' => 'plug:wb_slave[0]'
                                                        },
                                          'sa_tag_i' => {
                                                          'type' => 'input',
                                                          'intfc_name' => 'plug:wb_slave[0]',
                                                          'intfc_port' => 'tag_i',
                                                          'range' => 'TAGw-1     :   0'
                                                        },
                                          'sb_dat_o' => {
                                                          'type' => 'output',
                                                          'intfc_name' => 'plug:wb_slave[1]',
                                                          'range' => 'Dw-1       :   0',
                                                          'intfc_port' => 'dat_o'
                                                        },
                                          'sa_addr_i' => {
                                                           'intfc_port' => 'adr_i',
                                                           'range' => 'Aw-1       :   0',
                                                           'type' => 'input',
                                                           'intfc_name' => 'plug:wb_slave[0]'
                                                         },
                                          'sb_tag_i' => {
                                                          'intfc_port' => 'tag_i',
                                                          'range' => 'TAGw-1     :   0',
                                                          'type' => 'input',
                                                          'intfc_name' => 'plug:wb_slave[1]'
                                                        }
                                        },
                             'description' => 'Dual port ram.',
                             'parameters' => {
                                               'WB_Aw' => {
                                                            'type' => 'Fixed',
                                                            'redefine_param' => 0,
                                                            'info' => 'Wishbone bus address width in byte',
                                                            'content' => '',
                                                            'deafult' => 'Aw+2',
                                                            'global_param' => 'Don\'t include'
                                                          },
                                               'BTEw' => {
                                                           'info' => 'Parameter',
                                                           'content' => '',
                                                           'type' => 'Fixed',
                                                           'redefine_param' => 1,
                                                           'global_param' => 'Localparam',
                                                           'deafult' => '2'
                                                         },
                                               'MEM_CONTENT_FILE_NAME' => {
                                                                            'type' => 'Entry',
                                                                            'redefine_param' => 1,
                                                                            'content' => '',
                                                                            'info' => 'MEM_FILE_NAME:
The memory file name (without file type extension ) that is used for writting the memory content at initialization time.
 
File Path:
For bus-based SoC the file path is {ProNoC_work}/SOC/{soc_name}/sw/RAM/{file_type}/{MEM_FILE_NAME}.
For NoC-based MPSoC the file path is {ProNoC_work}/MPSOC/{mpsoc_name}/sw/tile{tile_num}/RAM/{file_type}/{MEM_FILE_NAME}
 
file_type:
memh: hexadecimal-string format . It will be used for initialing the Generic RAM using $readmemh command.
mif: memory initialization file format. This file can be used to initialize Altera FPGA memory. Also if the JTAG_CONECT is selected as ALTERA_IEMC it can be used for changing memory content at run time . ',
                                                                            'deafult' => '"ram0"',
                                                                            'global_param' => 'Localparam'
                                                                          },
                                               'TAGw' => {
                                                           'info' => 'Parameter',
                                                           'content' => '',
                                                           'type' => 'Fixed',
                                                           'redefine_param' => 1,
                                                           'global_param' => 'Localparam',
                                                           'deafult' => '3'
                                                         },
                                               'CTIw' => {
                                                           'redefine_param' => 1,
                                                           'type' => 'Fixed',
                                                           'content' => '',
                                                           'info' => 'Parameter',
                                                           'deafult' => '3',
                                                           'global_param' => 'Localparam'
                                                         },
                                               'INIT_FILE_PATH' => {
                                                                     'redefine_param' => 1,
                                                                     'type' => 'Fixed',
                                                                     'info' => undef,
                                                                     'content' => '',
                                                                     'deafult' => 'SW_LOC',
                                                                     'global_param' => 'Don\'t include'
                                                                   },
                                               'Aw' => {
                                                         'deafult' => '12',
                                                         'global_param' => 'Localparam',
                                                         'type' => 'Spin-button',
                                                         'redefine_param' => 1,
                                                         'info' => 'Ram address width',
                                                         'content' => '2,31,1'
                                                       },
                                               'INITIAL_EN' => {
                                                                 'type' => 'Combo-box',
                                                                 'redefine_param' => 1,
                                                                 'info' => 'If selected as "YES", the memory content will be initialized at compilation time using MEM_CONTENT_FILE_NAME.',
                                                                 'content' => '"YES","NO"',
                                                                 'deafult' => '"NO"',
                                                                 'global_param' => 'Localparam'
                                                               },
                                               'RAM_INDEX' => {
                                                                'deafult' => 'CORE_ID',
                                                                'global_param' => 'Localparam',
                                                                'redefine_param' => 1,
                                                                'type' => 'Entry',
                                                                'content' => '',
                                                                'info' => 'RAM_INDEX is a unique number which will be used for initialing the memory content only.
 
'
                                                              },
                                               'SELw' => {
                                                           'deafult' => 'Dw/8',
                                                           'global_param' => 'Localparam',
                                                           'redefine_param' => 1,
                                                           'type' => 'Fixed',
                                                           'info' => 'Parameter',
                                                           'content' => ''
                                                         },
                                               'Dw' => {
                                                         'redefine_param' => 1,
                                                         'type' => 'Spin-button',
                                                         'content' => '4,1024,1',
                                                         'info' => 'Ram data width in Bits',
                                                         'deafult' => '32',
                                                         'global_param' => 'Localparam'
                                                       },
                                               'PORT_B_BURST_MODE' => {
                                                                        'info' => 'wisbone bus burst mode ebable/disable on port B',
                                                                        'content' => '"DISABLED","ENABLED" ',
                                                                        'redefine_param' => 1,
                                                                        'type' => 'Fixed',
                                                                        'global_param' => 'Localparam',
                                                                        'deafult' => '"ENABLED"'
                                                                      },
                                               'BYTE_WR_EN' => {
                                                                 'content' => '"YES","NO"',
                                                                 'info' => 'Parameter',
                                                                 'type' => 'Combo-box',
                                                                 'redefine_param' => 1,
                                                                 'global_param' => 'Localparam',
                                                                 'deafult' => '"YES"'
                                                               },
                                               'PORT_A_BURST_MODE' => {
                                                                        'deafult' => '"ENABLED"',
                                                                        'global_param' => 'Localparam',
                                                                        'redefine_param' => 1,
                                                                        'type' => 'Combo-box',
                                                                        'content' => '"DISABLED","ENABLED"',
                                                                        'info' => ' wisbone bus burst mode enable/disable on port A'
                                                                      },
                                               'FPGA_VENDOR' => {
                                                                  'redefine_param' => 1,
                                                                  'type' => 'Combo-box',
                                                                  'content' => '"ALTERA","GENERIC"',
                                                                  'info' => 'Parameter',
                                                                  'deafult' => '"GENERIC"',
                                                                  'global_param' => 'Localparam'
                                                                }
                                             },
                             'ports_order' => [
                                                'clk',
                                                'reset',
                                                'sa_dat_i',
                                                'sa_sel_i',
                                                'sa_addr_i',
                                                'sa_tag_i',
                                                'sa_cti_i',
                                                'sa_bte_i',
                                                'sa_stb_i',
                                                'sa_cyc_i',
                                                'sa_we_i',
                                                'sa_dat_o',
                                                'sa_ack_o',
                                                'sa_err_o',
                                                'sa_rty_o',
                                                'sb_dat_i',
                                                'sb_sel_i',
                                                'sb_addr_i',
                                                'sb_tag_i',
                                                'sb_cti_i',
                                                'sb_bte_i',
                                                'sb_stb_i',
                                                'sb_cyc_i',
                                                'sb_we_i',
                                                'sb_dat_o',
                                                'sb_ack_o',
                                                'sb_err_o',
                                                'sb_rty_o'
                                              ],
                             'version' => 6,
                             'gui_status' => {
                                               'timeout' => 0,
                                               'status' => 'ideal'
                                             },
                             'parameters_order' => [
                                                     'Dw',
                                                     'Aw',
                                                     'BYTE_WR_EN',
                                                     'FPGA_VENDOR',
                                                     'TAGw',
                                                     'SELw',
                                                     'CTIw',
                                                     'BTEw',
                                                     'WB_Aw',
                                                     'RAM_INDEX',
                                                     'PORT_A_BURST_MODE',
                                                     'PORT_B_BURST_MODE',
                                                     'INITIAL_EN',
                                                     'MEM_CONTENT_FILE_NAME',
                                                     'INIT_FILE_PATH'
                                                   ],
                             'unused' => undef,
                             'ip_name' => 'dual_port_ram',
                             'modules' => {
                                            'wb_dual_port_ram' => {}
                                          },
                             'file_name' => '/home/alireza/Mywork/mpsoc/src_peripheral/ram/wb_dual_port_ram.v'
                           }, 'ip_gen' );

Line No.	Rev	Author	Line
1	25	alirezamon	`#######################################################################`
2			`## File: dual_port_ram.IP`
3			`##`
4			`## Copyright (C) 2014-2016 Alireza Monemi`
5			`##`
6	34	alirezamon	`## This file is part of ProNoC 1.6.0`
7	25	alirezamon	`##`
8			`## WARNING: THIS IS AN AUTO-GENERATED FILE. CHANGES TO IT`
9			`## MAY CAUSE UNEXPECTED BEHAIVOR.`
10			`################################################################################`
11
12			`$wb_dual_port_ram = bless( {`
13			`'hdl_files' => [`
14			`'/mpsoc/src_peripheral/ram/generic_ram.v',`
15			`'/mpsoc/src_peripheral/ram/byte_enabled_generic_ram.sv',`
16			`'/mpsoc/src_peripheral/ram/wb_dual_port_ram.v',`
17			`'/mpsoc/src_peripheral/ram/wb_bram_ctrl.v'`
18			`],`
19	34	alirezamon	`'module_name' => 'wb_dual_port_ram',`
20			`'category' => 'RAM',`
21	25	alirezamon	`'plugs' => {`
22	28	alirezamon	`'clk' => {`
23			`'clk' => {},`
24			`'value' => 1,`
25	34	alirezamon	`'type' => 'num',`
26	28	alirezamon	`'0' => {`
27			`'name' => 'clk'`
28	34	alirezamon	`}`
29	28	alirezamon	`},`
30	25	alirezamon	`'reset' => {`
31			`'0' => {`
32			`'name' => 'reset'`
33			`},`
34	34	alirezamon	`'type' => 'num',`
35			`'value' => 1,`
36			`'reset' => {}`
37	25	alirezamon	`},`
38			`'wb_slave' => {`
39	34	alirezamon	`'value' => 2,`
40	25	alirezamon	`'1' => {`
41	34	alirezamon	`'addr' => '0x0000_0000 0x3fff_ffff RAM',`
42	25	alirezamon	`'width' => 'WB_Aw',`
43	34	alirezamon	`'name' => 'wb_b'`
44	25	alirezamon	`},`
45	34	alirezamon	`'type' => 'num',`
46			`'wb_slave' => {},`
47	25	alirezamon	`'0' => {`
48	34	alirezamon	`'addr' => '0x0000_0000 0x3fff_ffff RAM',`
49	25	alirezamon	`'width' => 'WB_Aw',`
50	34	alirezamon	`'name' => 'wb_a'`
51			`}`
52	25	alirezamon	`}`
53			`},`
54			`'ports' => {`
55	34	alirezamon	`'sb_err_o' => {`
56			`'range' => '',`
57			`'intfc_port' => 'err_o',`
58			`'intfc_name' => 'plug:wb_slave[1]',`
59			`'type' => 'output'`
60			`},`
61			`'sa_stb_i' => {`
62			`'type' => 'input',`
63			`'intfc_name' => 'plug:wb_slave[0]',`
64			`'intfc_port' => 'stb_i',`
65			`'range' => ''`
66			`},`
67	28	alirezamon	`'sb_addr_i' => {`
68	34	alirezamon	`'intfc_name' => 'plug:wb_slave[1]',`
69			`'type' => 'input',`
70	28	alirezamon	`'intfc_port' => 'adr_i',`
71	34	alirezamon	`'range' => 'Aw-1 : 0'`
72	28	alirezamon	`},`
73	34	alirezamon	`'sb_rty_o' => {`
74			`'type' => 'output',`
75			`'intfc_name' => 'plug:wb_slave[1]',`
76			`'intfc_port' => 'rty_o',`
77			`'range' => ''`
78	25	alirezamon	`},`
79	34	alirezamon	`'sb_cyc_i' => {`
80			`'intfc_port' => 'cyc_i',`
81			`'range' => '',`
82			`'type' => 'input',`
83			`'intfc_name' => 'plug:wb_slave[1]'`
84			`},`
85			`'sa_we_i' => {`
86			`'intfc_port' => 'we_i',`
87			`'range' => '',`
88			`'intfc_name' => 'plug:wb_slave[0]',`
89			`'type' => 'input'`
90			`},`
91			`'sb_we_i' => {`
92			`'intfc_port' => 'we_i',`
93			`'range' => '',`
94			`'intfc_name' => 'plug:wb_slave[1]',`
95			`'type' => 'input'`
96			`},`
97			`'sb_dat_i' => {`
98			`'type' => 'input',`
99			`'intfc_name' => 'plug:wb_slave[1]',`
100			`'range' => 'Dw-1 : 0',`
101			`'intfc_port' => 'dat_i'`
102			`},`
103			`'sa_err_o' => {`
104			`'type' => 'output',`
105	25	alirezamon	`'intfc_name' => 'plug:wb_slave[0]',`
106			`'range' => '',`
107	34	alirezamon	`'intfc_port' => 'err_o'`
108	25	alirezamon	`},`
109	34	alirezamon	`'sb_sel_i' => {`
110			`'type' => 'input',`
111			`'intfc_name' => 'plug:wb_slave[1]',`
112	28	alirezamon	`'range' => 'SELw-1 : 0',`
113	34	alirezamon	`'intfc_port' => 'sel_i'`
114	25	alirezamon	`},`
115	34	alirezamon	`'sb_ack_o' => {`
116			`'type' => 'output',`
117			`'intfc_name' => 'plug:wb_slave[1]',`
118			`'range' => '',`
119			`'intfc_port' => 'ack_o'`
120			`},`
121			`'sb_cti_i' => {`
122	28	alirezamon	`'intfc_port' => 'cti_i',`
123			`'range' => 'CTIw-1 : 0',`
124	34	alirezamon	`'type' => 'input',`
125			`'intfc_name' => 'plug:wb_slave[1]'`
126			`},`
127			`'sb_stb_i' => {`
128			`'intfc_port' => 'stb_i',`
129			`'range' => '',`
130			`'intfc_name' => 'plug:wb_slave[1]',`
131	25	alirezamon	`'type' => 'input'`
132			`},`
133	34	alirezamon	`'sa_cti_i' => {`
134			`'type' => 'input',`
135	25	alirezamon	`'intfc_name' => 'plug:wb_slave[0]',`
136	34	alirezamon	`'intfc_port' => 'cti_i',`
137			`'range' => 'CTIw-1 : 0'`
138			`},`
139			`'sb_bte_i' => {`
140			`'type' => 'input',`
141			`'intfc_name' => 'plug:wb_slave[1]',`
142	25	alirezamon	`'range' => 'BTEw-1 : 0',`
143	34	alirezamon	`'intfc_port' => 'bte_i'`
144	25	alirezamon	`},`
145	34	alirezamon	`'sa_rty_o' => {`
146	28	alirezamon	`'intfc_name' => 'plug:wb_slave[0]',`
147	34	alirezamon	`'type' => 'output',`
148	28	alirezamon	`'range' => '',`
149	34	alirezamon	`'intfc_port' => 'rty_o'`
150	28	alirezamon	`},`
151	34	alirezamon	`'clk' => {`
152			`'intfc_port' => 'clk_i',`
153			`'range' => '',`
154			`'type' => 'input',`
155			`'intfc_name' => 'plug:clk[0]'`
156			`},`
157			`'sa_dat_o' => {`
158			`'type' => 'output',`
159	25	alirezamon	`'intfc_name' => 'plug:wb_slave[0]',`
160	34	alirezamon	`'range' => 'Dw-1 : 0',`
161			`'intfc_port' => 'dat_o'`
162	25	alirezamon	`},`
163	34	alirezamon	`'sa_dat_i' => {`
164			`'type' => 'input',`
165			`'intfc_name' => 'plug:wb_slave[0]',`
166			`'intfc_port' => 'dat_i',`
167			`'range' => 'Dw-1 : 0'`
168			`},`
169			`'sa_bte_i' => {`
170			`'intfc_name' => 'plug:wb_slave[0]',`
171			`'type' => 'input',`
172			`'intfc_port' => 'bte_i',`
173			`'range' => 'BTEw-1 : 0'`
174			`},`
175			`'sa_ack_o' => {`
176	25	alirezamon	`'range' => '',`
177	34	alirezamon	`'intfc_port' => 'ack_o',`
178			`'type' => 'output',`
179			`'intfc_name' => 'plug:wb_slave[0]'`
180	25	alirezamon	`},`
181	34	alirezamon	`'sa_sel_i' => {`
182			`'type' => 'input',`
183			`'intfc_name' => 'plug:wb_slave[0]',`
184			`'intfc_port' => 'sel_i',`
185			`'range' => 'SELw-1 : 0'`
186	25	alirezamon	`},`
187			`'reset' => {`
188			`'intfc_name' => 'plug:reset[0]',`
189	34	alirezamon	`'type' => 'input',`
190	25	alirezamon	`'range' => '',`
191	34	alirezamon	`'intfc_port' => 'reset_i'`
192	25	alirezamon	`},`
193	34	alirezamon	`'sa_cyc_i' => {`
194	28	alirezamon	`'range' => '',`
195	34	alirezamon	`'intfc_port' => 'cyc_i',`
196			`'type' => 'input',`
197			`'intfc_name' => 'plug:wb_slave[0]'`
198	25	alirezamon	`},`
199	34	alirezamon	`'sa_tag_i' => {`
200			`'type' => 'input',`
201			`'intfc_name' => 'plug:wb_slave[0]',`
202			`'intfc_port' => 'tag_i',`
203			`'range' => 'TAGw-1 : 0'`
204	25	alirezamon	`},`
205	34	alirezamon	`'sb_dat_o' => {`
206			`'type' => 'output',`
207	25	alirezamon	`'intfc_name' => 'plug:wb_slave[1]',`
208	34	alirezamon	`'range' => 'Dw-1 : 0',`
209			`'intfc_port' => 'dat_o'`
210	25	alirezamon	`},`
211	28	alirezamon	`'sa_addr_i' => {`
212			`'intfc_port' => 'adr_i',`
213			`'range' => 'Aw-1 : 0',`
214	34	alirezamon	`'type' => 'input',`
215			`'intfc_name' => 'plug:wb_slave[0]'`
216	28	alirezamon	`},`
217			`'sb_tag_i' => {`
218			`'intfc_port' => 'tag_i',`
219			`'range' => 'TAGw-1 : 0',`
220	34	alirezamon	`'type' => 'input',`
221			`'intfc_name' => 'plug:wb_slave[1]'`
222	25	alirezamon	`}`
223			`},`
224	34	alirezamon	`'description' => 'Dual port ram.',`
225			`'parameters' => {`
226			`'WB_Aw' => {`
227			`'type' => 'Fixed',`
228			`'redefine_param' => 0,`
229			`'info' => 'Wishbone bus address width in byte',`
230			`'content' => '',`
231			`'deafult' => 'Aw+2',`
232			`'global_param' => 'Don\'t include'`
233			`},`
234			`'BTEw' => {`
235			`'info' => 'Parameter',`
236			`'content' => '',`
237			`'type' => 'Fixed',`
238			`'redefine_param' => 1,`
239			`'global_param' => 'Localparam',`
240			`'deafult' => '2'`
241			`},`
242			`'MEM_CONTENT_FILE_NAME' => {`
243			`'type' => 'Entry',`
244			`'redefine_param' => 1,`
245			`'content' => '',`
246			`'info' => 'MEM_FILE_NAME:`
247			`The memory file name (without file type extension ) that is used for writting the memory content at initialization time.`
248
249			`File Path:`
250			`For bus-based SoC the file path is {ProNoC_work}/SOC/{soc_name}/sw/RAM/{file_type}/{MEM_FILE_NAME}.`
251			`For NoC-based MPSoC the file path is {ProNoC_work}/MPSOC/{mpsoc_name}/sw/tile{tile_num}/RAM/{file_type}/{MEM_FILE_NAME}`
252
253			`file_type:`
254			`memh: hexadecimal-string format . It will be used for initialing the Generic RAM using $readmemh command.`
255			`mif: memory initialization file format. This file can be used to initialize Altera FPGA memory. Also if the JTAG_CONECT is selected as ALTERA_IEMC it can be used for changing memory content at run time . ',`
256			`'deafult' => '"ram0"',`
257			`'global_param' => 'Localparam'`
258			`},`
259			`'TAGw' => {`
260			`'info' => 'Parameter',`
261			`'content' => '',`
262			`'type' => 'Fixed',`
263			`'redefine_param' => 1,`
264			`'global_param' => 'Localparam',`
265			`'deafult' => '3'`
266			`},`
267			`'CTIw' => {`
268			`'redefine_param' => 1,`
269			`'type' => 'Fixed',`
270			`'content' => '',`
271			`'info' => 'Parameter',`
272			`'deafult' => '3',`
273			`'global_param' => 'Localparam'`
274			`},`
275			`'INIT_FILE_PATH' => {`
276			`'redefine_param' => 1,`
277			`'type' => 'Fixed',`
278			`'info' => undef,`
279			`'content' => '',`
280			`'deafult' => 'SW_LOC',`
281			`'global_param' => 'Don\'t include'`
282			`},`
283			`'Aw' => {`
284			`'deafult' => '12',`
285			`'global_param' => 'Localparam',`
286			`'type' => 'Spin-button',`
287			`'redefine_param' => 1,`
288			`'info' => 'Ram address width',`
289			`'content' => '2,31,1'`
290			`},`
291			`'INITIAL_EN' => {`
292			`'type' => 'Combo-box',`
293			`'redefine_param' => 1,`
294			`'info' => 'If selected as "YES", the memory content will be initialized at compilation time using MEM_CONTENT_FILE_NAME.',`
295			`'content' => '"YES","NO"',`
296			`'deafult' => '"NO"',`
297			`'global_param' => 'Localparam'`
298			`},`
299			`'RAM_INDEX' => {`
300			`'deafult' => 'CORE_ID',`
301			`'global_param' => 'Localparam',`
302			`'redefine_param' => 1,`
303			`'type' => 'Entry',`
304			`'content' => '',`
305			`'info' => 'RAM_INDEX is a unique number which will be used for initialing the memory content only.`
306
307			`'`
308			`},`
309			`'SELw' => {`
310			`'deafult' => 'Dw/8',`
311			`'global_param' => 'Localparam',`
312			`'redefine_param' => 1,`
313			`'type' => 'Fixed',`
314			`'info' => 'Parameter',`
315			`'content' => ''`
316			`},`
317			`'Dw' => {`
318			`'redefine_param' => 1,`
319			`'type' => 'Spin-button',`
320			`'content' => '4,1024,1',`
321			`'info' => 'Ram data width in Bits',`
322			`'deafult' => '32',`
323			`'global_param' => 'Localparam'`
324			`},`
325			`'PORT_B_BURST_MODE' => {`
326			`'info' => 'wisbone bus burst mode ebable/disable on port B',`
327			`'content' => '"DISABLED","ENABLED" ',`
328			`'redefine_param' => 1,`
329			`'type' => 'Fixed',`
330			`'global_param' => 'Localparam',`
331			`'deafult' => '"ENABLED"'`
332			`},`
333			`'BYTE_WR_EN' => {`
334			`'content' => '"YES","NO"',`
335			`'info' => 'Parameter',`
336			`'type' => 'Combo-box',`
337			`'redefine_param' => 1,`
338			`'global_param' => 'Localparam',`
339			`'deafult' => '"YES"'`
340			`},`
341			`'PORT_A_BURST_MODE' => {`
342			`'deafult' => '"ENABLED"',`
343			`'global_param' => 'Localparam',`
344			`'redefine_param' => 1,`
345			`'type' => 'Combo-box',`
346			`'content' => '"DISABLED","ENABLED"',`
347			`'info' => ' wisbone bus burst mode enable/disable on port A'`
348			`},`
349			`'FPGA_VENDOR' => {`
350			`'redefine_param' => 1,`
351			`'type' => 'Combo-box',`
352			`'content' => '"ALTERA","GENERIC"',`
353			`'info' => 'Parameter',`
354			`'deafult' => '"GENERIC"',`
355			`'global_param' => 'Localparam'`
356			`}`
357			`},`
358	25	alirezamon	`'ports_order' => [`
359			`'clk',`
360			`'reset',`
361			`'sa_dat_i',`
362			`'sa_sel_i',`
363			`'sa_addr_i',`
364			`'sa_tag_i',`
365			`'sa_cti_i',`
366			`'sa_bte_i',`
367			`'sa_stb_i',`
368			`'sa_cyc_i',`
369			`'sa_we_i',`
370			`'sa_dat_o',`
371			`'sa_ack_o',`
372			`'sa_err_o',`
373			`'sa_rty_o',`
374			`'sb_dat_i',`
375			`'sb_sel_i',`
376			`'sb_addr_i',`
377			`'sb_tag_i',`
378			`'sb_cti_i',`
379			`'sb_bte_i',`
380			`'sb_stb_i',`
381			`'sb_cyc_i',`
382			`'sb_we_i',`
383			`'sb_dat_o',`
384			`'sb_ack_o',`
385			`'sb_err_o',`
386			`'sb_rty_o'`
387			`],`
388	34	alirezamon	`'version' => 6,`
389			`'gui_status' => {`
390			`'timeout' => 0,`
391			`'status' => 'ideal'`
392			`},`
393			`'parameters_order' => [`
394			`'Dw',`
395			`'Aw',`
396			`'BYTE_WR_EN',`
397			`'FPGA_VENDOR',`
398			`'TAGw',`
399			`'SELw',`
400			`'CTIw',`
401			`'BTEw',`
402			`'WB_Aw',`
403			`'RAM_INDEX',`
404			`'PORT_A_BURST_MODE',`
405			`'PORT_B_BURST_MODE',`
406			`'INITIAL_EN',`
407			`'MEM_CONTENT_FILE_NAME',`
408			`'INIT_FILE_PATH'`
409			`],`
410	25	alirezamon	`'unused' => undef,`
411	34	alirezamon	`'ip_name' => 'dual_port_ram',`
412			`'modules' => {`
413			`'wb_dual_port_ram' => {}`
414			`},`
415			`'file_name' => '/home/alireza/Mywork/mpsoc/src_peripheral/ram/wb_dual_port_ram.v'`
416	25	alirezamon	`}, 'ip_gen' );`

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[/] [an-fpga-implementation-of-low-latency-noc-based-mpsoc/] [trunk/] [mpsoc/] [perl_gui/] [lib/] [ip/] [RAM/] [dual_port_ram.IP] - Blame information for rev 34