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25 |
alirezamon |
#######################################################################
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## File: single_port_ram.IP
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##
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## Copyright (C) 2014-2016 Alireza Monemi
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##
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38 |
alirezamon |
## This file is part of ProNoC 1.8.0
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25 |
alirezamon |
##
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## WARNING: THIS IS AN AUTO-GENERATED FILE. CHANGES TO IT
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## MAY CAUSE UNEXPECTED BEHAIVOR.
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################################################################################
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38 |
alirezamon |
$ipgen = bless( {
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'description_pdf' => '/mpsoc/src_peripheral/ram/RAM.pdf',
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'unused' => undef,
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'gui_status' => {
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'timeout' => 0,
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'status' => 'ideal'
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},
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'modules' => {
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'wb_single_port_ram' => {}
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},
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'parameters' => {
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'Aw' => {
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'global_param' => 'Parameter',
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'info' => 'Memory address width',
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'type' => 'Spin-button',
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'redefine_param' => 1,
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'default' => '12',
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'content' => '4,31,1'
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25 |
alirezamon |
},
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38 |
alirezamon |
'INITIAL_EN' => {
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'content' => '"YES","NO"',
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'redefine_param' => 1,
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'default' => '"NO"',
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'info' => 'If selected as "ENABLED", the memory content will be initialized at compilation time using MEM_CONTENT_FILE_NAME.',
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'type' => 'Combo-box',
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'global_param' => 'Localparam'
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},
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'WB_Aw' => {
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'global_param' => 'Don\'t include',
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'info' => undef,
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'type' => 'Fixed',
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'redefine_param' => 1,
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'default' => 'Aw+2',
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'content' => ''
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34 |
alirezamon |
},
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38 |
alirezamon |
'BYTE_WR_EN' => {
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'info' => 'Byte enable',
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'type' => 'Combo-box',
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'global_param' => 'Localparam',
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'redefine_param' => 1,
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'content' => '"YES","NO"',
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'default' => '"YES"'
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},
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'TAGw' => {
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'global_param' => 'Localparam',
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'info' => 'Parameter',
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'type' => 'Fixed',
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'content' => '',
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'default' => '3',
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'redefine_param' => 1
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},
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'FPGA_VENDOR' => {
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'content' => '"ALTERA","GENERIC"',
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'redefine_param' => 1,
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'default' => '"GENERIC"',
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'info' => '',
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'type' => 'Combo-box',
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'global_param' => 'Localparam'
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},
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'MEM_CONTENT_FILE_NAME' => {
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'default' => '"ram0"',
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'content' => '',
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'redefine_param' => 1,
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'type' => 'Entry',
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'info' => 'MEM_FILE_NAME:
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34 |
alirezamon |
The memory file name (without file type extension ) that is used for writting the memory content either at run time or at initialization time.
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File Path:
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For bus-based SoC the file path is {ProNoC_work}/SOC/{soc_name}/sw/RAM/{file_type}/{MEM_FILE_NAME}.
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For NoC-based MPSoC the file path is {ProNoC_work}/MPSOC/{mpsoc_name}/sw/tile{tile_num}/RAM/{file_type}/{MEM_FILE_NAME}
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file_type:
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bin: raw binary format . It will be used by JTAG_WB to change the memory content at runtime.
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memh: hexadecimal-string format . It will be used for initialing the Generic RAM using $readmemh command.
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mif: memory initialization file format. This file can be used to initialize Altera FPGA memory. Also if the JTAG_CONECT is selected as ALTERA_IEMC it can be used for changing memory content at run time . ',
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38 |
alirezamon |
'global_param' => 'Localparam'
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},
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'Dw' => {
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'content' => '8,1024,1',
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'redefine_param' => 1,
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'default' => '32',
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'global_param' => 'Parameter',
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'info' => 'Memory data width in Bits.',
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'type' => 'Spin-button'
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},
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'JTAG_INDEX' => {
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'content' => '',
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'default' => 'CORE_ID',
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'redefine_param' => 1,
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'info' => ' A unique index number which will be used for accessing to the memory content using JTAG cable.The default value is the processing tile id (CORE_ID) . You can also inter a unique number for each individula memory.
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34 |
alirezamon |
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In case you have \'n\' memory in each processing core you can define their index as "n*CORE_ID+1 , n*CORE_ID+2 ...n*CORE_ID+n-1).
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You also can disabled JTAG access here and connect one jtag to wb interface (jtag_wb) to the wishbone bus. Using single jtag index number, a jtag_wb module can read/wr any IP that is connected to wishbone bus slave port (including all memory units).
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38 |
alirezamon |
',
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'type' => 'Entry',
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'global_param' => 'Localparam'
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},
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'CTIw' => {
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'content' => '',
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'redefine_param' => 1,
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'default' => '3',
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'global_param' => 'Localparam',
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'type' => 'Fixed',
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'info' => 'Parameter'
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},
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'SELw' => {
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'content' => '',
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'redefine_param' => 1,
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'default' => 'Dw/8',
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'info' => 'Parameter',
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'type' => 'Fixed',
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'global_param' => 'Localparam'
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},
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| 127 |
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'BURST_MODE' => {
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'default' => '"ENABLED"',
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'content' => '"DISABLED","ENABLED"',
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'redefine_param' => 1,
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'info' => 'Enable the Wishbone bus Incrementing burst mode data transfer. Support Linear burst and 4,8,16-beat wrap burst types. ',
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'type' => 'Combo-box',
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'global_param' => 'Localparam'
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},
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| 135 |
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'BTEw' => {
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'redefine_param' => 1,
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'default' => '2',
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'content' => '',
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'type' => 'Fixed',
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'info' => 'Parameter',
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'global_param' => 'Localparam'
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},
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'INIT_FILE_PATH' => {
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'type' => 'Fixed',
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'info' => undef,
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'global_param' => 'Localparam',
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| 147 |
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'content' => '',
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'default' => 'SW_LOC',
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'redefine_param' => 1
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},
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'JTAG_CONNECT' => {
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'type' => 'Combo-box',
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'info' => 'JTAG_CONNECT:
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if it is not disabled then the actual memory is implemented as a dual port RAM with the second port is connected either to In-System Memory Content Editor or Jtag_to_wb. This allows that the memory content can be read/written using JTAG. ',
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'global_param' => 'Localparam',
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'default' => '"DISABLED"',
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'redefine_param' => 1,
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'content' => '"DISABLED", "JTAG_WB" , "ALTERA_IMCE"'
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}
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| 160 |
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},
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'version' => 22,
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'ports' => {
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'reset' => {
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'type' => 'input',
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'range' => '',
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| 166 |
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'intfc_port' => 'reset_i',
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| 167 |
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'intfc_name' => 'plug:reset[0]'
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| 168 |
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},
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| 169 |
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'sa_bte_i' => {
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| 170 |
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'intfc_name' => 'plug:wb_slave[0]',
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| 171 |
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'intfc_port' => 'bte_i',
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| 172 |
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'type' => 'input',
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| 173 |
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'range' => 'BTEw-1 : 0'
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| 174 |
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},
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| 175 |
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'sa_ack_o' => {
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| 176 |
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'intfc_name' => 'plug:wb_slave[0]',
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| 177 |
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'intfc_port' => 'ack_o',
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| 178 |
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'range' => '',
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| 179 |
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'type' => 'output'
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| 180 |
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},
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| 181 |
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'sa_sel_i' => {
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| 182 |
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'intfc_port' => 'sel_i',
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| 183 |
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'intfc_name' => 'plug:wb_slave[0]',
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| 184 |
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'range' => 'SELw-1 : 0',
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| 185 |
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'type' => 'input'
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| 186 |
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},
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| 187 |
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'sa_err_o' => {
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| 188 |
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'type' => 'output',
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| 189 |
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'range' => '',
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| 190 |
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'intfc_name' => 'plug:wb_slave[0]',
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| 191 |
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'intfc_port' => 'err_o'
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| 192 |
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},
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| 193 |
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'sa_tag_i' => {
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| 194 |
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'intfc_name' => 'plug:wb_slave[0]',
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| 195 |
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'intfc_port' => 'tag_i',
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| 196 |
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'type' => 'input',
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| 197 |
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'range' => 'TAGw-1 : 0'
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| 198 |
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},
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| 199 |
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'sa_dat_i' => {
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| 200 |
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'type' => 'input',
|
| 201 |
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'range' => 'Dw-1 : 0',
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| 202 |
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'intfc_port' => 'dat_i',
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| 203 |
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'intfc_name' => 'plug:wb_slave[0]'
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| 204 |
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},
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| 205 |
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'sa_cyc_i' => {
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| 206 |
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'intfc_name' => 'plug:wb_slave[0]',
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| 207 |
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'intfc_port' => 'cyc_i',
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| 208 |
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'type' => 'input',
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| 209 |
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'range' => ''
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| 210 |
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},
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| 211 |
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'sa_rty_o' => {
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| 212 |
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'intfc_name' => 'plug:wb_slave[0]',
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| 213 |
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'intfc_port' => 'rty_o',
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| 214 |
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'range' => '',
|
| 215 |
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'type' => 'output'
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| 216 |
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},
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| 217 |
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'sa_cti_i' => {
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| 218 |
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'range' => 'CTIw-1 : 0',
|
| 219 |
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'type' => 'input',
|
| 220 |
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'intfc_name' => 'plug:wb_slave[0]',
|
| 221 |
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'intfc_port' => 'cti_i'
|
| 222 |
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},
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| 223 |
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'sa_we_i' => {
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| 224 |
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'type' => 'input',
|
| 225 |
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'range' => '',
|
| 226 |
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'intfc_port' => 'we_i',
|
| 227 |
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'intfc_name' => 'plug:wb_slave[0]'
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| 228 |
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},
|
| 229 |
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'sa_dat_o' => {
|
| 230 |
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'intfc_port' => 'dat_o',
|
| 231 |
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'intfc_name' => 'plug:wb_slave[0]',
|
| 232 |
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'type' => 'output',
|
| 233 |
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'range' => 'Dw-1 : 0'
|
| 234 |
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},
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| 235 |
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'clk' => {
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| 236 |
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'type' => 'input',
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| 237 |
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'range' => '',
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| 238 |
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'intfc_name' => 'plug:clk[0]',
|
| 239 |
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'intfc_port' => 'clk_i'
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| 240 |
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},
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| 241 |
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'sa_stb_i' => {
|
| 242 |
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'intfc_name' => 'plug:wb_slave[0]',
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| 243 |
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'intfc_port' => 'stb_i',
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| 244 |
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'range' => '',
|
| 245 |
|
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'type' => 'input'
|
| 246 |
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},
|
| 247 |
|
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'sa_addr_i' => {
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| 248 |
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'intfc_port' => 'adr_i',
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| 249 |
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'intfc_name' => 'plug:wb_slave[0]',
|
| 250 |
|
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'range' => 'Aw-1 : 0',
|
| 251 |
|
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'type' => 'input'
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| 252 |
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}
|
| 253 |
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},
|
| 254 |
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'parameters_order' => [
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| 255 |
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'Dw',
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| 256 |
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'Aw',
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| 257 |
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'BYTE_WR_EN',
|
| 258 |
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'FPGA_VENDOR',
|
| 259 |
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'JTAG_CONNECT',
|
| 260 |
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'JTAG_INDEX',
|
| 261 |
|
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'TAGw',
|
| 262 |
|
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'SELw',
|
| 263 |
|
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'CTIw',
|
| 264 |
|
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'BTEw',
|
| 265 |
|
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'WB_Aw',
|
| 266 |
|
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'BURST_MODE',
|
| 267 |
|
|
'MEM_CONTENT_FILE_NAME',
|
| 268 |
|
|
'INITIAL_EN',
|
| 269 |
|
|
'INIT_FILE_PATH'
|
| 270 |
|
|
],
|
| 271 |
|
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'plugs' => {
|
| 272 |
|
|
'reset' => {
|
| 273 |
|
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'0' => {
|
| 274 |
|
|
'name' => 'reset'
|
| 275 |
|
|
},
|
| 276 |
|
|
'type' => 'num',
|
| 277 |
|
|
'value' => 1,
|
| 278 |
|
|
'reset' => {}
|
| 279 |
|
|
},
|
| 280 |
|
|
'wb_slave' => {
|
| 281 |
|
|
'type' => 'num',
|
| 282 |
|
|
'0' => {
|
| 283 |
|
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'name' => 'wb',
|
| 284 |
|
|
'addr' => '0x0000_0000 0x3fff_ffff RAM',
|
| 285 |
|
|
'width' => 'WB_Aw'
|
| 286 |
|
|
},
|
| 287 |
|
|
'wb_slave' => {},
|
| 288 |
|
|
'value' => 1
|
| 289 |
|
|
},
|
| 290 |
|
|
'clk' => {
|
| 291 |
|
|
'value' => 1,
|
| 292 |
|
|
'clk' => {},
|
| 293 |
|
|
'type' => 'num',
|
| 294 |
|
|
'0' => {
|
| 295 |
|
|
'name' => 'clk'
|
| 296 |
|
|
}
|
| 297 |
|
|
}
|
| 298 |
|
|
},
|
| 299 |
|
|
'hdl_files' => [
|
| 300 |
|
|
'/mpsoc/src_peripheral/ram/wb_single_port_ram.v',
|
| 301 |
|
|
'/mpsoc/src_peripheral/ram/generic_ram.v',
|
| 302 |
|
|
'/mpsoc/src_peripheral/ram/byte_enabled_generic_ram.sv',
|
| 303 |
|
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'/mpsoc/src_peripheral/ram/wb_bram_ctrl.v'
|
| 304 |
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],
|
| 305 |
|
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'ip_name' => 'single_port_ram',
|
| 306 |
|
|
'ports_order' => [
|
| 307 |
|
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'clk',
|
| 308 |
|
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'reset',
|
| 309 |
|
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'sa_dat_i',
|
| 310 |
|
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'sa_sel_i',
|
| 311 |
|
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'sa_addr_i',
|
| 312 |
|
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'sa_tag_i',
|
| 313 |
|
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'sa_cti_i',
|
| 314 |
|
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'sa_bte_i',
|
| 315 |
|
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'sa_stb_i',
|
| 316 |
|
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'sa_cyc_i',
|
| 317 |
|
|
'sa_we_i',
|
| 318 |
|
|
'sa_dat_o',
|
| 319 |
|
|
'sa_ack_o',
|
| 320 |
|
|
'sa_err_o',
|
| 321 |
|
|
'sa_rty_o'
|
| 322 |
|
|
],
|
| 323 |
|
|
'module_name' => 'wb_single_port_ram',
|
| 324 |
|
|
'description' => 'Single port ram with wishbone bus interface.',
|
| 325 |
|
|
'file_name' => '/home/alireza/Mywork/mpsoc/src_peripheral/ram/wb_single_port_ram.v',
|
| 326 |
|
|
'category' => 'RAM'
|
| 327 |
|
|
}, 'ip_gen' );
|
