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[/] [an-fpga-implementation-of-low-latency-noc-based-mpsoc/] [trunk/] [mpsoc/] [perl_gui/] [lib/] [ip/] [RAM/] [single_port_ram.IP] - Blame information for rev 48

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#######################################################################
##      File: single_port_ram.IP
##
##      Copyright (C) 2014-2019  Alireza Monemi
##
##      This file is part of ProNoC 1.9.1
##
##      WARNING: THIS IS AN AUTO-GENERATED FILE. CHANGES TO IT
##      MAY CAUSE UNEXPECTED BEHAVIOR.
################################################################################
 
$ipgen = bless( {
                  'sockets' => {
                                 'jtag_to_wb' => {
                                                   'value' => 1,
                                                   '0' => {
                                                            'name' => 'jtag_to_wb'
                                                          },
                                                   'connection_num' => 'single connection',
                                                   'type' => 'num'
                                                 }
                               },
                  'parameters_order' => [
                                          'Dw',
                                          'Aw',
                                                                                  'WB_Aw',
                                          'BYTE_WR_EN',
                                          'FPGA_VENDOR',
                                          'JTAG_CONNECT',
                                          'JTAG_INDEX',
                                          'CORE_NUM',
                                          'TAGw',
                                          'SELw',
                                          'CTIw',
                                          'BTEw',
                                          'WB_Byte_Aw',
                                          'BURST_MODE',
                                          'MEM_CONTENT_FILE_NAME',
                                          'INITIAL_EN',
                                          'INIT_FILE_PATH',
                                          'JDw',
                                          'JAw',
                                          'JSTATUSw',
                                          'JINDEXw',
                                          'J2WBw',
                                          'WB2Jw',
                                          'JTAG_CHAIN'
 
                                        ],
                  'description_pdf' => '/mpsoc/rtl/src_peripheral/ram/RAM.pdf',
                  'version' => 39,
                  'parameters' => {
                                    'JTAG_INDEX' => {
                                                      'default' => 'CORE_ID',
                                                      'info' => '   A unique index number which will be used for accessing to the memory content using JTAG cable.The default value is the processing tile id (CORE_ID) . You can also inter a unique number for each individula memory.
 
   In case you have \'n\' memory in each processing core you can define their index as "n*CORE_ID+1 , n*CORE_ID+2 ...n*CORE_ID+n-1).
 
   You also can disabled JTAG access here and connect one jtag to wb interface (jtag_wb) to the wishbone bus. Using single jtag index number, a jtag_wb module can read/wr any IP that is connected to wishbone bus slave port (including all memory units).
 
',
                                                      'type' => 'Entry',
                                                      'global_param' => 'Parameter',
                                                      'content' => '',
                                                      'redefine_param' => 1
                                                    },
                                    'JAw' => {
                                               'content' => '',
                                               'global_param' => 'Parameter',
                                               'redefine_param' => 1,
                                               'default' => '32',
                                               'type' => 'Fixed',
                                               'info' => 'Parameter'
                                             },
                                    'INIT_FILE_PATH' => {
                                                          'info' => undef,
                                                          'type' => 'Fixed',
                                                          'default' => 'SW_LOC',
                                                          'redefine_param' => 1,
                                                          'content' => '',
                                                          'global_param' => 'Localparam'
                                                        },
                                    'FPGA_VENDOR' => {
                                                       'global_param' => 'Localparam',
                                                       'content' => '"ALTERA","XILINX","GENERIC"',
                                                       'redefine_param' => 1,
                                                       'default' => '"GENERIC"',
                                                       'info' => '',
                                                       'type' => 'Combo-box'
                                                     },
                                    'Aw' => {
                                              'default' => '12',
                                              'type' => 'Spin-button',
                                              'info' => 'Memory address width',
                                              'content' => '4,31,1',
                                              'global_param' => 'Localparam',
                                              'redefine_param' => 1
                                            },
                                    'CTIw' => {
                                                'redefine_param' => 1,
                                                'global_param' => 'Localparam',
                                                'content' => '',
                                                'info' => 'Parameter',
                                                'type' => 'Fixed',
                                                'default' => '3'
                                              },
                                    'JINDEXw' => {
                                                   'redefine_param' => 1,
                                                   'content' => '',
                                                   'global_param' => 'Parameter',
                                                   'type' => 'Fixed',
                                                   'info' => 'Parameter',
                                                   'default' => '8'
                                                 },
                                    'INITIAL_EN' => {
                                                      'default' => '"NO"',
                                                      'info' => 'If selected as "ENABLED", the memory content will be initialized at compilation time using MEM_CONTENT_FILE_NAME.',
                                                      'type' => 'Combo-box',
                                                      'global_param' => 'Localparam',
                                                      'content' => '"YES","NO"',
                                                      'redefine_param' => 1
                                                    },
                                    'J2WBw' => {
                                                 'info' => undef,
                                                 'type' => 'Fixed',
                                                 'default' => '(JTAG_CONNECT== "XILINX_JTAG_WB") ? 1+1+JDw+JAw : 1',
                                                 'redefine_param' => 1,
                                                 'content' => '',
                                                 'global_param' => 'Parameter'
                                               },
                                    'WB2Jw' => {
                                                 'redefine_param' => 1,
                                                 'content' => '',
                                                 'global_param' => 'Parameter',
                                                 'type' => 'Fixed',
                                                 'info' => undef,
                                                 'default' => '(JTAG_CONNECT== "XILINX_JTAG_WB") ? 1+JSTATUSw+JINDEXw+1+JDw  : 1'
                                               },
                                    'JDw' => {
                                               'type' => 'Fixed',
                                               'info' => 'Parameter',
                                               'default' => 'Dw',
                                               'redefine_param' => 1,
                                               'global_param' => 'Parameter',
                                               'content' => ''
                                             },
                                    'BTEw' => {
                                                'default' => '2',
                                                'info' => 'Parameter',
                                                'type' => 'Fixed',
                                                'global_param' => 'Localparam',
                                                'content' => '',
                                                'redefine_param' => 1
                                              },
                                    'BURST_MODE' => {
                                                      'info' => 'Enable the Wishbone bus Incrementing burst mode data transfer. Support Linear burst and 4,8,16-beat wrap burst types. ',
                                                      'type' => 'Combo-box',
                                                      'default' => '"ENABLED"',
                                                      'redefine_param' => 1,
                                                      'content' => '"DISABLED","ENABLED"',
                                                      'global_param' => 'Localparam'
                                                    },
                                    'WB_Aw' => {
                                                 'info' => 'Wishbon bus reserved address with range. The reserved address will be 2 pow(WB_Aw) in words. This value should be larger or eqal than memory address width (Aw). ',
                                                 'type' => 'Spin-button',
                                                 'default' => '20',
                                                 'redefine_param' => 1,
                                                 'global_param' => 'Localparam',
                                                 'content' => '4,31,1'
                                               },
                                    'Dw' => {
                                              'type' => 'Spin-button',
                                              'info' => 'Memory data width in Bits.',
                                              'default' => '32',
                                              'redefine_param' => 1,
                                              'content' => '8,1024,1',
                                              'global_param' => 'Parameter'
                                            },
                                    'JTAG_CHAIN' => {
                                                      'info' => 'Only used for Virtex 4/5 devices. May be 1, 2, 3, or 4. It is the  BSCANE2 JTAG tap number. The default Jtag tap numbers are:
    4: JTAG runtime memory programmers.
    3: UART
    1,2: reserved',
                                                      'type' => 'Combo-box',
                                                      'default' => '4',
                                                      'redefine_param' => 0,
                                                      'content' => '1,2,3,4',
                                                      'global_param' => 'Parameter'
                                                    },
                                    'BYTE_WR_EN' => {
                                                      'redefine_param' => 1,
                                                      'global_param' => 'Localparam',
                                                      'content' => '"YES","NO"',
                                                      'info' => 'Byte enable',
                                                      'type' => 'Combo-box',
                                                      'default' => '"YES"'
                                                    },
                                    'SELw' => {
                                                'redefine_param' => 1,
                                                'content' => '',
                                                'global_param' => 'Localparam',
                                                'type' => 'Fixed',
                                                'info' => 'Parameter',
                                                'default' => 'Dw/8'
                                              },
                                    'WB_Byte_Aw' => {
                                                      'global_param' => 'Don\'t include',
                                                      'content' => '',
                                                      'redefine_param' => 1,
                                                      'default' => 'WB_Aw+2',
                                                      'info' => undef,
                                                      'type' => 'Fixed'
                                                    },
                                    'CORE_NUM' => {
                                                    'global_param' => 'Localparam',
                                                    'content' => '',
                                                    'redefine_param' => 1,
                                                    'default' => 'CORE_ID',
                                                    'info' => 'Parameter',
                                                    'type' => 'Fixed'
                                                  },
                                    'TAGw' => {
                                                'type' => 'Fixed',
                                                'info' => 'Parameter',
                                                'default' => '3',
                                                'redefine_param' => 1,
                                                'global_param' => 'Localparam',
                                                'content' => ''
                                              },
                                    'JSTATUSw' => {
                                                    'global_param' => 'Parameter',
                                                    'content' => '',
                                                    'redefine_param' => 1,
                                                    'default' => '8',
                                                    'type' => 'Fixed',
                                                    'info' => 'Parameter'
                                                  },
                                    'MEM_CONTENT_FILE_NAME' => {
                                                                 'redefine_param' => 1,
                                                                 'content' => '',
                                                                 'global_param' => 'Localparam',
                                                                 'type' => 'Entry',
                                                                 'info' => 'MEM_FILE_NAME:
The memory file name (without file type extension ) that is used for writting the memory content either at run time or at initialization time.
 
File Path:
For bus-based SoC the file path is {ProNoC_work}/SOC/{soc_name}/sw/RAM/{file_type}/{MEM_FILE_NAME}.
For NoC-based MPSoC the file path is {ProNoC_work}/MPSOC/{mpsoc_name}/sw/tile{tile_num}/RAM/{file_type}/{MEM_FILE_NAME}
 
file_type:
bin: raw binary format . It will be used by ALTERA_JTAG_WB to change the memory content at runtime.
memh: hexadecimal-string format . It will be used for initialing the Generic RAM using $readmemh command.
mif: memory initialization file format. This file can be used to initialize Altera FPGA memory. Also if the JTAG_CONECT is selected as ALTERA_IEMC it can be used for changing memory content at run time . ',
                                                                 'default' => '"ram0"'
                                                               },
                                    'JTAG_CONNECT' => {
                                                        'default' => '"DISABLED"',
                                                        'type' => 'Combo-box',
                                                        'info' => 'JTAG_CONNECT:
if it is not disabled then the actual memory is implemented as a dual port RAM with the second port is connected either to In-System Memory Content Editor or Jtag_to_wb. This allows that the memory content can be read/written using JTAG.   ',
                                                        'global_param' => 'Parameter',
                                                        'content' => '"DISABLED", "ALTERA_JTAG_WB" , "ALTERA_IMCE","XILINX_JTAG_WB"',
                                                        'redefine_param' => 1
                                                      }
                                  },
                  'module_name' => 'wb_single_port_ram',
                  'file_name' => 'mpsoc/rtl/src_peripheral/ram/wb_single_port_ram.v',
                  'plugs' => {
                               'reset' => {
                                            '0' => {
                                                     'name' => 'reset'
                                                   },
                                            'value' => 1,
                                            'reset' => {},
                                            'type' => 'num'
                                          },
                               'wb_slave' => {
                                               'type' => 'num',
                                               'wb_slave' => {},
                                               '0' => {
                                                        'addr' => '0x0000_0000  0x3fff_ffff             RAM',
                                                        'name' => 'wb',
                                                        'width' => 'WB_Byte_Aw'
                                                      },
                                               'value' => 1
                                             },
                               'clk' => {
                                          '0' => {
                                                   'name' => 'clk'
                                                 },
                                          'value' => 1,
                                          'type' => 'num',
                                          'clk' => {}
                                        }
                             },
                  'category' => 'RAM',
                  'ports' => {
                               'sa_rty_o' => {
                                               'range' => '',
                                               'type' => 'output',
                                               'intfc_port' => 'rty_o',
                                               'intfc_name' => 'plug:wb_slave[0]'
                                             },
                               'sa_dat_o' => {
                                               'intfc_name' => 'plug:wb_slave[0]',
                                               'type' => 'output',
                                               'intfc_port' => 'dat_o',
                                               'range' => 'Dw-1       :   0'
                                             },
                               'sa_dat_i' => {
                                               'range' => 'Dw-1       :   0',
                                               'type' => 'input',
                                               'intfc_port' => 'dat_i',
                                               'intfc_name' => 'plug:wb_slave[0]'
                                             },
                               'clk' => {
                                          'intfc_name' => 'plug:clk[0]',
                                          'intfc_port' => 'clk_i',
                                          'type' => 'input',
                                          'range' => ''
                                        },
                               'jtag_to_wb' => {
                                                 'intfc_name' => 'socket:jtag_to_wb[0]',
                                                 'range' => 'J2WBw-1 : 0',
                                                 'type' => 'input',
                                                 'intfc_port' => 'jwb_i'
                                               },
                               'sa_ack_o' => {
                                               'type' => 'output',
                                               'intfc_port' => 'ack_o',
                                               'range' => '',
                                               'intfc_name' => 'plug:wb_slave[0]'
                                             },
                               'reset' => {
                                            'range' => '',
                                            'intfc_port' => 'reset_i',
                                            'type' => 'input',
                                            'intfc_name' => 'plug:reset[0]'
                                          },
                               'sa_err_o' => {
                                               'range' => '',
                                               'intfc_port' => 'err_o',
                                               'type' => 'output',
                                               'intfc_name' => 'plug:wb_slave[0]'
                                             },
                               'sa_stb_i' => {
                                               'range' => '',
                                               'intfc_port' => 'stb_i',
                                               'type' => 'input',
                                               'intfc_name' => 'plug:wb_slave[0]'
                                             },
                               'sa_tag_i' => {
                                               'range' => 'TAGw-1     :   0',
                                               'type' => 'input',
                                               'intfc_port' => 'tag_i',
                                               'intfc_name' => 'plug:wb_slave[0]'
                                             },
                               'sa_cyc_i' => {
                                               'range' => '',
                                               'intfc_port' => 'cyc_i',
                                               'type' => 'input',
                                               'intfc_name' => 'plug:wb_slave[0]'
                                             },
                               'sa_addr_i' => {
                                                'intfc_name' => 'plug:wb_slave[0]',
                                                'range' => 'Aw-1       :   0',
                                                'intfc_port' => 'adr_i',
                                                'type' => 'input'
                                              },
                               'sa_cti_i' => {
                                               'intfc_name' => 'plug:wb_slave[0]',
                                               'range' => 'CTIw-1     :   0',
                                               'type' => 'input',
                                               'intfc_port' => 'cti_i'
                                             },
                               'sa_sel_i' => {
                                               'range' => 'SELw-1     :   0',
                                               'type' => 'input',
                                               'intfc_port' => 'sel_i',
                                               'intfc_name' => 'plug:wb_slave[0]'
                                             },
                               'sa_we_i' => {
                                              'type' => 'input',
                                              'intfc_port' => 'we_i',
                                              'range' => '',
                                              'intfc_name' => 'plug:wb_slave[0]'
                                            },
                               'sa_bte_i' => {
                                               'intfc_name' => 'plug:wb_slave[0]',
                                               'type' => 'input',
                                               'intfc_port' => 'bte_i',
                                               'range' => 'BTEw-1     :   0'
                                             },
                               'wb_to_jtag' => {
                                                 'type' => 'output',
                                                 'intfc_port' => 'jwb_o',
                                                 'range' => 'WB2Jw-1 : 0',
                                                 'intfc_name' => 'socket:jtag_to_wb[0]'
                                               }
                             },
                  'modules' => {
                                 'wb_single_port_ram' => {}
                               },
                  'ports_order' => [
                                     'clk',
                                     'reset',
                                     'jtag_to_wb',
                                     'wb_to_jtag',
                                     'sa_dat_i',
                                     'sa_sel_i',
                                     'sa_addr_i',
                                     'sa_tag_i',
                                     'sa_cti_i',
                                     'sa_bte_i',
                                     'sa_stb_i',
                                     'sa_cyc_i',
                                     'sa_we_i',
                                     'sa_dat_o',
                                     'sa_ack_o',
                                     'sa_err_o',
                                     'sa_rty_o'
                                   ],
                  'hdl_files' => [
                                   '/mpsoc/rtl/src_peripheral/ram/wb_single_port_ram.v',
                                   '/mpsoc/rtl/src_peripheral/ram/generic_ram.v',
                                   '/mpsoc/rtl/src_peripheral/ram/byte_enabled_generic_ram.sv',
                                   '/mpsoc/rtl/src_peripheral/ram/wb_bram_ctrl.v'
                                 ],
                  'description' => 'Single port ram with wishbone bus interface.',
                  'unused' => undef,
                  'ip_name' => 'single_port_ram',
                  'gui_status' => {
                                    'status' => 'ideal',
                                    'timeout' => 0
                                  }
                }, 'ip_gen' );

Line No.	Rev	Author	Line
1	25	alirezamon	`#######################################################################`
2			`## File: single_port_ram.IP`
3			`##`
4	48	alirezamon	`## Copyright (C) 2014-2019 Alireza Monemi`
5	25	alirezamon	`##`
6	48	alirezamon	`## This file is part of ProNoC 1.9.1`
7	25	alirezamon	`##`
8			`## WARNING: THIS IS AN AUTO-GENERATED FILE. CHANGES TO IT`
9	48	alirezamon	`## MAY CAUSE UNEXPECTED BEHAVIOR.`
10	25	alirezamon	`################################################################################`
11
12	38	alirezamon	`$ipgen = bless( {`
13	48	alirezamon	`'sockets' => {`
14			`'jtag_to_wb' => {`
15			`'value' => 1,`
16			`'0' => {`
17			`'name' => 'jtag_to_wb'`
18			`},`
19			`'connection_num' => 'single connection',`
20			`'type' => 'num'`
21			`}`
22	38	alirezamon	`},`
23	48	alirezamon	`'parameters_order' => [`
24			`'Dw',`
25			`'Aw',`
26			`'WB_Aw',`
27			`'BYTE_WR_EN',`
28			`'FPGA_VENDOR',`
29			`'JTAG_CONNECT',`
30			`'JTAG_INDEX',`
31			`'CORE_NUM',`
32			`'TAGw',`
33			`'SELw',`
34			`'CTIw',`
35			`'BTEw',`
36			`'WB_Byte_Aw',`
37			`'BURST_MODE',`
38			`'MEM_CONTENT_FILE_NAME',`
39			`'INITIAL_EN',`
40			`'INIT_FILE_PATH',`
41			`'JDw',`
42			`'JAw',`
43			`'JSTATUSw',`
44			`'JINDEXw',`
45			`'J2WBw',`
46			`'WB2Jw',`
47			`'JTAG_CHAIN'`
48
49			`],`
50			`'description_pdf' => '/mpsoc/rtl/src_peripheral/ram/RAM.pdf',`
51			`'version' => 39,`
52	38	alirezamon	`'parameters' => {`
53	48	alirezamon	`'JTAG_INDEX' => {`
54			`'default' => 'CORE_ID',`
55			`'info' => ' A unique index number which will be used for accessing to the memory content using JTAG cable.The default value is the processing tile id (CORE_ID) . You can also inter a unique number for each individula memory.`
56
57			`In case you have \'n\' memory in each processing core you can define their index as "nCORE_ID+1 , nCORE_ID+2 ...n*CORE_ID+n-1).`
58
59			`You also can disabled JTAG access here and connect one jtag to wb interface (jtag_wb) to the wishbone bus. Using single jtag index number, a jtag_wb module can read/wr any IP that is connected to wishbone bus slave port (including all memory units).`
60
61			`',`
62			`'type' => 'Entry',`
63			`'global_param' => 'Parameter',`
64			`'content' => '',`
65			`'redefine_param' => 1`
66			`},`
67			`'JAw' => {`
68			`'content' => '',`
69			`'global_param' => 'Parameter',`
70			`'redefine_param' => 1,`
71			`'default' => '32',`
72			`'type' => 'Fixed',`
73			`'info' => 'Parameter'`
74			`},`
75			`'INIT_FILE_PATH' => {`
76			`'info' => undef,`
77			`'type' => 'Fixed',`
78			`'default' => 'SW_LOC',`
79			`'redefine_param' => 1,`
80			`'content' => '',`
81			`'global_param' => 'Localparam'`
82			`},`
83			`'FPGA_VENDOR' => {`
84			`'global_param' => 'Localparam',`
85			`'content' => '"ALTERA","XILINX","GENERIC"',`
86			`'redefine_param' => 1,`
87			`'default' => '"GENERIC"',`
88			`'info' => '',`
89			`'type' => 'Combo-box'`
90			`},`
91	38	alirezamon	`'Aw' => {`
92	48	alirezamon	`'default' => '12',`
93			`'type' => 'Spin-button',`
94	38	alirezamon	`'info' => 'Memory address width',`
95	48	alirezamon	`'content' => '4,31,1',`
96			`'global_param' => 'Localparam',`
97			`'redefine_param' => 1`
98	25	alirezamon	`},`
99	48	alirezamon	`'CTIw' => {`
100			`'redefine_param' => 1,`
101			`'global_param' => 'Localparam',`
102			`'content' => '',`
103			`'info' => 'Parameter',`
104			`'type' => 'Fixed',`
105			`'default' => '3'`
106			`},`
107			`'JINDEXw' => {`
108			`'redefine_param' => 1,`
109			`'content' => '',`
110			`'global_param' => 'Parameter',`
111			`'type' => 'Fixed',`
112			`'info' => 'Parameter',`
113			`'default' => '8'`
114			`},`
115	38	alirezamon	`'INITIAL_EN' => {`
116			`'default' => '"NO"',`
117			`'info' => 'If selected as "ENABLED", the memory content will be initialized at compilation time using MEM_CONTENT_FILE_NAME.',`
118			`'type' => 'Combo-box',`
119	48	alirezamon	`'global_param' => 'Localparam',`
120			`'content' => '"YES","NO"',`
121			`'redefine_param' => 1`
122	38	alirezamon	`},`
123	48	alirezamon	`'J2WBw' => {`
124	38	alirezamon	`'info' => undef,`
125			`'type' => 'Fixed',`
126	48	alirezamon	`'default' => '(JTAG_CONNECT== "XILINX_JTAG_WB") ? 1+1+JDw+JAw : 1',`
127	38	alirezamon	`'redefine_param' => 1,`
128	48	alirezamon	`'content' => '',`
129			`'global_param' => 'Parameter'`
130	34	alirezamon	`},`
131	48	alirezamon	`'WB2Jw' => {`
132			`'redefine_param' => 1,`
133			`'content' => '',`
134			`'global_param' => 'Parameter',`
135			`'type' => 'Fixed',`
136			`'info' => undef,`
137			`'default' => '(JTAG_CONNECT== "XILINX_JTAG_WB") ? 1+JSTATUSw+JINDEXw+1+JDw : 1'`
138			`},`
139			`'JDw' => {`
140			`'type' => 'Fixed',`
141			`'info' => 'Parameter',`
142			`'default' => 'Dw',`
143			`'redefine_param' => 1,`
144			`'global_param' => 'Parameter',`
145			`'content' => ''`
146			`},`
147			`'BTEw' => {`
148			`'default' => '2',`
149			`'info' => 'Parameter',`
150			`'type' => 'Fixed',`
151			`'global_param' => 'Localparam',`
152			`'content' => '',`
153			`'redefine_param' => 1`
154			`},`
155			`'BURST_MODE' => {`
156			`'info' => 'Enable the Wishbone bus Incrementing burst mode data transfer. Support Linear burst and 4,8,16-beat wrap burst types. ',`
157			`'type' => 'Combo-box',`
158			`'default' => '"ENABLED"',`
159			`'redefine_param' => 1,`
160			`'content' => '"DISABLED","ENABLED"',`
161			`'global_param' => 'Localparam'`
162			`},`
163			`'WB_Aw' => {`
164			`'info' => 'Wishbon bus reserved address with range. The reserved address will be 2 pow(WB_Aw) in words. This value should be larger or eqal than memory address width (Aw). ',`
165			`'type' => 'Spin-button',`
166			`'default' => '20',`
167			`'redefine_param' => 1,`
168			`'global_param' => 'Localparam',`
169			`'content' => '4,31,1'`
170			`},`
171			`'Dw' => {`
172			`'type' => 'Spin-button',`
173			`'info' => 'Memory data width in Bits.',`
174			`'default' => '32',`
175			`'redefine_param' => 1,`
176			`'content' => '8,1024,1',`
177			`'global_param' => 'Parameter'`
178			`},`
179			`'JTAG_CHAIN' => {`
180			`'info' => 'Only used for Virtex 4/5 devices. May be 1, 2, 3, or 4. It is the BSCANE2 JTAG tap number. The default Jtag tap numbers are:`
181			`4: JTAG runtime memory programmers.`
182			`3: UART`
183			`1,2: reserved',`
184			`'type' => 'Combo-box',`
185			`'default' => '4',`
186			`'redefine_param' => 0,`
187			`'content' => '1,2,3,4',`
188			`'global_param' => 'Parameter'`
189			`},`
190	38	alirezamon	`'BYTE_WR_EN' => {`
191	48	alirezamon	`'redefine_param' => 1,`
192			`'global_param' => 'Localparam',`
193			`'content' => '"YES","NO"',`
194	38	alirezamon	`'info' => 'Byte enable',`
195			`'type' => 'Combo-box',`
196			`'default' => '"YES"'`
197			`},`
198	48	alirezamon	`'SELw' => {`
199			`'redefine_param' => 1,`
200			`'content' => '',`
201	38	alirezamon	`'global_param' => 'Localparam',`
202	48	alirezamon	`'type' => 'Fixed',`
203	38	alirezamon	`'info' => 'Parameter',`
204	48	alirezamon	`'default' => 'Dw/8'`
205			`},`
206			`'WB_Byte_Aw' => {`
207			`'global_param' => 'Don\'t include',`
208			`'content' => '',`
209			`'redefine_param' => 1,`
210			`'default' => 'WB_Aw+2',`
211			`'info' => undef,`
212			`'type' => 'Fixed'`
213			`},`
214			`'CORE_NUM' => {`
215			`'global_param' => 'Localparam',`
216			`'content' => '',`
217			`'redefine_param' => 1,`
218			`'default' => 'CORE_ID',`
219			`'info' => 'Parameter',`
220			`'type' => 'Fixed'`
221			`},`
222			`'TAGw' => {`
223	38	alirezamon	`'type' => 'Fixed',`
224	48	alirezamon	`'info' => 'Parameter',`
225	38	alirezamon	`'default' => '3',`
226	48	alirezamon	`'redefine_param' => 1,`
227			`'global_param' => 'Localparam',`
228			`'content' => ''`
229	38	alirezamon	`},`
230	48	alirezamon	`'JSTATUSw' => {`
231			`'global_param' => 'Parameter',`
232			`'content' => '',`
233			`'redefine_param' => 1,`
234			`'default' => '8',`
235			`'type' => 'Fixed',`
236			`'info' => 'Parameter'`
237			`},`
238	38	alirezamon	`'MEM_CONTENT_FILE_NAME' => {`
239	48	alirezamon	`'redefine_param' => 1,`
240	38	alirezamon	`'content' => '',`
241	48	alirezamon	`'global_param' => 'Localparam',`
242	38	alirezamon	`'type' => 'Entry',`
243			`'info' => 'MEM_FILE_NAME:`
244	34	alirezamon	`The memory file name (without file type extension ) that is used for writting the memory content either at run time or at initialization time.`
245
246			`File Path:`
247			`For bus-based SoC the file path is {ProNoC_work}/SOC/{soc_name}/sw/RAM/{file_type}/{MEM_FILE_NAME}.`
248			`For NoC-based MPSoC the file path is {ProNoC_work}/MPSOC/{mpsoc_name}/sw/tile{tile_num}/RAM/{file_type}/{MEM_FILE_NAME}`
249
250			`file_type:`
251	48	alirezamon	`bin: raw binary format . It will be used by ALTERA_JTAG_WB to change the memory content at runtime.`
252	34	alirezamon	`memh: hexadecimal-string format . It will be used for initialing the Generic RAM using $readmemh command.`
253			`mif: memory initialization file format. This file can be used to initialize Altera FPGA memory. Also if the JTAG_CONECT is selected as ALTERA_IEMC it can be used for changing memory content at run time . ',`
254	48	alirezamon	`'default' => '"ram0"'`
255	38	alirezamon	`},`
256			`'JTAG_CONNECT' => {`
257	48	alirezamon	`'default' => '"DISABLED"',`
258	38	alirezamon	`'type' => 'Combo-box',`
259			`'info' => 'JTAG_CONNECT:`
260			`if it is not disabled then the actual memory is implemented as a dual port RAM with the second port is connected either to In-System Memory Content Editor or Jtag_to_wb. This allows that the memory content can be read/written using JTAG. ',`
261	48	alirezamon	`'global_param' => 'Parameter',`
262			`'content' => '"DISABLED", "ALTERA_JTAG_WB" , "ALTERA_IMCE","XILINX_JTAG_WB"',`
263			`'redefine_param' => 1`
264	38	alirezamon	`}`
265			`},`
266	48	alirezamon	`'module_name' => 'wb_single_port_ram',`
267			`'file_name' => 'mpsoc/rtl/src_peripheral/ram/wb_single_port_ram.v',`
268			`'plugs' => {`
269	38	alirezamon	`'reset' => {`
270	48	alirezamon	`'0' => {`
271			`'name' => 'reset'`
272			`},`
273			`'value' => 1,`
274			`'reset' => {},`
275			`'type' => 'num'`
276	38	alirezamon	`},`
277	48	alirezamon	`'wb_slave' => {`
278			`'type' => 'num',`
279			`'wb_slave' => {},`
280			`'0' => {`
281			`'addr' => '0x0000_0000 0x3fff_ffff RAM',`
282			`'name' => 'wb',`
283			`'width' => 'WB_Byte_Aw'`
284			`},`
285			`'value' => 1`
286			`},`
287			`'clk' => {`
288			`'0' => {`
289			`'name' => 'clk'`
290			`},`
291			`'value' => 1,`
292			`'type' => 'num',`
293			`'clk' => {}`
294			`}`
295			`},`
296			`'category' => 'RAM',`
297			`'ports' => {`
298			`'sa_rty_o' => {`
299			`'range' => '',`
300			`'type' => 'output',`
301			`'intfc_port' => 'rty_o',`
302			`'intfc_name' => 'plug:wb_slave[0]'`
303			`},`
304			`'sa_dat_o' => {`
305	38	alirezamon	`'intfc_name' => 'plug:wb_slave[0]',`
306	48	alirezamon	`'type' => 'output',`
307			`'intfc_port' => 'dat_o',`
308			`'range' => 'Dw-1 : 0'`
309			`},`
310			`'sa_dat_i' => {`
311			`'range' => 'Dw-1 : 0',`
312	38	alirezamon	`'type' => 'input',`
313	48	alirezamon	`'intfc_port' => 'dat_i',`
314			`'intfc_name' => 'plug:wb_slave[0]'`
315	38	alirezamon	`},`
316	48	alirezamon	`'clk' => {`
317			`'intfc_name' => 'plug:clk[0]',`
318			`'intfc_port' => 'clk_i',`
319			`'type' => 'input',`
320			`'range' => ''`
321			`},`
322			`'jtag_to_wb' => {`
323			`'intfc_name' => 'socket:jtag_to_wb[0]',`
324			`'range' => 'J2WBw-1 : 0',`
325			`'type' => 'input',`
326			`'intfc_port' => 'jwb_i'`
327			`},`
328	38	alirezamon	`'sa_ack_o' => {`
329	48	alirezamon	`'type' => 'output',`
330	38	alirezamon	`'intfc_port' => 'ack_o',`
331			`'range' => '',`
332	48	alirezamon	`'intfc_name' => 'plug:wb_slave[0]'`
333	38	alirezamon	`},`
334	48	alirezamon	`'reset' => {`
335			`'range' => '',`
336			`'intfc_port' => 'reset_i',`
337			`'type' => 'input',`
338			`'intfc_name' => 'plug:reset[0]'`
339			`},`
340	38	alirezamon	`'sa_err_o' => {`
341	48	alirezamon	`'range' => '',`
342			`'intfc_port' => 'err_o',`
343	38	alirezamon	`'type' => 'output',`
344	48	alirezamon	`'intfc_name' => 'plug:wb_slave[0]'`
345			`},`
346			`'sa_stb_i' => {`
347	38	alirezamon	`'range' => '',`
348	48	alirezamon	`'intfc_port' => 'stb_i',`
349			`'type' => 'input',`
350			`'intfc_name' => 'plug:wb_slave[0]'`
351	38	alirezamon	`},`
352			`'sa_tag_i' => {`
353	48	alirezamon	`'range' => 'TAGw-1 : 0',`
354			`'type' => 'input',`
355	38	alirezamon	`'intfc_port' => 'tag_i',`
356			`'intfc_name' => 'plug:wb_slave[0]'`
357			`},`
358			`'sa_cyc_i' => {`
359	48	alirezamon	`'range' => '',`
360	38	alirezamon	`'intfc_port' => 'cyc_i',`
361			`'type' => 'input',`
362	48	alirezamon	`'intfc_name' => 'plug:wb_slave[0]'`
363	38	alirezamon	`},`
364	48	alirezamon	`'sa_addr_i' => {`
365			`'intfc_name' => 'plug:wb_slave[0]',`
366			`'range' => 'Aw-1 : 0',`
367			`'intfc_port' => 'adr_i',`
368			`'type' => 'input'`
369			`},`
370			`'sa_cti_i' => {`
371	38	alirezamon	`'intfc_name' => 'plug:wb_slave[0]',`
372			`'range' => 'CTIw-1 : 0',`
373			`'type' => 'input',`
374			`'intfc_port' => 'cti_i'`
375			`},`
376	48	alirezamon	`'sa_sel_i' => {`
377			`'range' => 'SELw-1 : 0',`
378			`'type' => 'input',`
379			`'intfc_port' => 'sel_i',`
380			`'intfc_name' => 'plug:wb_slave[0]'`
381			`},`
382	38	alirezamon	`'sa_we_i' => {`
383			`'type' => 'input',`
384	48	alirezamon	`'intfc_port' => 'we_i',`
385	38	alirezamon	`'range' => '',`
386			`'intfc_name' => 'plug:wb_slave[0]'`
387			`},`
388	48	alirezamon	`'sa_bte_i' => {`
389	38	alirezamon	`'intfc_name' => 'plug:wb_slave[0]',`
390	48	alirezamon	`'type' => 'input',`
391			`'intfc_port' => 'bte_i',`
392			`'range' => 'BTEw-1 : 0'`
393	38	alirezamon	`},`
394	48	alirezamon	`'wb_to_jtag' => {`
395			`'type' => 'output',`
396			`'intfc_port' => 'jwb_o',`
397			`'range' => 'WB2Jw-1 : 0',`
398			`'intfc_name' => 'socket:jtag_to_wb[0]'`
399			`}`
400	38	alirezamon	`},`
401	48	alirezamon	`'modules' => {`
402			`'wb_single_port_ram' => {}`
403			`},`
404	38	alirezamon	`'ports_order' => [`
405			`'clk',`
406			`'reset',`
407	48	alirezamon	`'jtag_to_wb',`
408			`'wb_to_jtag',`
409	38	alirezamon	`'sa_dat_i',`
410			`'sa_sel_i',`
411			`'sa_addr_i',`
412			`'sa_tag_i',`
413			`'sa_cti_i',`
414			`'sa_bte_i',`
415			`'sa_stb_i',`
416			`'sa_cyc_i',`
417			`'sa_we_i',`
418			`'sa_dat_o',`
419			`'sa_ack_o',`
420			`'sa_err_o',`
421			`'sa_rty_o'`
422			`],`
423	48	alirezamon	`'hdl_files' => [`
424			`'/mpsoc/rtl/src_peripheral/ram/wb_single_port_ram.v',`
425			`'/mpsoc/rtl/src_peripheral/ram/generic_ram.v',`
426			`'/mpsoc/rtl/src_peripheral/ram/byte_enabled_generic_ram.sv',`
427			`'/mpsoc/rtl/src_peripheral/ram/wb_bram_ctrl.v'`
428			`],`
429	38	alirezamon	`'description' => 'Single port ram with wishbone bus interface.',`
430	48	alirezamon	`'unused' => undef,`
431			`'ip_name' => 'single_port_ram',`
432			`'gui_status' => {`
433			`'status' => 'ideal',`
434			`'timeout' => 0`
435			`}`
436	38	alirezamon	`}, 'ip_gen' );`

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[/] [an-fpga-implementation-of-low-latency-noc-based-mpsoc/] [trunk/] [mpsoc/] [perl_gui/] [lib/] [ip/] [RAM/] [single_port_ram.IP] - Blame information for rev 48