OpenCores
URL https://opencores.org/ocsvn/an-fpga-implementation-of-low-latency-noc-based-mpsoc/an-fpga-implementation-of-low-latency-noc-based-mpsoc/trunk

Subversion Repositories an-fpga-implementation-of-low-latency-noc-based-mpsoc

[/] [an-fpga-implementation-of-low-latency-noc-based-mpsoc/] [trunk/] [mpsoc/] [perl_gui/] [lib/] [ip/] [Source/] [clk_source.IP] - Blame information for rev 48

Details | Compare with Previous | View Log

Line No. Rev Author Line
1 25 alirezamon 
#######################################################################
2 
##      File: clk_source.IP
3 
##
4 48 alirezamon 
##      Copyright (C) 2014-2019  Alireza Monemi
5 25 alirezamon 
##
6 48 alirezamon 
##      This file is part of ProNoC 1.9.1
7 25 alirezamon 
##
8 
##      WARNING: THIS IS AN AUTO-GENERATED FILE. CHANGES TO IT
9 
##      MAY CAUSE UNEXPECTED BEHAIVOR.
10 
################################################################################
11 
 
12 48 alirezamon 
$ipgen = bless( {
13 
                  'version' => 1,
14 
                  'unused' => undef,
15 
                  'parameters' => {
16 
                                    'FPGA_VENDOR' => {
17 
                                                       'content' => '"ALTERA","XILINX"',
18 
                                                       'info' => '',
19 
                                                       'default' => '"ALTERA"',
20 
                                                       'type' => 'Combo-box',
21 
                                                       'global_param' => 'Localparam',
22 
                                                       'redefine_param' => 1
23 
                                                     }
24 25 alirezamon 
                                  },
25 48 alirezamon 
                  'category' => 'Source',
26 
                  'ip_name' => 'clk_source',
27 
                  'hdl_files' => [
28 
                                   '/mpsoc/rtl/src_peripheral/clk_source/altera_reset_synchronizer.v',
29 
                                   '/mpsoc/rtl/src_peripheral/clk_source/clk_source.v',
30 
                                   '/mpsoc/rtl/src_peripheral/clk_source/xilinx_reset_synchroniser.v'
31 
                                 ],
32 
                  'file_name' => 'mpsoc/rtl/src_peripheral/clk_source/clk_source.v',
33 
                  'parameters_order' => [
34 
                                          'FPGA_VENDOR'
35 
                                        ],
36 
                  'ports' => {
37 
                               'reset_in' => {
38 
                                               'intfc_port' => 'reset_i',
39 
                                               'range' => '',
40 
                                               'type' => 'input',
41 
                                               'intfc_name' => 'plug:reset[0]'
42 
                                             },
43 
                               'clk_in' => {
44 
                                             'intfc_name' => 'plug:clk[0]',
45 
                                             'type' => 'input',
46 
                                             'range' => '',
47 
                                             'intfc_port' => 'clk_i'
48 
                                           },
49 
                               'reset_out' => {
50 
                                                'range' => '',
51 
                                                'intfc_port' => 'reset_o',
52 
                                                'type' => 'output',
53 
                                                'intfc_name' => 'socket:reset[0]'
54 
                                              },
55 
                               'clk_out' => {
56 
                                              'intfc_port' => 'clk_o',
57 
                                              'range' => '',
58 
                                              'type' => 'output',
59 
                                              'intfc_name' => 'socket:clk[0]'
60 
                                            }
61 
                             },
62 
                  'description' => 'clk source. This module provides the clk and reset (socket) interfaces for all other IPs. It also synchronizes the reset signal.',
63 
                  'gui_status' => {
64 
                                    'timeout' => 0,
65 
                                    'status' => 'ideal'
66 
                                  },
67 
                  'sockets' => {
68 
                                 'clk' => {
69 
                                            'value' => 1,
70 
                                            '0' => {
71 
                                                     'name' => 'clk'
72 
                                                   },
73 
                                            'connection_num' => 'multi connection',
74 
                                            'clk' => {},
75 
                                            'type' => 'num'
76 
                                          },
77 
                                 'reset' => {
78 
                                              'connection_num' => 'multi connection',
79 
                                              'value' => 1,
80 
                                              '0' => {
81 
                                                       'name' => 'reset'
82 
                                                     },
83 
                                              'reset' => {},
84 
                                              'type' => 'num'
85 
                                            }
86 
                               },
87 
                  'modules' => {
88 
                                 'clk_source' => {}
89 
                               },
90 
                  'plugs' => {
91 
                               'reset' => {
92 
                                            'reset' => {},
93 
                                            'type' => 'num',
94 
                                            'value' => 1,
95 
                                            '0' => {
96 
                                                     'name' => 'reset'
97 
                                                   }
98 
                                          },
99 
                               'clk' => {
100 
                                          'type' => 'num',
101 
                                          'value' => 1,
102 
                                          '0' => {
103 
                                                   'name' => 'clk'
104 25 alirezamon 
                                                 },
105 48 alirezamon 
                                          'clk' => {}
106 
                                        }
107 
                             },
108 
                  'module_name' => 'clk_source'
109 
                }, 'ip_gen' );

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.