| 1 |
48 |
alirezamon |
#######################################################################
|
| 2 |
|
|
## File: mor1k_mpsoc.MPSOC
|
| 3 |
|
|
##
|
| 4 |
|
|
## Copyright (C) 2014-2019 Alireza Monemi
|
| 5 |
|
|
##
|
| 6 |
|
|
## This file is part of ProNoC 1.9.1
|
| 7 |
|
|
##
|
| 8 |
|
|
## WARNING: THIS IS AN AUTO-GENERATED FILE. CHANGES TO IT
|
| 9 |
|
|
## MAY CAUSE UNEXPECTED BEHAVIOR.
|
| 10 |
|
|
################################################################################
|
| 11 |
|
|
|
| 12 |
54 |
alirezamon |
$mor1k_mpsoc = bless( {
|
| 13 |
|
|
'RAM3' => {
|
| 14 |
|
|
'end' => 65536,
|
| 15 |
|
|
'start' => 49152
|
| 16 |
|
|
},
|
| 17 |
|
|
'mpsoc_name' => 'mor1k_mpsoc',
|
| 18 |
|
|
'compile_pin_range_lsb' => {
|
| 19 |
|
|
'processors_en' => 0
|
| 20 |
|
|
},
|
| 21 |
|
|
'ROM3' => {
|
| 22 |
|
|
'end' => 49152,
|
| 23 |
|
|
'start' => 0
|
| 24 |
|
|
},
|
| 25 |
|
|
'compile' => {
|
| 26 |
|
|
'cpu_num' => '4',
|
| 27 |
|
|
'modelsim_bin' => 'export LM_LICENSE_FILE=1717@epi03.bsc.es; /home/alireza/intelFPGA_lite/questa/questasim/bin',
|
| 28 |
|
|
'type' => 'QuartusII',
|
| 29 |
|
|
'compilers' => 'QuartusII,Vivado,Verilator,Modelsim',
|
| 30 |
|
|
'board' => 'DE10_Nano_VB2',
|
| 31 |
|
|
'quartus bin' => '/home/alireza/intelFPGA_lite/18.1/quartus/bin'
|
| 32 |
|
|
},
|
| 33 |
|
|
'MEM2' => {
|
| 34 |
|
|
'percent' => '75',
|
| 35 |
|
|
'width' => '14'
|
| 36 |
|
|
},
|
| 37 |
|
|
'socs' => {
|
| 38 |
|
|
'mor1k_tile' => {
|
| 39 |
|
|
'tile_nums' => [
|
| 40 |
|
|
0,
|
| 41 |
|
|
1,
|
| 42 |
|
|
2,
|
| 43 |
|
|
3
|
| 44 |
|
|
],
|
| 45 |
|
|
'top' => bless( {
|
| 46 |
|
|
'interface' => {
|
| 47 |
|
|
'socket:RxD_sim[0]' => {
|
| 48 |
|
|
'ports' => {
|
| 49 |
|
|
'uart_RxD_din_sim' => {
|
| 50 |
|
|
'range' => '7:0 ',
|
| 51 |
|
|
'intfc_port' => 'RxD_din_sim',
|
| 52 |
|
|
'instance_name' => 'ProNoC_jtag_uart0',
|
| 53 |
|
|
'type' => 'input'
|
| 54 |
|
|
},
|
| 55 |
|
|
'uart_RxD_ready_sim' => {
|
| 56 |
|
|
'instance_name' => 'ProNoC_jtag_uart0',
|
| 57 |
|
|
'type' => 'output',
|
| 58 |
|
|
'intfc_port' => 'RxD_ready_sim',
|
| 59 |
|
|
'range' => ''
|
| 60 |
|
|
},
|
| 61 |
|
|
'uart_RxD_wr_sim' => {
|
| 62 |
|
|
'range' => '',
|
| 63 |
|
|
'type' => 'input',
|
| 64 |
|
|
'intfc_port' => 'RxD_wr_sim',
|
| 65 |
|
|
'instance_name' => 'ProNoC_jtag_uart0'
|
| 66 |
|
|
}
|
| 67 |
48 |
alirezamon |
}
|
| 68 |
54 |
alirezamon |
},
|
| 69 |
|
|
'plug:clk[0]' => {
|
| 70 |
|
|
'ports' => {
|
| 71 |
|
|
'source_clk_in' => {
|
| 72 |
|
|
'range' => '',
|
| 73 |
|
|
'type' => 'input',
|
| 74 |
|
|
'instance_name' => 'clk_source0',
|
| 75 |
|
|
'intfc_port' => 'clk_i'
|
| 76 |
|
|
}
|
| 77 |
|
|
}
|
| 78 |
|
|
},
|
| 79 |
|
|
'plug:enable[0]' => {
|
| 80 |
48 |
alirezamon |
'ports' => {
|
| 81 |
54 |
alirezamon |
'cpu_cpu_en' => {
|
| 82 |
|
|
'range' => '',
|
| 83 |
|
|
'instance_name' => 'mor1kx0',
|
| 84 |
|
|
'type' => 'input',
|
| 85 |
|
|
'intfc_port' => 'enable_i'
|
| 86 |
|
|
}
|
| 87 |
48 |
alirezamon |
}
|
| 88 |
|
|
},
|
| 89 |
54 |
alirezamon |
'plug:reset[0]' => {
|
| 90 |
48 |
alirezamon |
'ports' => {
|
| 91 |
54 |
alirezamon |
'source_reset_in' => {
|
| 92 |
|
|
'range' => '',
|
| 93 |
|
|
'instance_name' => 'clk_source0',
|
| 94 |
|
|
'type' => 'input',
|
| 95 |
|
|
'intfc_port' => 'reset_i'
|
| 96 |
|
|
}
|
| 97 |
48 |
alirezamon |
}
|
| 98 |
|
|
},
|
| 99 |
54 |
alirezamon |
'socket:jtag_to_wb[0]' => {
|
| 100 |
48 |
alirezamon |
'ports' => {
|
| 101 |
54 |
alirezamon |
'uart_jtag_to_wb' => {
|
| 102 |
|
|
'range' => 'uart_J2WBw-1 : 0',
|
| 103 |
|
|
'instance_name' => 'ProNoC_jtag_uart0',
|
| 104 |
48 |
alirezamon |
'type' => 'input',
|
| 105 |
|
|
'intfc_port' => 'jwb_i'
|
| 106 |
|
|
},
|
| 107 |
54 |
alirezamon |
'ram_jtag_to_wb' => {
|
| 108 |
|
|
'range' => 'ram_J2WBw-1 : 0',
|
| 109 |
|
|
'intfc_port' => 'jwb_i',
|
| 110 |
|
|
'instance_name' => 'single_port_ram0',
|
| 111 |
|
|
'type' => 'input'
|
| 112 |
|
|
},
|
| 113 |
|
|
'uart_wb_to_jtag' => {
|
| 114 |
|
|
'range' => 'uart_WB2Jw-1 : 0',
|
| 115 |
48 |
alirezamon |
'type' => 'output',
|
| 116 |
|
|
'intfc_port' => 'jwb_o',
|
| 117 |
54 |
alirezamon |
'instance_name' => 'ProNoC_jtag_uart0'
|
| 118 |
|
|
},
|
| 119 |
|
|
'ram_wb_to_jtag' => {
|
| 120 |
|
|
'range' => 'ram_WB2Jw-1 : 0',
|
| 121 |
|
|
'instance_name' => 'single_port_ram0',
|
| 122 |
|
|
'type' => 'output',
|
| 123 |
|
|
'intfc_port' => 'jwb_o'
|
| 124 |
|
|
}
|
| 125 |
48 |
alirezamon |
}
|
| 126 |
|
|
},
|
| 127 |
54 |
alirezamon |
'socket:ni[0]' => {
|
| 128 |
|
|
'ports' => {
|
| 129 |
|
|
'ni_current_e_addr' => {
|
| 130 |
|
|
'range' => 'ni_EAw-1 : 0',
|
| 131 |
|
|
'type' => 'input',
|
| 132 |
|
|
'intfc_port' => 'current_e_addr',
|
| 133 |
|
|
'instance_name' => 'ni_master0'
|
| 134 |
48 |
alirezamon |
},
|
| 135 |
54 |
alirezamon |
'ni_chan_in' => {
|
| 136 |
|
|
'range' => 'smartflit_chanel_t',
|
| 137 |
|
|
'intfc_port' => 'chan_in',
|
| 138 |
|
|
'instance_name' => 'ni_master0',
|
| 139 |
|
|
'type' => 'input'
|
| 140 |
|
|
},
|
| 141 |
|
|
'ni_chan_out' => {
|
| 142 |
|
|
'range' => 'smartflit_chanel_t',
|
| 143 |
|
|
'instance_name' => 'ni_master0',
|
| 144 |
|
|
'type' => 'output',
|
| 145 |
|
|
'intfc_port' => 'chan_out'
|
| 146 |
48 |
alirezamon |
},
|
| 147 |
54 |
alirezamon |
'ni_current_r_addr' => {
|
| 148 |
|
|
'range' => 'ni_RAw-1 : 0',
|
| 149 |
|
|
'intfc_port' => 'current_r_addr',
|
| 150 |
|
|
'type' => 'input',
|
| 151 |
|
|
'instance_name' => 'ni_master0'
|
| 152 |
|
|
}
|
| 153 |
|
|
}
|
| 154 |
|
|
}
|
| 155 |
|
|
},
|
| 156 |
|
|
'parameters' => {
|
| 157 |
|
|
'ram_WB2Jw' => '(ram_JTAG_CONNECT== "XILINX_JTAG_WB") ? 1+ram_JSTATUSw+ram_JINDEXw+1+ram_JDw : 1',
|
| 158 |
|
|
'ram_JINDEXw' => '8',
|
| 159 |
|
|
'uart_J2WBw' => '(uart_JTAG_CONNECT== "XILINX_JTAG_WB") ? 1+1+uart_JDw+uart_JAw : 1',
|
| 160 |
|
|
'ram_JSTATUSw' => '8',
|
| 161 |
|
|
'uart_JDw' => '32',
|
| 162 |
|
|
'uart_JINDEXw' => '8',
|
| 163 |
|
|
'ram_JTAG_CHAIN' => '4',
|
| 164 |
|
|
'ram_JDw' => 'ram_Dw',
|
| 165 |
|
|
'uart_JTAG_INDEX' => '126-CORE_ID',
|
| 166 |
|
|
'ram_JTAG_INDEX' => 'CORE_ID',
|
| 167 |
|
|
'ram_JAw' => '32',
|
| 168 |
|
|
'ram_Dw' => '32',
|
| 169 |
|
|
'uart_JAw' => '32',
|
| 170 |
|
|
'uart_JTAG_CHAIN' => '3',
|
| 171 |
|
|
'ram_J2WBw' => '(ram_JTAG_CONNECT== "XILINX_JTAG_WB") ? 1+1+ram_JDw+ram_JAw : 1',
|
| 172 |
|
|
'uart_JSTATUSw' => '8',
|
| 173 |
|
|
'uart_JTAG_CONNECT' => '"ALTERA_JTAG_WB"',
|
| 174 |
|
|
'ram_JTAG_CONNECT' => '"ALTERA_JTAG_WB"',
|
| 175 |
|
|
'uart_WB2Jw' => '(uart_JTAG_CONNECT== "XILINX_JTAG_WB") ? 1+uart_JSTATUSw+uart_JINDEXw+1+uart_JDw : 1'
|
| 176 |
|
|
},
|
| 177 |
|
|
'instance_ids' => {
|
| 178 |
|
|
'timer0' => {
|
| 179 |
|
|
'module' => 'timer',
|
| 180 |
|
|
'localparam' => {
|
| 181 |
|
|
'timer_CNTw' => {
|
| 182 |
48 |
alirezamon |
'content' => '',
|
| 183 |
54 |
alirezamon |
'info' => undef,
|
| 184 |
|
|
'default' => '32 ',
|
| 185 |
48 |
alirezamon |
'type' => 'Fixed',
|
| 186 |
54 |
alirezamon |
'redefine_param' => 1,
|
| 187 |
|
|
'global_param' => 'Localparam'
|
| 188 |
48 |
alirezamon |
},
|
| 189 |
54 |
alirezamon |
'timer_SELw' => {
|
| 190 |
|
|
'info' => undef,
|
| 191 |
48 |
alirezamon |
'content' => '',
|
| 192 |
|
|
'redefine_param' => 1,
|
| 193 |
54 |
alirezamon |
'global_param' => 'Localparam',
|
| 194 |
|
|
'default' => '4',
|
| 195 |
48 |
alirezamon |
'type' => 'Fixed'
|
| 196 |
|
|
},
|
| 197 |
54 |
alirezamon |
'timer_Aw' => {
|
| 198 |
|
|
'global_param' => 'Localparam',
|
| 199 |
|
|
'redefine_param' => 1,
|
| 200 |
|
|
'type' => 'Fixed',
|
| 201 |
|
|
'default' => '3',
|
| 202 |
|
|
'info' => undef,
|
| 203 |
|
|
'content' => ''
|
| 204 |
|
|
},
|
| 205 |
|
|
'timer_PRESCALER_WIDTH' => {
|
| 206 |
|
|
'global_param' => 'Localparam',
|
| 207 |
|
|
'redefine_param' => 1,
|
| 208 |
|
|
'default' => '8',
|
| 209 |
|
|
'type' => 'Spin-button',
|
| 210 |
|
|
'info' => ' The prescaler timer width. The prescaler takes the basic timer clock frequency and divides it by some value before feeding it to the timer, according to how the prescaler register(s) are configured.
|
| 211 |
|
|
|
| 212 |
|
|
|
| 213 |
|
|
',
|
| 214 |
|
|
'content' => '1,32,1'
|
| 215 |
|
|
},
|
| 216 |
|
|
'timer_Dw' => {
|
| 217 |
|
|
'default' => '32',
|
| 218 |
|
|
'type' => 'Fixed',
|
| 219 |
|
|
'global_param' => 'Localparam',
|
| 220 |
|
|
'redefine_param' => 1,
|
| 221 |
|
|
'content' => '',
|
| 222 |
|
|
'info' => undef
|
| 223 |
|
|
},
|
| 224 |
|
|
'timer_TAGw' => {
|
| 225 |
48 |
alirezamon |
'type' => 'Fixed',
|
| 226 |
54 |
alirezamon |
'default' => '3',
|
| 227 |
48 |
alirezamon |
'global_param' => 'Localparam',
|
| 228 |
54 |
alirezamon |
'redefine_param' => 1,
|
| 229 |
48 |
alirezamon |
'content' => '',
|
| 230 |
54 |
alirezamon |
'info' => undef
|
| 231 |
|
|
}
|
| 232 |
|
|
},
|
| 233 |
|
|
'category' => 'Timer',
|
| 234 |
|
|
'instance' => 'timer',
|
| 235 |
|
|
'module_name' => 'timer'
|
| 236 |
|
|
},
|
| 237 |
|
|
'ProNoC_jtag_uart0' => {
|
| 238 |
|
|
'category' => 'Communication',
|
| 239 |
|
|
'parameters' => {
|
| 240 |
|
|
'uart_JTAG_CONNECT' => {
|
| 241 |
|
|
'info' => 'For Altera FPGAs define it as "ALTERA_JTAG_WB". In this case, the UART uses Virtual JTAG tap IP core from Altera lib to communicate with the Host PC.
|
| 242 |
|
|
|
| 243 |
|
|
For XILINX FPGAs define it as "XILINX_JTAG_WB". In this case, the UART uses BSCANE2 JTAG tap IP core from XILINX lib to communicate with the Host PC.',
|
| 244 |
|
|
'content' => '"XILINX_JTAG_WB","ALTERA_JTAG_WB"',
|
| 245 |
|
|
'redefine_param' => 1,
|
| 246 |
|
|
'global_param' => 'Parameter',
|
| 247 |
|
|
'default' => '"ALTERA_JTAG_WB"',
|
| 248 |
|
|
'type' => 'Combo-box'
|
| 249 |
|
|
},
|
| 250 |
|
|
'uart_JSTATUSw' => {
|
| 251 |
|
|
'global_param' => 'Parameter',
|
| 252 |
48 |
alirezamon |
'redefine_param' => 1,
|
| 253 |
54 |
alirezamon |
'default' => '8',
|
| 254 |
|
|
'type' => 'Fixed',
|
| 255 |
48 |
alirezamon |
'info' => 'Parameter',
|
| 256 |
54 |
alirezamon |
'content' => ''
|
| 257 |
48 |
alirezamon |
},
|
| 258 |
54 |
alirezamon |
'uart_J2WBw' => {
|
| 259 |
|
|
'info' => undef,
|
| 260 |
|
|
'content' => '',
|
| 261 |
48 |
alirezamon |
'redefine_param' => 1,
|
| 262 |
54 |
alirezamon |
'global_param' => 'Parameter',
|
| 263 |
|
|
'default' => '(uart_JTAG_CONNECT== "XILINX_JTAG_WB") ? 1+1+uart_JDw+uart_JAw : 1',
|
| 264 |
|
|
'type' => 'Fixed'
|
| 265 |
48 |
alirezamon |
},
|
| 266 |
54 |
alirezamon |
'uart_JDw' => {
|
| 267 |
|
|
'content' => '',
|
| 268 |
|
|
'info' => 'Parameter',
|
| 269 |
|
|
'type' => 'Fixed',
|
| 270 |
|
|
'default' => '32',
|
| 271 |
|
|
'global_param' => 'Parameter',
|
| 272 |
|
|
'redefine_param' => 1
|
| 273 |
|
|
},
|
| 274 |
|
|
'uart_JINDEXw' => {
|
| 275 |
48 |
alirezamon |
'content' => '',
|
| 276 |
|
|
'info' => 'Parameter',
|
| 277 |
|
|
'default' => '8',
|
| 278 |
54 |
alirezamon |
'type' => 'Fixed',
|
| 279 |
|
|
'redefine_param' => 1,
|
| 280 |
|
|
'global_param' => 'Parameter'
|
| 281 |
48 |
alirezamon |
},
|
| 282 |
54 |
alirezamon |
'uart_JTAG_INDEX' => {
|
| 283 |
|
|
'info' => 'The index number id used for communicating with this IP. all modules connected to the same jtag tab should have a unique JTAG index number. The default value is 126-CORE_ID. The core ID is the tile number in MPSoC. So if each tile has a UART, then each UART index would be different.',
|
| 284 |
|
|
'content' => '',
|
| 285 |
|
|
'global_param' => 'Parameter',
|
| 286 |
|
|
'redefine_param' => 1,
|
| 287 |
|
|
'type' => 'Entry',
|
| 288 |
|
|
'default' => '126-CORE_ID'
|
| 289 |
|
|
},
|
| 290 |
|
|
'uart_JAw' => {
|
| 291 |
|
|
'default' => '32',
|
| 292 |
|
|
'type' => 'Fixed',
|
| 293 |
|
|
'redefine_param' => 1,
|
| 294 |
48 |
alirezamon |
'global_param' => 'Parameter',
|
| 295 |
|
|
'content' => '',
|
| 296 |
54 |
alirezamon |
'info' => 'Parameter'
|
| 297 |
48 |
alirezamon |
},
|
| 298 |
54 |
alirezamon |
'uart_JTAG_CHAIN' => {
|
| 299 |
48 |
alirezamon |
'info' => 'Only used for Virtex 4/5 devices. May be 1, 2, 3, or 4. It is the BSCANE2 JTAG tap number. The default Jtag tap numbers are:
|
| 300 |
|
|
4: JTAG runtime memory programmers.
|
| 301 |
|
|
3: UART
|
| 302 |
|
|
1,2: reserved',
|
| 303 |
|
|
'content' => '1,2,3,4',
|
| 304 |
54 |
alirezamon |
'global_param' => 'Parameter',
|
| 305 |
|
|
'redefine_param' => 0,
|
| 306 |
|
|
'default' => '3',
|
| 307 |
|
|
'type' => 'Combo-box'
|
| 308 |
48 |
alirezamon |
},
|
| 309 |
54 |
alirezamon |
'uart_WB2Jw' => {
|
| 310 |
|
|
'redefine_param' => 1,
|
| 311 |
|
|
'global_param' => 'Parameter',
|
| 312 |
|
|
'type' => 'Fixed',
|
| 313 |
|
|
'default' => '(uart_JTAG_CONNECT== "XILINX_JTAG_WB") ? 1+uart_JSTATUSw+uart_JINDEXw+1+uart_JDw : 1',
|
| 314 |
|
|
'info' => '',
|
| 315 |
|
|
'content' => ''
|
| 316 |
|
|
}
|
| 317 |
48 |
alirezamon |
},
|
| 318 |
54 |
alirezamon |
'module' => 'ProNoC_jtag_uart',
|
| 319 |
|
|
'localparam' => {
|
| 320 |
|
|
'uart_BUFF_Aw' => {
|
| 321 |
|
|
'default' => '4',
|
| 322 |
|
|
'type' => 'Spin-button',
|
| 323 |
|
|
'redefine_param' => 1,
|
| 324 |
|
|
'global_param' => 'Localparam',
|
| 325 |
|
|
'content' => '2,16,1',
|
| 326 |
|
|
'info' => 'UART internal fifo buffer address width shared equally for send and recive FIFOs. Each of send and recive fifo buffers have 2^(BUFF_Aw-1) entry.'
|
| 327 |
|
|
},
|
| 328 |
|
|
'uart_Dw' => {
|
| 329 |
|
|
'global_param' => 'Localparam',
|
| 330 |
|
|
'redefine_param' => 1,
|
| 331 |
|
|
'default' => '32',
|
| 332 |
48 |
alirezamon |
'type' => 'Fixed',
|
| 333 |
54 |
alirezamon |
'info' => 'Parameter',
|
| 334 |
48 |
alirezamon |
'content' => ''
|
| 335 |
|
|
},
|
| 336 |
54 |
alirezamon |
'uart_TAGw' => {
|
| 337 |
|
|
'global_param' => 'Localparam',
|
| 338 |
|
|
'redefine_param' => 1,
|
| 339 |
48 |
alirezamon |
'type' => 'Fixed',
|
| 340 |
54 |
alirezamon |
'default' => '3',
|
| 341 |
48 |
alirezamon |
'info' => 'Parameter',
|
| 342 |
54 |
alirezamon |
'content' => ''
|
| 343 |
|
|
},
|
| 344 |
|
|
'uart_SELw' => {
|
| 345 |
48 |
alirezamon |
'content' => '',
|
| 346 |
54 |
alirezamon |
'info' => 'Parameter',
|
| 347 |
|
|
'type' => 'Fixed',
|
| 348 |
|
|
'default' => '4',
|
| 349 |
48 |
alirezamon |
'redefine_param' => 1,
|
| 350 |
54 |
alirezamon |
'global_param' => 'Localparam'
|
| 351 |
48 |
alirezamon |
},
|
| 352 |
54 |
alirezamon |
'uart_Aw' => {
|
| 353 |
|
|
'info' => 'Parameter',
|
| 354 |
|
|
'content' => '',
|
| 355 |
|
|
'global_param' => 'Localparam',
|
| 356 |
48 |
alirezamon |
'redefine_param' => 1,
|
| 357 |
54 |
alirezamon |
'default' => '1',
|
| 358 |
|
|
'type' => 'Fixed'
|
| 359 |
|
|
}
|
| 360 |
|
|
},
|
| 361 |
|
|
'instance' => 'uart',
|
| 362 |
|
|
'module_name' => 'pronoc_jtag_uart',
|
| 363 |
|
|
'ports' => {
|
| 364 |
|
|
'uart_RxD_wr_sim' => {
|
| 365 |
|
|
'intfc_port' => 'RxD_wr_sim',
|
| 366 |
|
|
'type' => 'input',
|
| 367 |
|
|
'intfc_name' => 'socket:RxD_sim[0]',
|
| 368 |
|
|
'range' => ''
|
| 369 |
|
|
},
|
| 370 |
|
|
'uart_wb_to_jtag' => {
|
| 371 |
|
|
'intfc_port' => 'jwb_o',
|
| 372 |
|
|
'type' => 'output',
|
| 373 |
|
|
'range' => 'uart_WB2Jw-1 : 0',
|
| 374 |
|
|
'intfc_name' => 'socket:jtag_to_wb[0]'
|
| 375 |
|
|
},
|
| 376 |
|
|
'uart_RxD_din_sim' => {
|
| 377 |
|
|
'intfc_name' => 'socket:RxD_sim[0]',
|
| 378 |
|
|
'range' => '7:0 ',
|
| 379 |
|
|
'intfc_port' => 'RxD_din_sim',
|
| 380 |
|
|
'type' => 'input'
|
| 381 |
|
|
},
|
| 382 |
|
|
'uart_jtag_to_wb' => {
|
| 383 |
|
|
'type' => 'input',
|
| 384 |
|
|
'intfc_port' => 'jwb_i',
|
| 385 |
|
|
'intfc_name' => 'socket:jtag_to_wb[0]',
|
| 386 |
|
|
'range' => 'uart_J2WBw-1 : 0'
|
| 387 |
|
|
},
|
| 388 |
|
|
'uart_RxD_ready_sim' => {
|
| 389 |
|
|
'type' => 'output',
|
| 390 |
|
|
'intfc_port' => 'RxD_ready_sim',
|
| 391 |
|
|
'intfc_name' => 'socket:RxD_sim[0]',
|
| 392 |
|
|
'range' => ''
|
| 393 |
|
|
}
|
| 394 |
|
|
}
|
| 395 |
|
|
},
|
| 396 |
|
|
'wishbone_bus0' => {
|
| 397 |
|
|
'localparam' => {
|
| 398 |
|
|
'bus_SELw' => {
|
| 399 |
48 |
alirezamon |
'type' => 'Fixed',
|
| 400 |
54 |
alirezamon |
'default' => 'bus_Dw/8',
|
| 401 |
48 |
alirezamon |
'global_param' => 'Localparam',
|
| 402 |
|
|
'redefine_param' => 1,
|
| 403 |
|
|
'content' => '',
|
| 404 |
54 |
alirezamon |
'info' => undef
|
| 405 |
|
|
},
|
| 406 |
|
|
'bus_CTIw' => {
|
| 407 |
48 |
alirezamon |
'type' => 'Fixed',
|
| 408 |
54 |
alirezamon |
'default' => '3',
|
| 409 |
48 |
alirezamon |
'global_param' => 'Localparam',
|
| 410 |
|
|
'redefine_param' => 1,
|
| 411 |
|
|
'content' => '',
|
| 412 |
54 |
alirezamon |
'info' => undef
|
| 413 |
48 |
alirezamon |
},
|
| 414 |
54 |
alirezamon |
'bus_S' => {
|
| 415 |
|
|
'content' => '1,256,1',
|
| 416 |
|
|
'info' => 'Number of wishbone slave interface',
|
| 417 |
|
|
'default' => '4',
|
| 418 |
|
|
'type' => 'Spin-button',
|
| 419 |
|
|
'redefine_param' => 1,
|
| 420 |
|
|
'global_param' => 'Localparam'
|
| 421 |
|
|
},
|
| 422 |
|
|
'bus_TAGw' => {
|
| 423 |
48 |
alirezamon |
'content' => '',
|
| 424 |
54 |
alirezamon |
'info' => undef,
|
| 425 |
48 |
alirezamon |
'type' => 'Fixed',
|
| 426 |
54 |
alirezamon |
'default' => '3',
|
| 427 |
48 |
alirezamon |
'global_param' => 'Localparam',
|
| 428 |
54 |
alirezamon |
'redefine_param' => 1
|
| 429 |
48 |
alirezamon |
},
|
| 430 |
54 |
alirezamon |
'bus_M' => {
|
| 431 |
|
|
'content' => '1,256,1',
|
| 432 |
|
|
'info' => 'Number of wishbone master interface',
|
| 433 |
|
|
'type' => 'Spin-button',
|
| 434 |
|
|
'default' => ' 4',
|
| 435 |
48 |
alirezamon |
'global_param' => 'Localparam',
|
| 436 |
54 |
alirezamon |
'redefine_param' => 1
|
| 437 |
48 |
alirezamon |
},
|
| 438 |
54 |
alirezamon |
'bus_Dw' => {
|
| 439 |
|
|
'info' => 'The wishbone Bus data width in bits.',
|
| 440 |
|
|
'content' => '8,512,8',
|
| 441 |
48 |
alirezamon |
'global_param' => 'Localparam',
|
| 442 |
|
|
'redefine_param' => 1,
|
| 443 |
54 |
alirezamon |
'type' => 'Spin-button',
|
| 444 |
|
|
'default' => '32'
|
| 445 |
48 |
alirezamon |
},
|
| 446 |
54 |
alirezamon |
'bus_Aw' => {
|
| 447 |
|
|
'info' => 'The wishbone Bus address width',
|
| 448 |
|
|
'content' => '4,128,1',
|
| 449 |
48 |
alirezamon |
'redefine_param' => 1,
|
| 450 |
54 |
alirezamon |
'global_param' => 'Localparam',
|
| 451 |
48 |
alirezamon |
'default' => '32',
|
| 452 |
54 |
alirezamon |
'type' => 'Spin-button'
|
| 453 |
|
|
},
|
| 454 |
|
|
'bus_BTEw' => {
|
| 455 |
|
|
'info' => undef,
|
| 456 |
48 |
alirezamon |
'content' => '',
|
| 457 |
|
|
'redefine_param' => 1,
|
| 458 |
|
|
'global_param' => 'Localparam',
|
| 459 |
54 |
alirezamon |
'default' => '2 ',
|
| 460 |
48 |
alirezamon |
'type' => 'Fixed'
|
| 461 |
54 |
alirezamon |
}
|
| 462 |
48 |
alirezamon |
},
|
| 463 |
54 |
alirezamon |
'module' => 'wishbone_bus',
|
| 464 |
|
|
'category' => 'Bus',
|
| 465 |
|
|
'module_name' => 'wishbone_bus',
|
| 466 |
|
|
'instance' => 'bus'
|
| 467 |
|
|
},
|
| 468 |
|
|
'clk_source0' => {
|
| 469 |
|
|
'category' => 'Source',
|
| 470 |
|
|
'module' => 'clk_source',
|
| 471 |
|
|
'localparam' => {
|
| 472 |
|
|
'source_FPGA_VENDOR' => {
|
| 473 |
|
|
'default' => '"ALTERA"',
|
| 474 |
48 |
alirezamon |
'type' => 'Combo-box',
|
| 475 |
54 |
alirezamon |
'global_param' => 'Localparam',
|
| 476 |
|
|
'redefine_param' => 1,
|
| 477 |
|
|
'content' => '"ALTERA","XILINX"',
|
| 478 |
|
|
'info' => ''
|
| 479 |
|
|
}
|
| 480 |
|
|
},
|
| 481 |
|
|
'ports' => {
|
| 482 |
|
|
'source_clk_in' => {
|
| 483 |
|
|
'intfc_name' => 'plug:clk[0]',
|
| 484 |
|
|
'range' => '',
|
| 485 |
|
|
'type' => 'input',
|
| 486 |
|
|
'intfc_port' => 'clk_i'
|
| 487 |
48 |
alirezamon |
},
|
| 488 |
54 |
alirezamon |
'source_reset_in' => {
|
| 489 |
|
|
'intfc_port' => 'reset_i',
|
| 490 |
|
|
'type' => 'input',
|
| 491 |
|
|
'intfc_name' => 'plug:reset[0]',
|
| 492 |
|
|
'range' => ''
|
| 493 |
|
|
}
|
| 494 |
|
|
},
|
| 495 |
|
|
'instance' => 'source',
|
| 496 |
|
|
'module_name' => 'clk_source'
|
| 497 |
|
|
},
|
| 498 |
|
|
'ni_master0' => {
|
| 499 |
|
|
'ports' => {
|
| 500 |
|
|
'ni_current_r_addr' => {
|
| 501 |
|
|
'type' => 'input',
|
| 502 |
|
|
'intfc_port' => 'current_r_addr',
|
| 503 |
|
|
'intfc_name' => 'socket:ni[0]',
|
| 504 |
|
|
'range' => 'ni_RAw-1 : 0'
|
| 505 |
48 |
alirezamon |
},
|
| 506 |
54 |
alirezamon |
'ni_chan_out' => {
|
| 507 |
48 |
alirezamon |
'type' => 'output',
|
| 508 |
54 |
alirezamon |
'intfc_port' => 'chan_out',
|
| 509 |
|
|
'range' => 'smartflit_chanel_t',
|
| 510 |
48 |
alirezamon |
'intfc_name' => 'socket:ni[0]'
|
| 511 |
|
|
},
|
| 512 |
54 |
alirezamon |
'ni_chan_in' => {
|
| 513 |
|
|
'intfc_port' => 'chan_in',
|
| 514 |
|
|
'type' => 'input',
|
| 515 |
|
|
'intfc_name' => 'socket:ni[0]',
|
| 516 |
|
|
'range' => 'smartflit_chanel_t'
|
| 517 |
48 |
alirezamon |
},
|
| 518 |
54 |
alirezamon |
'ni_current_e_addr' => {
|
| 519 |
|
|
'range' => 'ni_EAw-1 : 0',
|
| 520 |
|
|
'intfc_name' => 'socket:ni[0]',
|
| 521 |
|
|
'intfc_port' => 'current_e_addr',
|
| 522 |
|
|
'type' => 'input'
|
| 523 |
|
|
}
|
| 524 |
|
|
},
|
| 525 |
|
|
'instance' => 'ni',
|
| 526 |
|
|
'module_name' => 'ni_master',
|
| 527 |
|
|
'category' => 'NoC',
|
| 528 |
|
|
'parameters' => {
|
| 529 |
|
|
'ni_RAw' => {
|
| 530 |
|
|
'content' => '',
|
| 531 |
|
|
'info' => undef,
|
| 532 |
|
|
'default' => '16',
|
| 533 |
48 |
alirezamon |
'type' => 'Fixed',
|
| 534 |
54 |
alirezamon |
'redefine_param' => 0,
|
| 535 |
|
|
'global_param' => 'Parameter'
|
| 536 |
48 |
alirezamon |
},
|
| 537 |
54 |
alirezamon |
'ni_EAw' => {
|
| 538 |
48 |
alirezamon |
'global_param' => 'Parameter',
|
| 539 |
54 |
alirezamon |
'redefine_param' => 0,
|
| 540 |
|
|
'default' => '16',
|
| 541 |
48 |
alirezamon |
'type' => 'Fixed',
|
| 542 |
54 |
alirezamon |
'info' => undef,
|
| 543 |
|
|
'content' => ''
|
| 544 |
|
|
}
|
| 545 |
|
|
},
|
| 546 |
|
|
'module' => 'ni_master',
|
| 547 |
|
|
'localparam' => {
|
| 548 |
|
|
'ni_MAX_BURST_SIZE' => {
|
| 549 |
|
|
'info' => 'Maximum burst size in words.
|
| 550 |
48 |
alirezamon |
The NI releases the wishbone bus each time one burst is completed or when the VC\'s internal FIFO becomes full. The bus will be released for one clock cycle. Then in case, there are other active VCs, another active VC will get access to the bus using round robin arbiter. This process will be continued until all of the desired data is transferred. ',
|
| 551 |
54 |
alirezamon |
'content' => '2,4,8,16,32,64,128,256,512,1024,2048',
|
| 552 |
|
|
'global_param' => 'Localparam',
|
| 553 |
|
|
'redefine_param' => 1,
|
| 554 |
|
|
'default' => '16',
|
| 555 |
|
|
'type' => 'Combo-box'
|
| 556 |
|
|
},
|
| 557 |
|
|
'ni_MAX_TRANSACTION_WIDTH' => {
|
| 558 |
|
|
'default' => '13',
|
| 559 |
|
|
'type' => 'Spin-button',
|
| 560 |
|
|
'global_param' => 'Localparam',
|
| 561 |
|
|
'redefine_param' => 1,
|
| 562 |
|
|
'content' => '4,32,1',
|
| 563 |
|
|
'info' => 'maximum packet size width in words.
|
| 564 |
48 |
alirezamon |
The maximum data that can be sent via one packet will be 2 power of MAX_DMA_TRANSACTION_WIDTH in words.'
|
| 565 |
54 |
alirezamon |
},
|
| 566 |
|
|
'ni_M_Aw' => {
|
| 567 |
48 |
alirezamon |
'redefine_param' => 1,
|
| 568 |
|
|
'global_param' => 'Localparam',
|
| 569 |
54 |
alirezamon |
'type' => 'Fixed',
|
| 570 |
|
|
'default' => '32',
|
| 571 |
|
|
'info' => 'Parameter',
|
| 572 |
|
|
'content' => 'Dw'
|
| 573 |
48 |
alirezamon |
},
|
| 574 |
54 |
alirezamon |
'ni_S_Aw' => {
|
| 575 |
|
|
'info' => 'Parameter',
|
| 576 |
|
|
'content' => '',
|
| 577 |
48 |
alirezamon |
'redefine_param' => 1,
|
| 578 |
|
|
'global_param' => 'Localparam',
|
| 579 |
54 |
alirezamon |
'default' => '8',
|
| 580 |
|
|
'type' => 'Fixed'
|
| 581 |
48 |
alirezamon |
},
|
| 582 |
54 |
alirezamon |
'ni_SELw' => {
|
| 583 |
48 |
alirezamon |
'info' => 'Parameter',
|
| 584 |
54 |
alirezamon |
'content' => '',
|
| 585 |
48 |
alirezamon |
'redefine_param' => 1,
|
| 586 |
54 |
alirezamon |
'global_param' => 'Localparam',
|
| 587 |
|
|
'type' => 'Fixed',
|
| 588 |
|
|
'default' => '4'
|
| 589 |
48 |
alirezamon |
},
|
| 590 |
54 |
alirezamon |
'ni_TAGw' => {
|
| 591 |
|
|
'default' => '3',
|
| 592 |
48 |
alirezamon |
'type' => 'Fixed',
|
| 593 |
|
|
'redefine_param' => 1,
|
| 594 |
54 |
alirezamon |
'global_param' => 'Localparam',
|
| 595 |
48 |
alirezamon |
'content' => '',
|
| 596 |
54 |
alirezamon |
'info' => 'Parameter'
|
| 597 |
48 |
alirezamon |
},
|
| 598 |
54 |
alirezamon |
'ni_CRC_EN' => {
|
| 599 |
|
|
'info' => 'The parameter can be selected as "YES" or "NO".
|
| 600 |
|
|
If CRC is enabled, then two CRC32 generator modules will be added to the NI. One CRC generator for calculating CRC of sending packets and another for receiving packets. The CRC32 value of each packet is send via tail flit and at destination NI, is will be compared with received packet generated CRC32. The matching results can be used for error-detection and can be read via NI slave interface. ',
|
| 601 |
|
|
'content' => '"YES","NO"',
|
| 602 |
|
|
'global_param' => 'Localparam',
|
| 603 |
48 |
alirezamon |
'redefine_param' => 1,
|
| 604 |
54 |
alirezamon |
'type' => 'Combo-box',
|
| 605 |
|
|
'default' => '"NO"'
|
| 606 |
48 |
alirezamon |
},
|
| 607 |
54 |
alirezamon |
'ni_Dw' => {
|
| 608 |
|
|
'default' => '32',
|
| 609 |
|
|
'type' => 'Spin-button',
|
| 610 |
|
|
'global_param' => 'Localparam',
|
| 611 |
|
|
'redefine_param' => 1,
|
| 612 |
|
|
'content' => '32,256,8',
|
| 613 |
|
|
'info' => 'wishbone_bus data width in bits.'
|
| 614 |
|
|
},
|
| 615 |
|
|
'ni_HDATA_PRECAPw' => {
|
| 616 |
|
|
'type' => 'Spin-button',
|
| 617 |
|
|
'default' => '0',
|
| 618 |
|
|
'global_param' => 'Localparam',
|
| 619 |
48 |
alirezamon |
'redefine_param' => 1,
|
| 620 |
54 |
alirezamon |
'content' => '0,8,1',
|
| 621 |
|
|
'info' => ' The headr Data pre capture width. It Will be enabled when it is larger than zero. The header data can optionally carry a short width Data. This data can be pre-captured (completely/partially) by the NI before saving the packet in a memory buffer. This can give some hints to the software regarding the incoming packet such as its type, or source port so the software can store the packet in its appropriate buffer.'
|
| 622 |
|
|
}
|
| 623 |
|
|
}
|
| 624 |
|
|
},
|
| 625 |
|
|
'mor1kx0' => {
|
| 626 |
|
|
'category' => 'Processor',
|
| 627 |
|
|
'localparam' => {
|
| 628 |
|
|
'cpu_FEATURE_INSTRUCTIONCACHE' => {
|
| 629 |
|
|
'info' => '',
|
| 630 |
|
|
'content' => '"NONE","ENABLED"',
|
| 631 |
|
|
'redefine_param' => 1,
|
| 632 |
|
|
'global_param' => 'Localparam',
|
| 633 |
|
|
'type' => 'Combo-box',
|
| 634 |
|
|
'default' => '"ENABLED"'
|
| 635 |
|
|
},
|
| 636 |
|
|
'cpu_OPTION_SHIFTER' => {
|
| 637 |
|
|
'info' => 'Specify the shifter implementation',
|
| 638 |
|
|
'content' => '"BARREL","SERIAL"',
|
| 639 |
|
|
'redefine_param' => 1,
|
| 640 |
|
|
'global_param' => 'Localparam',
|
| 641 |
|
|
'type' => 'Combo-box',
|
| 642 |
|
|
'default' => '"BARREL"'
|
| 643 |
|
|
},
|
| 644 |
|
|
'cpu_FEATURE_DMMU' => {
|
| 645 |
|
|
'info' => '',
|
| 646 |
|
|
'content' => '"NONE","ENABLED"',
|
| 647 |
|
|
'redefine_param' => 1,
|
| 648 |
|
|
'global_param' => 'Localparam',
|
| 649 |
|
|
'default' => '"ENABLED"',
|
| 650 |
|
|
'type' => 'Combo-box'
|
| 651 |
|
|
},
|
| 652 |
|
|
'cpu_FEATURE_MULTIPLIER' => {
|
| 653 |
|
|
'type' => 'Combo-box',
|
| 654 |
|
|
'default' => '"THREESTAGE"',
|
| 655 |
|
|
'redefine_param' => 1,
|
| 656 |
|
|
'global_param' => 'Localparam',
|
| 657 |
|
|
'content' => '"THREESTAGE","PIPELINED","SERIAL","NONE"',
|
| 658 |
|
|
'info' => 'Specify the multiplier implementation'
|
| 659 |
|
|
},
|
| 660 |
|
|
'cpu_OPTION_DCACHE_SNOOP' => {
|
| 661 |
|
|
'default' => '"ENABLED"',
|
| 662 |
|
|
'type' => 'Combo-box',
|
| 663 |
|
|
'redefine_param' => 1,
|
| 664 |
|
|
'global_param' => 'Localparam',
|
| 665 |
|
|
'content' => '"NONE","ENABLED"',
|
| 666 |
|
|
'info' => ''
|
| 667 |
|
|
},
|
| 668 |
|
|
'cpu_OPTION_OPERAND_WIDTH' => {
|
| 669 |
|
|
'info' => 'Parameter',
|
| 670 |
|
|
'content' => '',
|
| 671 |
|
|
'redefine_param' => 1,
|
| 672 |
|
|
'global_param' => 'Localparam',
|
| 673 |
|
|
'type' => 'Fixed',
|
| 674 |
|
|
'default' => '32'
|
| 675 |
|
|
},
|
| 676 |
|
|
'cpu_FEATURE_IMMU' => {
|
| 677 |
|
|
'info' => '',
|
| 678 |
|
|
'content' => '"NONE","ENABLED"',
|
| 679 |
|
|
'global_param' => 'Localparam',
|
| 680 |
|
|
'redefine_param' => 1,
|
| 681 |
|
|
'type' => 'Combo-box',
|
| 682 |
|
|
'default' => '"ENABLED"'
|
| 683 |
|
|
},
|
| 684 |
|
|
'cpu_FEATURE_DIVIDER' => {
|
| 685 |
|
|
'default' => '"SERIAL"',
|
| 686 |
48 |
alirezamon |
'type' => 'Combo-box',
|
| 687 |
54 |
alirezamon |
'redefine_param' => 1,
|
| 688 |
|
|
'global_param' => 'Localparam',
|
| 689 |
|
|
'content' => '"SERIAL","NONE"',
|
| 690 |
|
|
'info' => 'Specify the divider implementation'
|
| 691 |
48 |
alirezamon |
},
|
| 692 |
54 |
alirezamon |
'cpu_IRQ_NUM' => {
|
| 693 |
|
|
'info' => undef,
|
| 694 |
|
|
'content' => '',
|
| 695 |
48 |
alirezamon |
'global_param' => 'Localparam',
|
| 696 |
|
|
'redefine_param' => 1,
|
| 697 |
|
|
'type' => 'Fixed',
|
| 698 |
54 |
alirezamon |
'default' => '32'
|
| 699 |
48 |
alirezamon |
},
|
| 700 |
54 |
alirezamon |
'cpu_FEATURE_DATACACHE' => {
|
| 701 |
|
|
'info' => '',
|
| 702 |
|
|
'content' => '"NONE","ENABLED"',
|
| 703 |
|
|
'global_param' => 'Localparam',
|
| 704 |
48 |
alirezamon |
'redefine_param' => 1,
|
| 705 |
54 |
alirezamon |
'default' => '"ENABLED"',
|
| 706 |
|
|
'type' => 'Combo-box'
|
| 707 |
48 |
alirezamon |
}
|
| 708 |
54 |
alirezamon |
},
|
| 709 |
|
|
'module' => 'mor1kx',
|
| 710 |
|
|
'module_name' => 'mor1k',
|
| 711 |
|
|
'ports' => {
|
| 712 |
|
|
'cpu_cpu_en' => {
|
| 713 |
|
|
'intfc_name' => 'plug:enable[0]',
|
| 714 |
|
|
'range' => '',
|
| 715 |
|
|
'type' => 'input',
|
| 716 |
|
|
'intfc_port' => 'enable_i'
|
| 717 |
48 |
alirezamon |
}
|
| 718 |
54 |
alirezamon |
},
|
| 719 |
|
|
'instance' => 'cpu'
|
| 720 |
|
|
},
|
| 721 |
|
|
'single_port_ram0' => {
|
| 722 |
|
|
'instance' => 'ram',
|
| 723 |
|
|
'module_name' => 'wb_single_port_ram',
|
| 724 |
|
|
'ports' => {
|
| 725 |
|
|
'ram_jtag_to_wb' => {
|
| 726 |
|
|
'type' => 'input',
|
| 727 |
|
|
'intfc_port' => 'jwb_i',
|
| 728 |
|
|
'intfc_name' => 'socket:jtag_to_wb[0]',
|
| 729 |
|
|
'range' => 'ram_J2WBw-1 : 0'
|
| 730 |
48 |
alirezamon |
},
|
| 731 |
54 |
alirezamon |
'ram_wb_to_jtag' => {
|
| 732 |
|
|
'type' => 'output',
|
| 733 |
|
|
'intfc_port' => 'jwb_o',
|
| 734 |
|
|
'range' => 'ram_WB2Jw-1 : 0',
|
| 735 |
|
|
'intfc_name' => 'socket:jtag_to_wb[0]'
|
| 736 |
|
|
}
|
| 737 |
|
|
},
|
| 738 |
|
|
'category' => 'RAM',
|
| 739 |
|
|
'module' => 'single_port_ram',
|
| 740 |
|
|
'parameters' => {
|
| 741 |
|
|
'ram_JSTATUSw' => {
|
| 742 |
|
|
'content' => '',
|
| 743 |
|
|
'info' => 'Parameter',
|
| 744 |
|
|
'default' => '8',
|
| 745 |
|
|
'type' => 'Fixed',
|
| 746 |
|
|
'global_param' => 'Parameter',
|
| 747 |
|
|
'redefine_param' => 1
|
| 748 |
|
|
},
|
| 749 |
|
|
'ram_JINDEXw' => {
|
| 750 |
|
|
'default' => '8',
|
| 751 |
|
|
'type' => 'Fixed',
|
| 752 |
48 |
alirezamon |
'redefine_param' => 1,
|
| 753 |
|
|
'global_param' => 'Parameter',
|
| 754 |
54 |
alirezamon |
'content' => '',
|
| 755 |
|
|
'info' => 'Parameter'
|
| 756 |
48 |
alirezamon |
},
|
| 757 |
54 |
alirezamon |
'ram_J2WBw' => {
|
| 758 |
|
|
'redefine_param' => 1,
|
| 759 |
48 |
alirezamon |
'global_param' => 'Parameter',
|
| 760 |
54 |
alirezamon |
'type' => 'Fixed',
|
| 761 |
|
|
'default' => '(ram_JTAG_CONNECT== "XILINX_JTAG_WB") ? 1+1+ram_JDw+ram_JAw : 1',
|
| 762 |
|
|
'info' => undef,
|
| 763 |
48 |
alirezamon |
'content' => ''
|
| 764 |
|
|
},
|
| 765 |
54 |
alirezamon |
'ram_WB2Jw' => {
|
| 766 |
|
|
'default' => '(ram_JTAG_CONNECT== "XILINX_JTAG_WB") ? 1+ram_JSTATUSw+ram_JINDEXw+1+ram_JDw : 1',
|
| 767 |
|
|
'type' => 'Fixed',
|
| 768 |
|
|
'redefine_param' => 1,
|
| 769 |
|
|
'global_param' => 'Parameter',
|
| 770 |
|
|
'content' => '',
|
| 771 |
|
|
'info' => undef
|
| 772 |
|
|
},
|
| 773 |
|
|
'ram_Dw' => {
|
| 774 |
48 |
alirezamon |
'redefine_param' => 1,
|
| 775 |
|
|
'global_param' => 'Parameter',
|
| 776 |
54 |
alirezamon |
'type' => 'Spin-button',
|
| 777 |
|
|
'default' => '32',
|
| 778 |
|
|
'info' => 'Memory data width in Bits.',
|
| 779 |
|
|
'content' => '8,1024,1'
|
| 780 |
48 |
alirezamon |
},
|
| 781 |
54 |
alirezamon |
'ram_JTAG_INDEX' => {
|
| 782 |
|
|
'global_param' => 'Parameter',
|
| 783 |
|
|
'redefine_param' => 1,
|
| 784 |
|
|
'default' => 'CORE_ID',
|
| 785 |
|
|
'type' => 'Entry',
|
| 786 |
|
|
'info' => ' A unique index number which will be used for accessing to the memory content using JTAG cable.The default value is the processing tile id (CORE_ID) . You can also inter a unique number for each individula memory.
|
| 787 |
48 |
alirezamon |
|
| 788 |
|
|
In case you have \'n\' memory in each processing core you can define their index as "n*CORE_ID+1 , n*CORE_ID+2 ...n*CORE_ID+n-1).
|
| 789 |
|
|
|
| 790 |
|
|
You also can disabled JTAG access here and connect one jtag to wb interface (jtag_wb) to the wishbone bus. Using single jtag index number, a jtag_wb module can read/wr any IP that is connected to wishbone bus slave port (including all memory units).
|
| 791 |
|
|
|
| 792 |
|
|
',
|
| 793 |
54 |
alirezamon |
'content' => ''
|
| 794 |
|
|
},
|
| 795 |
|
|
'ram_JAw' => {
|
| 796 |
|
|
'info' => 'Parameter',
|
| 797 |
|
|
'content' => '',
|
| 798 |
48 |
alirezamon |
'global_param' => 'Parameter',
|
| 799 |
|
|
'redefine_param' => 1,
|
| 800 |
54 |
alirezamon |
'default' => '32',
|
| 801 |
|
|
'type' => 'Fixed'
|
| 802 |
48 |
alirezamon |
},
|
| 803 |
54 |
alirezamon |
'ram_JTAG_CONNECT' => {
|
| 804 |
|
|
'type' => 'Combo-box',
|
| 805 |
|
|
'default' => '"ALTERA_JTAG_WB"',
|
| 806 |
|
|
'redefine_param' => 1,
|
| 807 |
|
|
'global_param' => 'Parameter',
|
| 808 |
|
|
'content' => '"DISABLED", "ALTERA_JTAG_WB" , "ALTERA_IMCE","XILINX_JTAG_WB"',
|
| 809 |
|
|
'info' => 'JTAG_CONNECT:
|
| 810 |
|
|
if it is not disabled then the actual memory is implemented as a dual port RAM with the second port is connected either to In-System Memory Content Editor or Jtag_to_wb. This allows that the memory content can be read/written using JTAG. '
|
| 811 |
|
|
},
|
| 812 |
|
|
'ram_JDw' => {
|
| 813 |
|
|
'global_param' => 'Parameter',
|
| 814 |
48 |
alirezamon |
'redefine_param' => 1,
|
| 815 |
54 |
alirezamon |
'default' => 'ram_Dw',
|
| 816 |
|
|
'type' => 'Fixed',
|
| 817 |
|
|
'info' => 'Parameter',
|
| 818 |
|
|
'content' => ''
|
| 819 |
48 |
alirezamon |
},
|
| 820 |
54 |
alirezamon |
'ram_JTAG_CHAIN' => {
|
| 821 |
|
|
'content' => '1,2,3,4',
|
| 822 |
|
|
'info' => 'Only used for Virtex 4/5 devices. May be 1, 2, 3, or 4. It is the BSCANE2 JTAG tap number. The default Jtag tap numbers are:
|
| 823 |
|
|
4: JTAG runtime memory programmers.
|
| 824 |
|
|
3: UART
|
| 825 |
|
|
1,2: reserved',
|
| 826 |
|
|
'default' => '4',
|
| 827 |
|
|
'type' => 'Combo-box',
|
| 828 |
|
|
'global_param' => 'Parameter',
|
| 829 |
|
|
'redefine_param' => 0
|
| 830 |
|
|
}
|
| 831 |
|
|
},
|
| 832 |
|
|
'localparam' => {
|
| 833 |
|
|
'ram_CTIw' => {
|
| 834 |
|
|
'content' => '',
|
| 835 |
|
|
'info' => 'Parameter',
|
| 836 |
|
|
'default' => '3',
|
| 837 |
|
|
'type' => 'Fixed',
|
| 838 |
|
|
'redefine_param' => 1,
|
| 839 |
|
|
'global_param' => 'Localparam'
|
| 840 |
|
|
},
|
| 841 |
|
|
'ram_TAGw' => {
|
| 842 |
|
|
'default' => '3',
|
| 843 |
|
|
'type' => 'Fixed',
|
| 844 |
|
|
'redefine_param' => 1,
|
| 845 |
|
|
'global_param' => 'Localparam',
|
| 846 |
|
|
'content' => '',
|
| 847 |
|
|
'info' => 'Parameter'
|
| 848 |
|
|
},
|
| 849 |
|
|
'ram_SELw' => {
|
| 850 |
|
|
'default' => 'ram_Dw/8',
|
| 851 |
|
|
'type' => 'Fixed',
|
| 852 |
|
|
'redefine_param' => 1,
|
| 853 |
|
|
'global_param' => 'Localparam',
|
| 854 |
|
|
'content' => '',
|
| 855 |
|
|
'info' => 'Parameter'
|
| 856 |
|
|
},
|
| 857 |
|
|
'ram_FPGA_VENDOR' => {
|
| 858 |
|
|
'type' => 'Combo-box',
|
| 859 |
|
|
'default' => '"ALTERA"',
|
| 860 |
|
|
'global_param' => 'Localparam',
|
| 861 |
|
|
'redefine_param' => 1,
|
| 862 |
|
|
'content' => '"ALTERA","XILINX","GENERIC"',
|
| 863 |
|
|
'info' => ''
|
| 864 |
|
|
},
|
| 865 |
|
|
'ram_BYTE_WR_EN' => {
|
| 866 |
|
|
'global_param' => 'Localparam',
|
| 867 |
|
|
'redefine_param' => 1,
|
| 868 |
|
|
'default' => '"YES"',
|
| 869 |
|
|
'type' => 'Combo-box',
|
| 870 |
|
|
'info' => 'Byte enable',
|
| 871 |
|
|
'content' => '"YES","NO"'
|
| 872 |
|
|
},
|
| 873 |
|
|
'ram_CORE_NUM' => {
|
| 874 |
|
|
'default' => 'CORE_ID',
|
| 875 |
|
|
'type' => 'Fixed',
|
| 876 |
|
|
'redefine_param' => 1,
|
| 877 |
|
|
'global_param' => 'Localparam',
|
| 878 |
|
|
'content' => '',
|
| 879 |
|
|
'info' => 'Parameter'
|
| 880 |
|
|
},
|
| 881 |
|
|
'ram_INIT_FILE_PATH' => {
|
| 882 |
|
|
'content' => '',
|
| 883 |
|
|
'info' => undef,
|
| 884 |
|
|
'default' => 'SW_LOC',
|
| 885 |
|
|
'type' => 'Fixed',
|
| 886 |
48 |
alirezamon |
'redefine_param' => 1,
|
| 887 |
54 |
alirezamon |
'global_param' => 'Localparam'
|
| 888 |
48 |
alirezamon |
},
|
| 889 |
54 |
alirezamon |
'ram_INITIAL_EN' => {
|
| 890 |
|
|
'default' => '"YES"',
|
| 891 |
|
|
'type' => 'Combo-box',
|
| 892 |
|
|
'global_param' => 'Localparam',
|
| 893 |
|
|
'redefine_param' => 1,
|
| 894 |
|
|
'content' => '"YES","NO"',
|
| 895 |
|
|
'info' => 'If selected as "ENABLED", the memory content will be initialized at compilation time using MEM_CONTENT_FILE_NAME.'
|
| 896 |
|
|
},
|
| 897 |
|
|
'ram_WB_Aw' => {
|
| 898 |
|
|
'content' => '4,31,1',
|
| 899 |
|
|
'info' => 'Wishbon bus reserved address with range. The reserved address will be 2 pow(WB_Aw) in words. This value should be larger or eqal than memory address width (Aw). ',
|
| 900 |
|
|
'default' => '20',
|
| 901 |
|
|
'type' => 'Spin-button',
|
| 902 |
|
|
'global_param' => 'Localparam',
|
| 903 |
|
|
'redefine_param' => 1
|
| 904 |
|
|
},
|
| 905 |
|
|
'ram_Aw' => {
|
| 906 |
|
|
'content' => '4,31,1',
|
| 907 |
|
|
'info' => 'Memory address width',
|
| 908 |
|
|
'type' => 'Spin-button',
|
| 909 |
|
|
'default' => '14',
|
| 910 |
|
|
'redefine_param' => 1,
|
| 911 |
|
|
'global_param' => 'Localparam'
|
| 912 |
48 |
alirezamon |
},
|
| 913 |
54 |
alirezamon |
'ram_MEM_CONTENT_FILE_NAME' => {
|
| 914 |
|
|
'content' => '',
|
| 915 |
|
|
'info' => 'MEM_FILE_NAME:
|
| 916 |
48 |
alirezamon |
The memory file name (without file type extension ) that is used for writting the memory content either at run time or at initialization time.
|
| 917 |
|
|
|
| 918 |
|
|
File Path:
|
| 919 |
|
|
For bus-based SoC the file path is {ProNoC_work}/SOC/{soc_name}/sw/RAM/{file_type}/{MEM_FILE_NAME}.
|
| 920 |
|
|
For NoC-based MPSoC the file path is {ProNoC_work}/MPSOC/{mpsoc_name}/sw/tile{tile_num}/RAM/{file_type}/{MEM_FILE_NAME}
|
| 921 |
|
|
|
| 922 |
|
|
file_type:
|
| 923 |
|
|
bin: raw binary format . It will be used by ALTERA_JTAG_WB to change the memory content at runtime.
|
| 924 |
|
|
memh: hexadecimal-string format . It will be used for initialing the Generic RAM using $readmemh command.
|
| 925 |
|
|
mif: memory initialization file format. This file can be used to initialize Altera FPGA memory. Also if the JTAG_CONECT is selected as ALTERA_IEMC it can be used for changing memory content at run time . ',
|
| 926 |
54 |
alirezamon |
'type' => 'Entry',
|
| 927 |
|
|
'default' => '"ram0"',
|
| 928 |
|
|
'redefine_param' => 1,
|
| 929 |
|
|
'global_param' => 'Localparam'
|
| 930 |
|
|
},
|
| 931 |
|
|
'ram_BTEw' => {
|
| 932 |
|
|
'default' => '2',
|
| 933 |
|
|
'type' => 'Fixed',
|
| 934 |
48 |
alirezamon |
'global_param' => 'Localparam',
|
| 935 |
54 |
alirezamon |
'redefine_param' => 1,
|
| 936 |
48 |
alirezamon |
'content' => '',
|
| 937 |
54 |
alirezamon |
'info' => 'Parameter'
|
| 938 |
48 |
alirezamon |
},
|
| 939 |
54 |
alirezamon |
'ram_BURST_MODE' => {
|
| 940 |
|
|
'global_param' => 'Localparam',
|
| 941 |
48 |
alirezamon |
'redefine_param' => 1,
|
| 942 |
54 |
alirezamon |
'default' => '"ENABLED"',
|
| 943 |
48 |
alirezamon |
'type' => 'Combo-box',
|
| 944 |
54 |
alirezamon |
'info' => 'Enable the Wishbone bus Incrementing burst mode data transfer. Support Linear burst and 4,8,16-beat wrap burst types. ',
|
| 945 |
|
|
'content' => '"DISABLED","ENABLED"'
|
| 946 |
|
|
}
|
| 947 |
|
|
}
|
| 948 |
|
|
}
|
| 949 |
|
|
},
|
| 950 |
|
|
'tiles' => {
|
| 951 |
|
|
'0' => {
|
| 952 |
|
|
'parameters' => {
|
| 953 |
|
|
'ram_J2WBw' => '(ram_JTAG_CONNECT== "XILINX_JTAG_WB") ? 1+1+ram_JDw+ram_JAw : 1',
|
| 954 |
|
|
'uart_JTAG_CONNECT' => '"XILINX_JTAG_WB"',
|
| 955 |
|
|
'uart_JSTATUSw' => '8',
|
| 956 |
|
|
'uart_WB2Jw' => '(uart_JTAG_CONNECT== "XILINX_JTAG_WB") ? 1+uart_JSTATUSw+uart_JINDEXw+1+uart_JDw : 1',
|
| 957 |
|
|
'ram_JTAG_CONNECT' => '"XILINX_JTAG_WB"',
|
| 958 |
|
|
'ram_JINDEXw' => '8',
|
| 959 |
|
|
'ram_JSTATUSw' => '8',
|
| 960 |
|
|
'uart_J2WBw' => '(uart_JTAG_CONNECT== "XILINX_JTAG_WB") ? 1+1+uart_JDw+uart_JAw : 1',
|
| 961 |
|
|
'uart_JDw' => '32',
|
| 962 |
|
|
'ram_Aw' => '14',
|
| 963 |
|
|
'ram_WB2Jw' => '(ram_JTAG_CONNECT== "XILINX_JTAG_WB") ? 1+ram_JSTATUSw+ram_JINDEXw+1+ram_JDw : 1',
|
| 964 |
|
|
'uart_JTAG_CHAIN' => '3',
|
| 965 |
|
|
'uart_JINDEXw' => '8',
|
| 966 |
|
|
'ram_JTAG_CHAIN' => '4',
|
| 967 |
|
|
'ram_JDw' => 'ram_Dw',
|
| 968 |
|
|
'uart_JTAG_INDEX' => '126-CORE_ID',
|
| 969 |
|
|
'ram_JTAG_INDEX' => 'CORE_ID',
|
| 970 |
|
|
'ram_JAw' => '32',
|
| 971 |
|
|
'uart_JAw' => '32',
|
| 972 |
|
|
'ram_Dw' => '32'
|
| 973 |
|
|
}
|
| 974 |
|
|
},
|
| 975 |
|
|
'1' => {
|
| 976 |
|
|
'parameters' => {
|
| 977 |
|
|
'ram_WB2Jw' => '(ram_JTAG_CONNECT== "XILINX_JTAG_WB") ? 1+ram_JSTATUSw+ram_JINDEXw+1+ram_JDw : 1',
|
| 978 |
|
|
'ram_Aw' => '14',
|
| 979 |
|
|
'uart_J2WBw' => '(uart_JTAG_CONNECT== "XILINX_JTAG_WB") ? 1+1+uart_JDw+uart_JAw : 1',
|
| 980 |
|
|
'ram_JSTATUSw' => '8',
|
| 981 |
|
|
'uart_JDw' => '32',
|
| 982 |
|
|
'ram_JINDEXw' => '8',
|
| 983 |
|
|
'uart_JTAG_INDEX' => '126-CORE_ID',
|
| 984 |
|
|
'ram_JAw' => '32',
|
| 985 |
|
|
'ram_Dw' => '32',
|
| 986 |
|
|
'uart_JAw' => '32',
|
| 987 |
|
|
'ram_JTAG_INDEX' => 'CORE_ID',
|
| 988 |
|
|
'uart_JINDEXw' => '8',
|
| 989 |
|
|
'ram_JTAG_CHAIN' => '4',
|
| 990 |
|
|
'ram_JDw' => 'ram_Dw',
|
| 991 |
|
|
'uart_JTAG_CHAIN' => '3',
|
| 992 |
|
|
'ram_J2WBw' => '(ram_JTAG_CONNECT== "XILINX_JTAG_WB") ? 1+1+ram_JDw+ram_JAw : 1',
|
| 993 |
|
|
'uart_JTAG_CONNECT' => '"XILINX_JTAG_WB"',
|
| 994 |
|
|
'uart_JSTATUSw' => '8',
|
| 995 |
|
|
'ram_JTAG_CONNECT' => '"XILINX_JTAG_WB"',
|
| 996 |
|
|
'uart_WB2Jw' => '(uart_JTAG_CONNECT== "XILINX_JTAG_WB") ? 1+uart_JSTATUSw+uart_JINDEXw+1+uart_JDw : 1'
|
| 997 |
|
|
}
|
| 998 |
|
|
},
|
| 999 |
|
|
'2' => {
|
| 1000 |
|
|
'parameters' => {
|
| 1001 |
|
|
'uart_JINDEXw' => '8',
|
| 1002 |
|
|
'ram_JTAG_CHAIN' => '4',
|
| 1003 |
|
|
'ram_JDw' => 'ram_Dw',
|
| 1004 |
|
|
'uart_JTAG_INDEX' => '126-CORE_ID',
|
| 1005 |
|
|
'ram_JAw' => '32',
|
| 1006 |
|
|
'ram_JTAG_INDEX' => 'CORE_ID',
|
| 1007 |
|
|
'ram_Dw' => '32',
|
| 1008 |
|
|
'uart_JAw' => '32',
|
| 1009 |
|
|
'uart_JTAG_CHAIN' => '3',
|
| 1010 |
|
|
'ram_WB2Jw' => '(ram_JTAG_CONNECT== "XILINX_JTAG_WB") ? 1+ram_JSTATUSw+ram_JINDEXw+1+ram_JDw : 1',
|
| 1011 |
|
|
'ram_JINDEXw' => '8',
|
| 1012 |
|
|
'ram_JSTATUSw' => '8',
|
| 1013 |
|
|
'uart_JDw' => '32',
|
| 1014 |
|
|
'ram_Aw' => '14',
|
| 1015 |
|
|
'uart_J2WBw' => '(uart_JTAG_CONNECT== "XILINX_JTAG_WB") ? 1+1+uart_JDw+uart_JAw : 1',
|
| 1016 |
|
|
'ram_JTAG_CONNECT' => '"XILINX_JTAG_WB"',
|
| 1017 |
|
|
'uart_WB2Jw' => '(uart_JTAG_CONNECT== "XILINX_JTAG_WB") ? 1+uart_JSTATUSw+uart_JINDEXw+1+uart_JDw : 1',
|
| 1018 |
|
|
'ram_J2WBw' => '(ram_JTAG_CONNECT== "XILINX_JTAG_WB") ? 1+1+ram_JDw+ram_JAw : 1',
|
| 1019 |
|
|
'uart_JSTATUSw' => '8',
|
| 1020 |
|
|
'uart_JTAG_CONNECT' => '"XILINX_JTAG_WB"'
|
| 1021 |
|
|
}
|
| 1022 |
|
|
},
|
| 1023 |
|
|
'3' => {
|
| 1024 |
|
|
'parameters' => {
|
| 1025 |
|
|
'ram_Dw' => '32',
|
| 1026 |
|
|
'ram_JAw' => '32',
|
| 1027 |
|
|
'ram_JTAG_INDEX' => 'CORE_ID',
|
| 1028 |
|
|
'uart_JAw' => '32',
|
| 1029 |
|
|
'uart_JTAG_INDEX' => '126-CORE_ID',
|
| 1030 |
|
|
'ram_JDw' => 'ram_Dw',
|
| 1031 |
|
|
'uart_JINDEXw' => '8',
|
| 1032 |
|
|
'ram_JTAG_CHAIN' => '4',
|
| 1033 |
|
|
'uart_JTAG_CHAIN' => '3',
|
| 1034 |
|
|
'ram_WB2Jw' => '(ram_JTAG_CONNECT== "XILINX_JTAG_WB") ? 1+ram_JSTATUSw+ram_JINDEXw+1+ram_JDw : 1',
|
| 1035 |
|
|
'ram_Aw' => '14',
|
| 1036 |
|
|
'ram_JSTATUSw' => '8',
|
| 1037 |
|
|
'uart_JDw' => '32',
|
| 1038 |
|
|
'uart_J2WBw' => '(uart_JTAG_CONNECT== "XILINX_JTAG_WB") ? 1+1+uart_JDw+uart_JAw : 1',
|
| 1039 |
|
|
'ram_JINDEXw' => '8',
|
| 1040 |
|
|
'ram_JTAG_CONNECT' => '"XILINX_JTAG_WB"',
|
| 1041 |
|
|
'uart_WB2Jw' => '(uart_JTAG_CONNECT== "XILINX_JTAG_WB") ? 1+uart_JSTATUSw+uart_JINDEXw+1+uart_JDw : 1',
|
| 1042 |
|
|
'uart_JSTATUSw' => '8',
|
| 1043 |
|
|
'uart_JTAG_CONNECT' => '"XILINX_JTAG_WB"',
|
| 1044 |
|
|
'ram_J2WBw' => '(ram_JTAG_CONNECT== "XILINX_JTAG_WB") ? 1+1+ram_JDw+ram_JAw : 1'
|
| 1045 |
|
|
}
|
| 1046 |
|
|
}
|
| 1047 |
|
|
},
|
| 1048 |
|
|
'ports' => {
|
| 1049 |
|
|
'uart_RxD_din_sim' => {
|
| 1050 |
|
|
'intfc_name' => 'socket:RxD_sim[0]',
|
| 1051 |
|
|
'range' => '7:0 ',
|
| 1052 |
|
|
'intfc_port' => 'RxD_din_sim',
|
| 1053 |
|
|
'type' => 'input',
|
| 1054 |
|
|
'instance_name' => 'ProNoC_jtag_uart0'
|
| 1055 |
|
|
},
|
| 1056 |
|
|
'ram_wb_to_jtag' => {
|
| 1057 |
48 |
alirezamon |
'intfc_name' => 'socket:jtag_to_wb[0]',
|
| 1058 |
54 |
alirezamon |
'range' => 'ram_WB2Jw-1 : 0',
|
| 1059 |
|
|
'instance_name' => 'single_port_ram0',
|
| 1060 |
48 |
alirezamon |
'type' => 'output',
|
| 1061 |
|
|
'intfc_port' => 'jwb_o'
|
| 1062 |
|
|
},
|
| 1063 |
54 |
alirezamon |
'source_clk_in' => {
|
| 1064 |
|
|
'intfc_name' => 'plug:clk[0]',
|
| 1065 |
|
|
'range' => '',
|
| 1066 |
|
|
'instance_name' => 'clk_source0',
|
| 1067 |
|
|
'type' => 'input',
|
| 1068 |
|
|
'intfc_port' => 'clk_i'
|
| 1069 |
|
|
},
|
| 1070 |
|
|
'source_reset_in' => {
|
| 1071 |
|
|
'intfc_name' => 'plug:reset[0]',
|
| 1072 |
|
|
'range' => '',
|
| 1073 |
|
|
'instance_name' => 'clk_source0',
|
| 1074 |
|
|
'type' => 'input',
|
| 1075 |
|
|
'intfc_port' => 'reset_i'
|
| 1076 |
48 |
alirezamon |
},
|
| 1077 |
54 |
alirezamon |
'uart_RxD_ready_sim' => {
|
| 1078 |
|
|
'intfc_port' => 'RxD_ready_sim',
|
| 1079 |
|
|
'type' => 'output',
|
| 1080 |
|
|
'instance_name' => 'ProNoC_jtag_uart0',
|
| 1081 |
|
|
'intfc_name' => 'socket:RxD_sim[0]',
|
| 1082 |
|
|
'range' => ''
|
| 1083 |
|
|
},
|
| 1084 |
|
|
'uart_jtag_to_wb' => {
|
| 1085 |
48 |
alirezamon |
'type' => 'input',
|
| 1086 |
|
|
'intfc_port' => 'jwb_i',
|
| 1087 |
54 |
alirezamon |
'instance_name' => 'ProNoC_jtag_uart0',
|
| 1088 |
|
|
'range' => 'uart_J2WBw-1 : 0',
|
| 1089 |
|
|
'intfc_name' => 'socket:jtag_to_wb[0]'
|
| 1090 |
48 |
alirezamon |
},
|
| 1091 |
54 |
alirezamon |
'ni_current_r_addr' => {
|
| 1092 |
|
|
'intfc_name' => 'socket:ni[0]',
|
| 1093 |
|
|
'range' => 'ni_RAw-1 : 0',
|
| 1094 |
|
|
'instance_name' => 'ni_master0',
|
| 1095 |
|
|
'type' => 'input',
|
| 1096 |
|
|
'intfc_port' => 'current_r_addr'
|
| 1097 |
|
|
},
|
| 1098 |
|
|
'uart_RxD_wr_sim' => {
|
| 1099 |
|
|
'range' => '',
|
| 1100 |
|
|
'intfc_name' => 'socket:RxD_sim[0]',
|
| 1101 |
|
|
'instance_name' => 'ProNoC_jtag_uart0',
|
| 1102 |
|
|
'type' => 'input',
|
| 1103 |
|
|
'intfc_port' => 'RxD_wr_sim'
|
| 1104 |
48 |
alirezamon |
},
|
| 1105 |
54 |
alirezamon |
'ni_chan_out' => {
|
| 1106 |
|
|
'instance_name' => 'ni_master0',
|
| 1107 |
|
|
'type' => 'output',
|
| 1108 |
|
|
'intfc_port' => 'chan_out',
|
| 1109 |
|
|
'range' => 'smartflit_chanel_t',
|
| 1110 |
|
|
'intfc_name' => 'socket:ni[0]'
|
| 1111 |
|
|
},
|
| 1112 |
|
|
'ni_chan_in' => {
|
| 1113 |
|
|
'intfc_name' => 'socket:ni[0]',
|
| 1114 |
|
|
'range' => 'smartflit_chanel_t',
|
| 1115 |
|
|
'type' => 'input',
|
| 1116 |
|
|
'intfc_port' => 'chan_in',
|
| 1117 |
|
|
'instance_name' => 'ni_master0'
|
| 1118 |
48 |
alirezamon |
},
|
| 1119 |
54 |
alirezamon |
'ni_current_e_addr' => {
|
| 1120 |
|
|
'intfc_port' => 'current_e_addr',
|
| 1121 |
|
|
'type' => 'input',
|
| 1122 |
|
|
'instance_name' => 'ni_master0',
|
| 1123 |
|
|
'intfc_name' => 'socket:ni[0]',
|
| 1124 |
|
|
'range' => 'ni_EAw-1 : 0'
|
| 1125 |
|
|
},
|
| 1126 |
|
|
'uart_wb_to_jtag' => {
|
| 1127 |
48 |
alirezamon |
'intfc_port' => 'jwb_o',
|
| 1128 |
54 |
alirezamon |
'instance_name' => 'ProNoC_jtag_uart0',
|
| 1129 |
|
|
'type' => 'output',
|
| 1130 |
|
|
'range' => 'uart_WB2Jw-1 : 0',
|
| 1131 |
|
|
'intfc_name' => 'socket:jtag_to_wb[0]'
|
| 1132 |
48 |
alirezamon |
},
|
| 1133 |
54 |
alirezamon |
'ram_jtag_to_wb' => {
|
| 1134 |
48 |
alirezamon |
'type' => 'input',
|
| 1135 |
|
|
'intfc_port' => 'jwb_i',
|
| 1136 |
54 |
alirezamon |
'instance_name' => 'single_port_ram0',
|
| 1137 |
48 |
alirezamon |
'intfc_name' => 'socket:jtag_to_wb[0]',
|
| 1138 |
54 |
alirezamon |
'range' => 'ram_J2WBw-1 : 0'
|
| 1139 |
48 |
alirezamon |
},
|
| 1140 |
54 |
alirezamon |
'cpu_cpu_en' => {
|
| 1141 |
|
|
'intfc_name' => 'plug:enable[0]',
|
| 1142 |
|
|
'range' => '',
|
| 1143 |
|
|
'intfc_port' => 'enable_i',
|
| 1144 |
|
|
'instance_name' => 'mor1kx0',
|
| 1145 |
|
|
'type' => 'input'
|
| 1146 |
|
|
}
|
| 1147 |
|
|
}
|
| 1148 |
|
|
}, 'ip_gen' )
|
| 1149 |
|
|
}
|
| 1150 |
|
|
},
|
| 1151 |
|
|
'MEM1' => {
|
| 1152 |
|
|
'percent' => '75',
|
| 1153 |
|
|
'width' => '14'
|
| 1154 |
|
|
},
|
| 1155 |
|
|
'SOURCE_SET' => {
|
| 1156 |
|
|
'clk_number' => 1,
|
| 1157 |
|
|
'reset_number' => 1,
|
| 1158 |
|
|
'reset_0_name' => 'reset',
|
| 1159 |
|
|
'REDEFINE_TOP' => 0,
|
| 1160 |
|
|
'clk_0_name' => 'clk',
|
| 1161 |
|
|
'SOC' => bless( {
|
| 1162 |
|
|
'gui_status' => {
|
| 1163 |
|
|
'timeout' => 0,
|
| 1164 |
|
|
'status' => 'ideal'
|
| 1165 |
48 |
alirezamon |
},
|
| 1166 |
54 |
alirezamon |
'hdl_files' => undef,
|
| 1167 |
|
|
'instances' => {
|
| 1168 |
|
|
'TOP' => {
|
| 1169 |
|
|
'parameters_order' => [],
|
| 1170 |
|
|
'sockets' => {},
|
| 1171 |
|
|
'category' => 'TOP',
|
| 1172 |
|
|
'description_pdf' => undef,
|
| 1173 |
|
|
'module' => 'TOP',
|
| 1174 |
|
|
'plugs' => {
|
| 1175 |
|
|
'reset' => {
|
| 1176 |
|
|
'connection_num' => undef,
|
| 1177 |
|
|
'value' => 1,
|
| 1178 |
|
|
'type' => 'num',
|
| 1179 |
|
|
'nums' => {
|
| 1180 |
|
|
'0' => {
|
| 1181 |
|
|
'connect_id' => 'IO',
|
| 1182 |
|
|
'name' => 'reset',
|
| 1183 |
|
|
'connect_socket' => undef,
|
| 1184 |
|
|
'connect_socket_num' => undef
|
| 1185 |
|
|
}
|
| 1186 |
|
|
}
|
| 1187 |
|
|
},
|
| 1188 |
|
|
'clk' => {
|
| 1189 |
|
|
'connection_num' => undef,
|
| 1190 |
|
|
'type' => 'num',
|
| 1191 |
|
|
'nums' => {
|
| 1192 |
|
|
'0' => {
|
| 1193 |
|
|
'name' => 'clk',
|
| 1194 |
|
|
'connect_id' => 'IO',
|
| 1195 |
|
|
'connect_socket' => undef,
|
| 1196 |
|
|
'connect_socket_num' => undef
|
| 1197 |
|
|
}
|
| 1198 |
|
|
},
|
| 1199 |
|
|
'value' => 1
|
| 1200 |
|
|
}
|
| 1201 |
|
|
},
|
| 1202 |
|
|
'module_name' => 'TOP',
|
| 1203 |
|
|
'instance_name' => 'TOP'
|
| 1204 |
|
|
}
|
| 1205 |
48 |
alirezamon |
},
|
| 1206 |
54 |
alirezamon |
'instance_order' => [
|
| 1207 |
|
|
'TOP'
|
| 1208 |
|
|
],
|
| 1209 |
|
|
'SOURCE_SET' => {
|
| 1210 |
|
|
'IP' => bless( {
|
| 1211 |
|
|
'file_name' => undef,
|
| 1212 |
|
|
'hdl_files_ticked' => [],
|
| 1213 |
|
|
'parameters_order' => [],
|
| 1214 |
|
|
'GUI_REMOVE_SET' => 'DISABLE',
|
| 1215 |
|
|
'hdl_files' => [],
|
| 1216 |
|
|
'plugs' => {
|
| 1217 |
|
|
'reset' => {
|
| 1218 |
|
|
'type' => 'num',
|
| 1219 |
|
|
'1' => {},
|
| 1220 |
|
|
'value' => 1,
|
| 1221 |
|
|
'0' => {
|
| 1222 |
|
|
'name' => 'reset'
|
| 1223 |
|
|
}
|
| 1224 |
|
|
},
|
| 1225 |
|
|
'clk' => {
|
| 1226 |
|
|
'type' => 'num',
|
| 1227 |
|
|
'value' => 1,
|
| 1228 |
|
|
'1' => {},
|
| 1229 |
|
|
'0' => {
|
| 1230 |
|
|
'name' => 'clk'
|
| 1231 |
|
|
}
|
| 1232 |
|
|
}
|
| 1233 |
|
|
},
|
| 1234 |
|
|
'module_name' => 'TOP',
|
| 1235 |
|
|
'ports' => {
|
| 1236 |
|
|
'clk' => {
|
| 1237 |
|
|
'intfc_name' => 'plug:clk[0]',
|
| 1238 |
|
|
'range' => undef,
|
| 1239 |
|
|
'type' => 'input',
|
| 1240 |
|
|
'intfc_port' => 'clk_i'
|
| 1241 |
|
|
},
|
| 1242 |
|
|
'reset' => {
|
| 1243 |
|
|
'intfc_port' => 'reset_i',
|
| 1244 |
|
|
'type' => 'input',
|
| 1245 |
|
|
'intfc_name' => 'plug:reset[0]',
|
| 1246 |
|
|
'range' => undef
|
| 1247 |
|
|
}
|
| 1248 |
|
|
},
|
| 1249 |
|
|
'ip_name' => 'TOP',
|
| 1250 |
|
|
'ports_order' => [],
|
| 1251 |
|
|
'category' => 'TOP'
|
| 1252 |
|
|
}, 'ip_gen' )
|
| 1253 |
48 |
alirezamon |
},
|
| 1254 |
54 |
alirezamon |
'TOP' => {
|
| 1255 |
|
|
'version' => 0
|
| 1256 |
|
|
},
|
| 1257 |
|
|
'soc_name' => {
|
| 1258 |
|
|
'TOP' => undef
|
| 1259 |
|
|
},
|
| 1260 |
|
|
'device_win_adj' => {
|
| 1261 |
|
|
'va' => '0',
|
| 1262 |
|
|
'ha' => '0'
|
| 1263 |
|
|
},
|
| 1264 |
|
|
'modules' => {}
|
| 1265 |
|
|
}, 'soc' )
|
| 1266 |
|
|
},
|
| 1267 |
|
|
'tile' => {
|
| 1268 |
|
|
'2' => {},
|
| 1269 |
|
|
'0' => {},
|
| 1270 |
|
|
'1' => {},
|
| 1271 |
|
|
'3' => {}
|
| 1272 |
|
|
},
|
| 1273 |
|
|
'compile_pin_pos' => {
|
| 1274 |
|
|
'TOP_reset' => [
|
| 1275 |
|
|
0,
|
| 1276 |
|
|
|
| 1277 |
|
|
],
|
| 1278 |
|
|
'jtag_debug_reset_in' => [
|
| 1279 |
|
|
0,
|
| 1280 |
|
|
|
| 1281 |
|
|
],
|
| 1282 |
|
|
'TOP_clk' => [
|
| 1283 |
|
|
4,
|
| 1284 |
|
|
|
| 1285 |
|
|
],
|
| 1286 |
|
|
'processors_en' => [
|
| 1287 |
|
|
6,
|
| 1288 |
|
|
|
| 1289 |
|
|
]
|
| 1290 |
|
|
},
|
| 1291 |
|
|
'current_tile_param' => undef,
|
| 1292 |
|
|
'gen_tiles_adj' => {
|
| 1293 |
|
|
'ha' => '0',
|
| 1294 |
|
|
'va' => '0'
|
| 1295 |
|
|
},
|
| 1296 |
|
|
'parameters_order' => {
|
| 1297 |
|
|
'noc_param' => [
|
| 1298 |
|
|
'TOPOLOGY',
|
| 1299 |
|
|
'T1',
|
| 1300 |
|
|
'T2',
|
| 1301 |
|
|
'T3',
|
| 1302 |
|
|
'V',
|
| 1303 |
|
|
'B',
|
| 1304 |
|
|
'Fpay',
|
| 1305 |
|
|
'ROUTE_NAME',
|
| 1306 |
|
|
'MIN_PCK_SIZE',
|
| 1307 |
|
|
'BYTE_EN',
|
| 1308 |
|
|
'SSA_EN',
|
| 1309 |
|
|
'CONGESTION_INDEX',
|
| 1310 |
|
|
'ESCAP_VC_MASK',
|
| 1311 |
|
|
'VC_REALLOCATION_TYPE',
|
| 1312 |
|
|
'COMBINATION_TYPE',
|
| 1313 |
|
|
'MUX_TYPE',
|
| 1314 |
|
|
'C',
|
| 1315 |
|
|
'DEBUG_EN',
|
| 1316 |
|
|
'ADD_PIPREG_AFTER_CROSSBAR',
|
| 1317 |
|
|
'FIRST_ARBITER_EXT_P_EN',
|
| 1318 |
|
|
'SWA_ARBITER_TYPE',
|
| 1319 |
|
|
'WEIGHTw',
|
| 1320 |
|
|
'AVC_ATOMIC_EN',
|
| 1321 |
|
|
'LB',
|
| 1322 |
|
|
'PCK_TYPE',
|
| 1323 |
|
|
'CAST_TYPE',
|
| 1324 |
|
|
'SMART_MAX',
|
| 1325 |
|
|
'SELF_LOOP_EN'
|
| 1326 |
|
|
],
|
| 1327 |
|
|
'SOURCE_SET' => [
|
| 1328 |
|
|
'clk_number',
|
| 1329 |
|
|
'clk_0_name',
|
| 1330 |
|
|
'reset_number',
|
| 1331 |
|
|
'reset_0_name'
|
| 1332 |
|
|
],
|
| 1333 |
|
|
'noc_type' => [
|
| 1334 |
|
|
'ROUTER_TYPE'
|
| 1335 |
|
|
],
|
| 1336 |
|
|
'compile' => [
|
| 1337 |
|
|
'cpu_num'
|
| 1338 |
|
|
],
|
| 1339 |
|
|
'SOURCE_SET_CONNECT' => [
|
| 1340 |
|
|
'NoC_clk',
|
| 1341 |
|
|
'T0_ss_clk_in',
|
| 1342 |
|
|
'T1_ss_clk_in',
|
| 1343 |
|
|
'T2_ss_clk_in',
|
| 1344 |
|
|
'T3_ss_clk_in',
|
| 1345 |
|
|
'NoC_reset',
|
| 1346 |
|
|
'T0_ss_reset_in',
|
| 1347 |
|
|
'T1_ss_reset_in',
|
| 1348 |
|
|
'T2_ss_reset_in',
|
| 1349 |
|
|
'T3_ss_reset_in',
|
| 1350 |
|
|
'T0_cs_clk_in',
|
| 1351 |
|
|
'T1_cs_clk_in',
|
| 1352 |
|
|
'T2_cs_clk_in',
|
| 1353 |
|
|
'T3_cs_clk_in',
|
| 1354 |
|
|
'T0_cs_reset_in',
|
| 1355 |
|
|
'T1_cs_reset_in',
|
| 1356 |
|
|
'T2_cs_reset_in',
|
| 1357 |
|
|
'T3_cs_reset_in'
|
| 1358 |
|
|
]
|
| 1359 |
|
|
},
|
| 1360 |
|
|
'noc_indept_param' => {},
|
| 1361 |
|
|
'file_name' => undef,
|
| 1362 |
|
|
'noc_param' => {
|
| 1363 |
|
|
'VC_REALLOCATION_TYPE' => '"NONATOMIC"',
|
| 1364 |
|
|
'COMBINATION_TYPE' => '"COMB_NONSPEC"',
|
| 1365 |
|
|
'T3' => '1',
|
| 1366 |
|
|
'ROUTE_NAME' => '"XY"',
|
| 1367 |
|
|
'C' => 0,
|
| 1368 |
|
|
'V' => '2',
|
| 1369 |
|
|
'SSA_EN' => '"NO"',
|
| 1370 |
|
|
'CONGESTION_INDEX' => 3,
|
| 1371 |
|
|
'ADD_PIPREG_AFTER_CROSSBAR' => '1\'b0',
|
| 1372 |
|
|
'WEIGHTw' => '4',
|
| 1373 |
|
|
'DEBUG_EN' => '0',
|
| 1374 |
|
|
'SMART_MAX' => '0',
|
| 1375 |
|
|
'SWA_ARBITER_TYPE' => '"RRA"',
|
| 1376 |
|
|
'FIRST_ARBITER_EXT_P_EN' => 1,
|
| 1377 |
|
|
'SELF_LOOP_EN' => '"NO"',
|
| 1378 |
|
|
'Fpay' => '32',
|
| 1379 |
|
|
'T1' => '2',
|
| 1380 |
|
|
'MUX_TYPE' => '"BINARY"',
|
| 1381 |
|
|
'PCK_TYPE' => '"MULTI_FLIT"',
|
| 1382 |
|
|
'BYTE_EN' => '1',
|
| 1383 |
|
|
'AVC_ATOMIC_EN' => 0,
|
| 1384 |
|
|
'MIN_PCK_SIZE' => '2',
|
| 1385 |
|
|
'ESCAP_VC_MASK' => '2\'b01',
|
| 1386 |
|
|
'T2' => '2',
|
| 1387 |
|
|
'B' => '4',
|
| 1388 |
|
|
'CAST_TYPE' => '"UNICAST"',
|
| 1389 |
|
|
'TOPOLOGY' => '"MESH"',
|
| 1390 |
|
|
'LB' => '4'
|
| 1391 |
|
|
},
|
| 1392 |
|
|
'compile_pin' => {
|
| 1393 |
|
|
'TOP_reset' => '*GND',
|
| 1394 |
|
|
'jtag_debug_reset_in' => '*GND',
|
| 1395 |
|
|
'TOP_clk' => 'FPGA_CLK1_50',
|
| 1396 |
|
|
'processors_en' => 'KEY'
|
| 1397 |
|
|
},
|
| 1398 |
|
|
'ROM2' => {
|
| 1399 |
|
|
'start' => 0,
|
| 1400 |
|
|
'end' => 49152
|
| 1401 |
|
|
},
|
| 1402 |
|
|
'gui_status' => {
|
| 1403 |
|
|
'timeout' => 0,
|
| 1404 |
|
|
'status' => 'save_project'
|
| 1405 |
|
|
},
|
| 1406 |
|
|
'SOURCE_SET_CONNECT' => {
|
| 1407 |
|
|
'T2_cs_clk_in' => 'clk',
|
| 1408 |
|
|
'T1_cs_clk_in' => 'clk',
|
| 1409 |
|
|
'T0_cs_clk_in' => 'clk',
|
| 1410 |
|
|
'T0_ss_clk_in' => 'clk0',
|
| 1411 |
|
|
'T3_ss_clk_in' => 'clk0',
|
| 1412 |
|
|
'T2_ss_reset_in' => 'reset0',
|
| 1413 |
|
|
'T2_cs_reset_in' => 'reset',
|
| 1414 |
|
|
'T0_ss_reset_in' => 'reset0',
|
| 1415 |
|
|
'T1_ss_clk_in' => 'clk0',
|
| 1416 |
|
|
'T3_cs_clk_in' => 'clk',
|
| 1417 |
|
|
'T3_cs_reset_in' => 'reset',
|
| 1418 |
|
|
'T1_ss_reset_in' => 'reset0',
|
| 1419 |
|
|
'T2_ss_clk_in' => 'clk0',
|
| 1420 |
|
|
'T0_cs_reset_in' => 'reset',
|
| 1421 |
|
|
'NoC_clk' => 'clk',
|
| 1422 |
|
|
'T1_cs_reset_in' => 'reset',
|
| 1423 |
|
|
'T3_ss_reset_in' => 'reset0',
|
| 1424 |
|
|
'NoC_reset' => 'reset'
|
| 1425 |
|
|
},
|
| 1426 |
|
|
'compile_pin_range_hsb' => {},
|
| 1427 |
|
|
'setting' => {
|
| 1428 |
|
|
'show_adv_setting' => 0,
|
| 1429 |
|
|
'show_noc_setting' => 1,
|
| 1430 |
|
|
'show_tile_setting' => 1,
|
| 1431 |
|
|
'soc_path' => 'lib/soc'
|
| 1432 |
|
|
},
|
| 1433 |
|
|
'RAM2' => {
|
| 1434 |
|
|
'start' => 49152,
|
| 1435 |
|
|
'end' => 65536
|
| 1436 |
|
|
},
|
| 1437 |
|
|
'top_ip' => bless( {
|
| 1438 |
|
|
'ports' => {
|
| 1439 |
|
|
'T2_uart_wb_to_jtag' => {
|
| 1440 |
|
|
'range' => 'T2_uart_WB2Jw-1 : 0',
|
| 1441 |
|
|
'intfc_name' => 'socket:jtag_to_wb[0]',
|
| 1442 |
|
|
'instance_name' => 'T2',
|
| 1443 |
|
|
'intfc_port' => 'jwb_o',
|
| 1444 |
|
|
'type' => 'output'
|
| 1445 |
|
|
},
|
| 1446 |
|
|
'T1_uart_jtag_to_wb' => {
|
| 1447 |
|
|
'range' => 'T1_uart_J2WBw-1 : 0',
|
| 1448 |
|
|
'intfc_name' => 'socket:jtag_to_wb[0]',
|
| 1449 |
|
|
'type' => 'input',
|
| 1450 |
|
|
'instance_name' => 'T1',
|
| 1451 |
|
|
'intfc_port' => 'jwb_i'
|
| 1452 |
|
|
},
|
| 1453 |
|
|
'clk' => {
|
| 1454 |
|
|
'intfc_name' => 'plug:clk[0]',
|
| 1455 |
|
|
'range' => '',
|
| 1456 |
|
|
'intfc_port' => 'clk_i',
|
| 1457 |
|
|
'instance_name' => 'IO',
|
| 1458 |
|
|
'type' => 'input'
|
| 1459 |
|
|
},
|
| 1460 |
|
|
'T3_ram_wb_to_jtag' => {
|
| 1461 |
|
|
'instance_name' => 'T3',
|
| 1462 |
|
|
'intfc_port' => 'jwb_o',
|
| 1463 |
|
|
'type' => 'output',
|
| 1464 |
|
|
'intfc_name' => 'socket:jtag_to_wb[0]',
|
| 1465 |
|
|
'range' => 'T3_ram_WB2Jw-1 : 0'
|
| 1466 |
|
|
},
|
| 1467 |
|
|
'T3_ram_jtag_to_wb' => {
|
| 1468 |
|
|
'range' => 'T3_ram_J2WBw-1 : 0',
|
| 1469 |
|
|
'intfc_name' => 'socket:jtag_to_wb[0]',
|
| 1470 |
|
|
'instance_name' => 'T3',
|
| 1471 |
|
|
'intfc_port' => 'jwb_i',
|
| 1472 |
|
|
'type' => 'input'
|
| 1473 |
|
|
},
|
| 1474 |
|
|
'T1_uart_wb_to_jtag' => {
|
| 1475 |
|
|
'intfc_name' => 'socket:jtag_to_wb[0]',
|
| 1476 |
|
|
'range' => 'T1_uart_WB2Jw-1 : 0',
|
| 1477 |
|
|
'type' => 'output',
|
| 1478 |
|
|
'instance_name' => 'T1',
|
| 1479 |
|
|
'intfc_port' => 'jwb_o'
|
| 1480 |
|
|
},
|
| 1481 |
|
|
'T3_uart_wb_to_jtag' => {
|
| 1482 |
|
|
'instance_name' => 'T3',
|
| 1483 |
|
|
'intfc_port' => 'jwb_o',
|
| 1484 |
|
|
'type' => 'output',
|
| 1485 |
|
|
'intfc_name' => 'socket:jtag_to_wb[0]',
|
| 1486 |
|
|
'range' => 'T3_uart_WB2Jw-1 : 0'
|
| 1487 |
|
|
},
|
| 1488 |
|
|
'processors_en' => {
|
| 1489 |
|
|
'intfc_name' => 'plug:enable[0]',
|
| 1490 |
|
|
'range' => '',
|
| 1491 |
|
|
'instance_name' => 'IO',
|
| 1492 |
|
|
'intfc_port' => 'enable_i',
|
| 1493 |
|
|
'type' => 'input'
|
| 1494 |
|
|
},
|
| 1495 |
|
|
'reset' => {
|
| 1496 |
|
|
'type' => 'input',
|
| 1497 |
|
|
'instance_name' => 'IO',
|
| 1498 |
|
|
'intfc_port' => 'reset_i',
|
| 1499 |
|
|
'intfc_name' => 'plug:reset[0]',
|
| 1500 |
|
|
'range' => ''
|
| 1501 |
|
|
},
|
| 1502 |
|
|
'T0_ram_jtag_to_wb' => {
|
| 1503 |
|
|
'range' => 'T0_ram_J2WBw-1 : 0',
|
| 1504 |
|
|
'intfc_name' => 'socket:jtag_to_wb[0]',
|
| 1505 |
|
|
'intfc_port' => 'jwb_i',
|
| 1506 |
|
|
'instance_name' => 'T0',
|
| 1507 |
|
|
'type' => 'input'
|
| 1508 |
|
|
},
|
| 1509 |
|
|
'T0_uart_jtag_to_wb' => {
|
| 1510 |
|
|
'intfc_name' => 'socket:jtag_to_wb[0]',
|
| 1511 |
|
|
'range' => 'T0_uart_J2WBw-1 : 0',
|
| 1512 |
|
|
'instance_name' => 'T0',
|
| 1513 |
|
|
'type' => 'input',
|
| 1514 |
|
|
'intfc_port' => 'jwb_i'
|
| 1515 |
|
|
},
|
| 1516 |
|
|
'T1_ram_jtag_to_wb' => {
|
| 1517 |
|
|
'intfc_name' => 'socket:jtag_to_wb[0]',
|
| 1518 |
|
|
'range' => 'T1_ram_J2WBw-1 : 0',
|
| 1519 |
|
|
'type' => 'input',
|
| 1520 |
|
|
'instance_name' => 'T1',
|
| 1521 |
|
|
'intfc_port' => 'jwb_i'
|
| 1522 |
|
|
},
|
| 1523 |
|
|
'T3_uart_jtag_to_wb' => {
|
| 1524 |
|
|
'intfc_name' => 'socket:jtag_to_wb[0]',
|
| 1525 |
|
|
'range' => 'T3_uart_J2WBw-1 : 0',
|
| 1526 |
|
|
'intfc_port' => 'jwb_i',
|
| 1527 |
|
|
'instance_name' => 'T3',
|
| 1528 |
|
|
'type' => 'input'
|
| 1529 |
|
|
},
|
| 1530 |
|
|
'T2_uart_jtag_to_wb' => {
|
| 1531 |
|
|
'instance_name' => 'T2',
|
| 1532 |
|
|
'type' => 'input',
|
| 1533 |
|
|
'intfc_port' => 'jwb_i',
|
| 1534 |
|
|
'intfc_name' => 'socket:jtag_to_wb[0]',
|
| 1535 |
|
|
'range' => 'T2_uart_J2WBw-1 : 0'
|
| 1536 |
|
|
},
|
| 1537 |
|
|
'T2_ram_jtag_to_wb' => {
|
| 1538 |
|
|
'range' => 'T2_ram_J2WBw-1 : 0',
|
| 1539 |
|
|
'intfc_name' => 'socket:jtag_to_wb[0]',
|
| 1540 |
|
|
'instance_name' => 'T2',
|
| 1541 |
|
|
'type' => 'input',
|
| 1542 |
|
|
'intfc_port' => 'jwb_i'
|
| 1543 |
|
|
},
|
| 1544 |
|
|
'T1_ram_wb_to_jtag' => {
|
| 1545 |
|
|
'instance_name' => 'T1',
|
| 1546 |
|
|
'intfc_port' => 'jwb_o',
|
| 1547 |
|
|
'type' => 'output',
|
| 1548 |
|
|
'range' => 'T1_ram_WB2Jw-1 : 0',
|
| 1549 |
|
|
'intfc_name' => 'socket:jtag_to_wb[0]'
|
| 1550 |
|
|
},
|
| 1551 |
|
|
'T0_ram_wb_to_jtag' => {
|
| 1552 |
|
|
'intfc_name' => 'socket:jtag_to_wb[0]',
|
| 1553 |
|
|
'range' => 'T0_ram_WB2Jw-1 : 0',
|
| 1554 |
|
|
'intfc_port' => 'jwb_o',
|
| 1555 |
|
|
'instance_name' => 'T0',
|
| 1556 |
|
|
'type' => 'output'
|
| 1557 |
|
|
},
|
| 1558 |
|
|
'T0_uart_wb_to_jtag' => {
|
| 1559 |
|
|
'intfc_name' => 'socket:jtag_to_wb[0]',
|
| 1560 |
|
|
'range' => 'T0_uart_WB2Jw-1 : 0',
|
| 1561 |
|
|
'type' => 'output',
|
| 1562 |
|
|
'instance_name' => 'T0',
|
| 1563 |
|
|
'intfc_port' => 'jwb_o'
|
| 1564 |
|
|
},
|
| 1565 |
|
|
'T2_ram_wb_to_jtag' => {
|
| 1566 |
|
|
'type' => 'output',
|
| 1567 |
|
|
'instance_name' => 'T2',
|
| 1568 |
|
|
'intfc_port' => 'jwb_o',
|
| 1569 |
|
|
'range' => 'T2_ram_WB2Jw-1 : 0',
|
| 1570 |
|
|
'intfc_name' => 'socket:jtag_to_wb[0]'
|
| 1571 |
|
|
}
|
| 1572 |
|
|
},
|
| 1573 |
|
|
'interface' => {
|
| 1574 |
|
|
'plug:clk[0]' => {
|
| 1575 |
|
|
'ports' => {
|
| 1576 |
|
|
'clk' => {
|
| 1577 |
|
|
'intfc_port' => 'clk_i',
|
| 1578 |
|
|
'instance_name' => 'IO',
|
| 1579 |
|
|
'type' => 'input',
|
| 1580 |
|
|
'range' => ''
|
| 1581 |
|
|
}
|
| 1582 |
|
|
}
|
| 1583 |
|
|
},
|
| 1584 |
|
|
'plug:reset[0]' => {
|
| 1585 |
|
|
'ports' => {
|
| 1586 |
|
|
'reset' => {
|
| 1587 |
|
|
'range' => '',
|
| 1588 |
|
|
'type' => 'input',
|
| 1589 |
|
|
'intfc_port' => 'reset_i',
|
| 1590 |
|
|
'instance_name' => 'IO'
|
| 1591 |
|
|
}
|
| 1592 |
|
|
}
|
| 1593 |
|
|
},
|
| 1594 |
|
|
'socket:jtag_to_wb[0]' => {
|
| 1595 |
|
|
'ports' => {
|
| 1596 |
|
|
'T0_uart_jtag_to_wb' => {
|
| 1597 |
|
|
'intfc_port' => 'jwb_i',
|
| 1598 |
|
|
'instance_name' => 'T0',
|
| 1599 |
|
|
'type' => 'input',
|
| 1600 |
|
|
'range' => 'T0_uart_J2WBw-1 : 0'
|
| 1601 |
|
|
},
|
| 1602 |
|
|
'T0_ram_jtag_to_wb' => {
|
| 1603 |
|
|
'range' => 'T0_ram_J2WBw-1 : 0',
|
| 1604 |
|
|
'intfc_port' => 'jwb_i',
|
| 1605 |
|
|
'type' => 'input',
|
| 1606 |
|
|
'instance_name' => 'T0'
|
| 1607 |
|
|
},
|
| 1608 |
|
|
'T3_uart_jtag_to_wb' => {
|
| 1609 |
|
|
'range' => 'T3_uart_J2WBw-1 : 0',
|
| 1610 |
|
|
'intfc_port' => 'jwb_i',
|
| 1611 |
|
|
'type' => 'input',
|
| 1612 |
|
|
'instance_name' => 'T3'
|
| 1613 |
|
|
},
|
| 1614 |
|
|
'T2_uart_jtag_to_wb' => {
|
| 1615 |
|
|
'range' => 'T2_uart_J2WBw-1 : 0',
|
| 1616 |
|
|
'type' => 'input',
|
| 1617 |
|
|
'intfc_port' => 'jwb_i',
|
| 1618 |
|
|
'instance_name' => 'T2'
|
| 1619 |
|
|
},
|
| 1620 |
|
|
'T1_ram_jtag_to_wb' => {
|
| 1621 |
|
|
'type' => 'input',
|
| 1622 |
|
|
'intfc_port' => 'jwb_i',
|
| 1623 |
|
|
'instance_name' => 'T1',
|
| 1624 |
|
|
'range' => 'T1_ram_J2WBw-1 : 0'
|
| 1625 |
|
|
},
|
| 1626 |
|
|
'T2_ram_jtag_to_wb' => {
|
| 1627 |
|
|
'range' => 'T2_ram_J2WBw-1 : 0',
|
| 1628 |
|
|
'intfc_port' => 'jwb_i',
|
| 1629 |
|
|
'instance_name' => 'T2',
|
| 1630 |
|
|
'type' => 'input'
|
| 1631 |
|
|
},
|
| 1632 |
|
|
'T1_ram_wb_to_jtag' => {
|
| 1633 |
|
|
'intfc_port' => 'jwb_o',
|
| 1634 |
|
|
'instance_name' => 'T1',
|
| 1635 |
|
|
'type' => 'output',
|
| 1636 |
|
|
'range' => 'T1_ram_WB2Jw-1 : 0'
|
| 1637 |
|
|
},
|
| 1638 |
|
|
'T0_ram_wb_to_jtag' => {
|
| 1639 |
|
|
'range' => 'T0_ram_WB2Jw-1 : 0',
|
| 1640 |
|
|
'intfc_port' => 'jwb_o',
|
| 1641 |
|
|
'type' => 'output',
|
| 1642 |
|
|
'instance_name' => 'T0'
|
| 1643 |
|
|
},
|
| 1644 |
|
|
'T0_uart_wb_to_jtag' => {
|
| 1645 |
|
|
'type' => 'output',
|
| 1646 |
|
|
'intfc_port' => 'jwb_o',
|
| 1647 |
|
|
'instance_name' => 'T0',
|
| 1648 |
|
|
'range' => 'T0_uart_WB2Jw-1 : 0'
|
| 1649 |
|
|
},
|
| 1650 |
|
|
'T2_ram_wb_to_jtag' => {
|
| 1651 |
|
|
'range' => 'T2_ram_WB2Jw-1 : 0',
|
| 1652 |
|
|
'type' => 'output',
|
| 1653 |
|
|
'intfc_port' => 'jwb_o',
|
| 1654 |
|
|
'instance_name' => 'T2'
|
| 1655 |
|
|
},
|
| 1656 |
|
|
'T2_uart_wb_to_jtag' => {
|
| 1657 |
|
|
'type' => 'output',
|
| 1658 |
|
|
'intfc_port' => 'jwb_o',
|
| 1659 |
|
|
'instance_name' => 'T2',
|
| 1660 |
|
|
'range' => 'T2_uart_WB2Jw-1 : 0'
|
| 1661 |
|
|
},
|
| 1662 |
|
|
'T1_uart_jtag_to_wb' => {
|
| 1663 |
|
|
'type' => 'input',
|
| 1664 |
|
|
'intfc_port' => 'jwb_i',
|
| 1665 |
|
|
'instance_name' => 'T1',
|
| 1666 |
|
|
'range' => 'T1_uart_J2WBw-1 : 0'
|
| 1667 |
|
|
},
|
| 1668 |
|
|
'T3_ram_wb_to_jtag' => {
|
| 1669 |
|
|
'range' => 'T3_ram_WB2Jw-1 : 0',
|
| 1670 |
|
|
'intfc_port' => 'jwb_o',
|
| 1671 |
|
|
'instance_name' => 'T3',
|
| 1672 |
|
|
'type' => 'output'
|
| 1673 |
|
|
},
|
| 1674 |
|
|
'T3_uart_wb_to_jtag' => {
|
| 1675 |
|
|
'type' => 'output',
|
| 1676 |
|
|
'intfc_port' => 'jwb_o',
|
| 1677 |
|
|
'instance_name' => 'T3',
|
| 1678 |
|
|
'range' => 'T3_uart_WB2Jw-1 : 0'
|
| 1679 |
|
|
},
|
| 1680 |
|
|
'T1_uart_wb_to_jtag' => {
|
| 1681 |
|
|
'instance_name' => 'T1',
|
| 1682 |
|
|
'intfc_port' => 'jwb_o',
|
| 1683 |
|
|
'type' => 'output',
|
| 1684 |
|
|
'range' => 'T1_uart_WB2Jw-1 : 0'
|
| 1685 |
|
|
},
|
| 1686 |
|
|
'T3_ram_jtag_to_wb' => {
|
| 1687 |
|
|
'range' => 'T3_ram_J2WBw-1 : 0',
|
| 1688 |
|
|
'type' => 'input',
|
| 1689 |
|
|
'intfc_port' => 'jwb_i',
|
| 1690 |
|
|
'instance_name' => 'T3'
|
| 1691 |
|
|
}
|
| 1692 |
|
|
}
|
| 1693 |
|
|
},
|
| 1694 |
|
|
'plug:enable[0]' => {
|
| 1695 |
|
|
'ports' => {
|
| 1696 |
|
|
'processors_en' => {
|
| 1697 |
|
|
'type' => 'input',
|
| 1698 |
|
|
'intfc_port' => 'enable_i',
|
| 1699 |
|
|
'instance_name' => 'IO',
|
| 1700 |
|
|
'range' => ''
|
| 1701 |
|
|
}
|
| 1702 |
|
|
}
|
| 1703 |
|
|
}
|
| 1704 |
|
|
},
|
| 1705 |
|
|
'instance_ids' => {
|
| 1706 |
|
|
'IO' => {
|
| 1707 |
48 |
alirezamon |
'ports' => {
|
| 1708 |
54 |
alirezamon |
'reset' => {
|
| 1709 |
|
|
'intfc_name' => 'plug:reset[0]',
|
| 1710 |
|
|
'range' => '',
|
| 1711 |
|
|
'intfc_port' => 'reset_i',
|
| 1712 |
|
|
'type' => 'input'
|
| 1713 |
|
|
},
|
| 1714 |
|
|
'processors_en' => {
|
| 1715 |
|
|
'intfc_port' => 'enable_i',
|
| 1716 |
|
|
'type' => 'input',
|
| 1717 |
|
|
'intfc_name' => 'plug:enable[0]',
|
| 1718 |
|
|
'range' => ''
|
| 1719 |
|
|
},
|
| 1720 |
48 |
alirezamon |
'clk' => {
|
| 1721 |
54 |
alirezamon |
'range' => '',
|
| 1722 |
|
|
'intfc_name' => 'plug:clk[0]',
|
| 1723 |
48 |
alirezamon |
'type' => 'input',
|
| 1724 |
54 |
alirezamon |
'intfc_port' => 'clk_i'
|
| 1725 |
48 |
alirezamon |
}
|
| 1726 |
|
|
}
|
| 1727 |
|
|
},
|
| 1728 |
54 |
alirezamon |
'T0' => {
|
| 1729 |
|
|
'ports' => {
|
| 1730 |
|
|
'T0_uart_wb_to_jtag' => {
|
| 1731 |
|
|
'intfc_name' => 'socket:jtag_to_wb[0]',
|
| 1732 |
|
|
'range' => 'T0_uart_WB2Jw-1 : 0',
|
| 1733 |
|
|
'type' => 'output',
|
| 1734 |
|
|
'intfc_port' => 'jwb_o'
|
| 1735 |
|
|
},
|
| 1736 |
|
|
'T0_uart_jtag_to_wb' => {
|
| 1737 |
|
|
'type' => 'input',
|
| 1738 |
|
|
'intfc_port' => 'jwb_i',
|
| 1739 |
|
|
'range' => 'T0_uart_J2WBw-1 : 0',
|
| 1740 |
|
|
'intfc_name' => 'socket:jtag_to_wb[0]'
|
| 1741 |
|
|
},
|
| 1742 |
|
|
'T0_ram_wb_to_jtag' => {
|
| 1743 |
|
|
'intfc_name' => 'socket:jtag_to_wb[0]',
|
| 1744 |
|
|
'range' => 'T0_ram_WB2Jw-1 : 0',
|
| 1745 |
|
|
'intfc_port' => 'jwb_o',
|
| 1746 |
|
|
'type' => 'output'
|
| 1747 |
|
|
},
|
| 1748 |
|
|
'T0_ram_jtag_to_wb' => {
|
| 1749 |
|
|
'type' => 'input',
|
| 1750 |
|
|
'intfc_port' => 'jwb_i',
|
| 1751 |
|
|
'range' => 'T0_ram_J2WBw-1 : 0',
|
| 1752 |
|
|
'intfc_name' => 'socket:jtag_to_wb[0]'
|
| 1753 |
|
|
}
|
| 1754 |
|
|
}
|
| 1755 |
|
|
},
|
| 1756 |
|
|
'T3' => {
|
| 1757 |
|
|
'ports' => {
|
| 1758 |
|
|
'T3_ram_wb_to_jtag' => {
|
| 1759 |
|
|
'type' => 'output',
|
| 1760 |
|
|
'intfc_port' => 'jwb_o',
|
| 1761 |
|
|
'intfc_name' => 'socket:jtag_to_wb[0]',
|
| 1762 |
|
|
'range' => 'T3_ram_WB2Jw-1 : 0'
|
| 1763 |
|
|
},
|
| 1764 |
|
|
'T3_uart_jtag_to_wb' => {
|
| 1765 |
|
|
'intfc_port' => 'jwb_i',
|
| 1766 |
|
|
'type' => 'input',
|
| 1767 |
|
|
'intfc_name' => 'socket:jtag_to_wb[0]',
|
| 1768 |
|
|
'range' => 'T3_uart_J2WBw-1 : 0'
|
| 1769 |
|
|
},
|
| 1770 |
|
|
'T3_uart_wb_to_jtag' => {
|
| 1771 |
|
|
'type' => 'output',
|
| 1772 |
|
|
'intfc_port' => 'jwb_o',
|
| 1773 |
|
|
'intfc_name' => 'socket:jtag_to_wb[0]',
|
| 1774 |
|
|
'range' => 'T3_uart_WB2Jw-1 : 0'
|
| 1775 |
|
|
},
|
| 1776 |
|
|
'T3_ram_jtag_to_wb' => {
|
| 1777 |
|
|
'type' => 'input',
|
| 1778 |
|
|
'intfc_port' => 'jwb_i',
|
| 1779 |
|
|
'intfc_name' => 'socket:jtag_to_wb[0]',
|
| 1780 |
|
|
'range' => 'T3_ram_J2WBw-1 : 0'
|
| 1781 |
|
|
}
|
| 1782 |
|
|
}
|
| 1783 |
|
|
},
|
| 1784 |
|
|
'T1' => {
|
| 1785 |
|
|
'ports' => {
|
| 1786 |
|
|
'T1_ram_wb_to_jtag' => {
|
| 1787 |
|
|
'type' => 'output',
|
| 1788 |
|
|
'intfc_port' => 'jwb_o',
|
| 1789 |
|
|
'range' => 'T1_ram_WB2Jw-1 : 0',
|
| 1790 |
|
|
'intfc_name' => 'socket:jtag_to_wb[0]'
|
| 1791 |
|
|
},
|
| 1792 |
|
|
'T1_uart_jtag_to_wb' => {
|
| 1793 |
|
|
'intfc_port' => 'jwb_i',
|
| 1794 |
|
|
'type' => 'input',
|
| 1795 |
|
|
'intfc_name' => 'socket:jtag_to_wb[0]',
|
| 1796 |
|
|
'range' => 'T1_uart_J2WBw-1 : 0'
|
| 1797 |
|
|
},
|
| 1798 |
|
|
'T1_uart_wb_to_jtag' => {
|
| 1799 |
|
|
'range' => 'T1_uart_WB2Jw-1 : 0',
|
| 1800 |
|
|
'intfc_name' => 'socket:jtag_to_wb[0]',
|
| 1801 |
|
|
'type' => 'output',
|
| 1802 |
|
|
'intfc_port' => 'jwb_o'
|
| 1803 |
|
|
},
|
| 1804 |
|
|
'T1_ram_jtag_to_wb' => {
|
| 1805 |
|
|
'intfc_port' => 'jwb_i',
|
| 1806 |
|
|
'type' => 'input',
|
| 1807 |
|
|
'intfc_name' => 'socket:jtag_to_wb[0]',
|
| 1808 |
|
|
'range' => 'T1_ram_J2WBw-1 : 0'
|
| 1809 |
|
|
}
|
| 1810 |
|
|
}
|
| 1811 |
|
|
},
|
| 1812 |
|
|
'T2' => {
|
| 1813 |
|
|
'ports' => {
|
| 1814 |
|
|
'T2_ram_wb_to_jtag' => {
|
| 1815 |
|
|
'type' => 'output',
|
| 1816 |
|
|
'intfc_port' => 'jwb_o',
|
| 1817 |
|
|
'range' => 'T2_ram_WB2Jw-1 : 0',
|
| 1818 |
|
|
'intfc_name' => 'socket:jtag_to_wb[0]'
|
| 1819 |
|
|
},
|
| 1820 |
|
|
'T2_uart_jtag_to_wb' => {
|
| 1821 |
|
|
'range' => 'T2_uart_J2WBw-1 : 0',
|
| 1822 |
|
|
'intfc_name' => 'socket:jtag_to_wb[0]',
|
| 1823 |
|
|
'intfc_port' => 'jwb_i',
|
| 1824 |
|
|
'type' => 'input'
|
| 1825 |
|
|
},
|
| 1826 |
|
|
'T2_ram_jtag_to_wb' => {
|
| 1827 |
|
|
'type' => 'input',
|
| 1828 |
|
|
'intfc_port' => 'jwb_i',
|
| 1829 |
|
|
'intfc_name' => 'socket:jtag_to_wb[0]',
|
| 1830 |
|
|
'range' => 'T2_ram_J2WBw-1 : 0'
|
| 1831 |
|
|
},
|
| 1832 |
|
|
'T2_uart_wb_to_jtag' => {
|
| 1833 |
|
|
'intfc_port' => 'jwb_o',
|
| 1834 |
|
|
'type' => 'output',
|
| 1835 |
|
|
'intfc_name' => 'socket:jtag_to_wb[0]',
|
| 1836 |
|
|
'range' => 'T2_uart_WB2Jw-1 : 0'
|
| 1837 |
|
|
}
|
| 1838 |
|
|
}
|
| 1839 |
|
|
}
|
| 1840 |
|
|
}
|
| 1841 |
|
|
}, 'ip_gen' ),
|
| 1842 |
|
|
'ROM0' => {
|
| 1843 |
|
|
'start' => 0,
|
| 1844 |
|
|
'end' => 22937
|
| 1845 |
|
|
},
|
| 1846 |
|
|
'soc_param' => {
|
| 1847 |
|
|
'default' => {
|
| 1848 |
|
|
'ram_J2WBw' => '(ram_JTAG_CONNECT== "XILINX_JTAG_WB") ? 1+1+ram_JDw+ram_JAw : 1',
|
| 1849 |
|
|
'uart_JTAG_CONNECT' => '"XILINX_JTAG_WB"',
|
| 1850 |
|
|
'uart_JSTATUSw' => '8',
|
| 1851 |
|
|
'ram_JTAG_CONNECT' => '"XILINX_JTAG_WB"',
|
| 1852 |
|
|
'uart_WB2Jw' => '(uart_JTAG_CONNECT== "XILINX_JTAG_WB") ? 1+uart_JSTATUSw+uart_JINDEXw+1+uart_JDw : 1',
|
| 1853 |
|
|
'ram_WB2Jw' => '(ram_JTAG_CONNECT== "XILINX_JTAG_WB") ? 1+ram_JSTATUSw+ram_JINDEXw+1+ram_JDw : 1',
|
| 1854 |
|
|
'ram_Aw' => '14',
|
| 1855 |
|
|
'uart_J2WBw' => '(uart_JTAG_CONNECT== "XILINX_JTAG_WB") ? 1+1+uart_JDw+uart_JAw : 1',
|
| 1856 |
|
|
'uart_JDw' => '32',
|
| 1857 |
|
|
'ram_JSTATUSw' => '8',
|
| 1858 |
|
|
'ram_JINDEXw' => '8',
|
| 1859 |
|
|
'uart_JTAG_INDEX' => '126-CORE_ID',
|
| 1860 |
|
|
'ram_JAw' => '32',
|
| 1861 |
|
|
'ram_JTAG_INDEX' => 'CORE_ID',
|
| 1862 |
|
|
'ram_Dw' => '32',
|
| 1863 |
|
|
'uart_JAw' => '32',
|
| 1864 |
|
|
'ram_JTAG_CHAIN' => '4',
|
| 1865 |
|
|
'uart_JINDEXw' => '8',
|
| 1866 |
|
|
'ram_JDw' => 'ram_Dw',
|
| 1867 |
|
|
'uart_JTAG_CHAIN' => '3'
|
| 1868 |
48 |
alirezamon |
}
|
| 1869 |
54 |
alirezamon |
},
|
| 1870 |
|
|
'verilator' => {
|
| 1871 |
|
|
'libs' => {
|
| 1872 |
|
|
'Vtile3' => '--top-module tile_3',
|
| 1873 |
|
|
'Vtile0' => '--top-module tile_0',
|
| 1874 |
|
|
'Vrouter1' => '--top-module router_top_v -GP=5 ',
|
| 1875 |
|
|
'Vtile1' => '--top-module tile_1',
|
| 1876 |
|
|
'Vtile2' => '--top-module tile_2'
|
| 1877 |
|
|
}
|
| 1878 |
|
|
},
|
| 1879 |
|
|
'JTAG' => {
|
| 1880 |
|
|
'M_CHAIN' => 4
|
| 1881 |
|
|
},
|
| 1882 |
|
|
'get_config_adj' => {
|
| 1883 |
|
|
'va' => '0',
|
| 1884 |
|
|
'ha' => '0'
|
| 1885 |
|
|
},
|
| 1886 |
|
|
'MEM0' => {
|
| 1887 |
|
|
'percent' => '70',
|
| 1888 |
|
|
'width' => '13'
|
| 1889 |
|
|
},
|
| 1890 |
|
|
'RAM1' => {
|
| 1891 |
|
|
'end' => 65536,
|
| 1892 |
|
|
'start' => 49152
|
| 1893 |
|
|
},
|
| 1894 |
|
|
'MEM3' => {
|
| 1895 |
|
|
'width' => '14',
|
| 1896 |
|
|
'percent' => '75'
|
| 1897 |
|
|
},
|
| 1898 |
|
|
'ROM1' => {
|
| 1899 |
|
|
'end' => 49152,
|
| 1900 |
|
|
'start' => 0
|
| 1901 |
|
|
},
|
| 1902 |
|
|
'compile_assign_type' => {
|
| 1903 |
|
|
'TOP_reset' => 'Direct',
|
| 1904 |
|
|
'jtag_debug_reset_in' => 'Direct',
|
| 1905 |
|
|
'processors_en' => 'Direct',
|
| 1906 |
|
|
'TOP_clk' => 'Direct'
|
| 1907 |
|
|
},
|
| 1908 |
|
|
'noc_type' => {
|
| 1909 |
|
|
'ROUTER_TYPE' => '"VC_BASED"'
|
| 1910 |
|
|
},
|
| 1911 |
|
|
'liststore' => {
|
| 1912 |
|
|
'ha' => '0',
|
| 1913 |
|
|
'va' => '0'
|
| 1914 |
|
|
},
|
| 1915 |
|
|
'fpga_param' => {},
|
| 1916 |
|
|
'RAM0' => {
|
| 1917 |
|
|
'end' => 32768,
|
| 1918 |
|
|
'start' => 22937
|
| 1919 |
48 |
alirezamon |
}
|
| 1920 |
54 |
alirezamon |
}, 'mpsoc' );
|
