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Subversion Repositories an-fpga-implementation-of-low-latency-noc-based-mpsoc

[/] [an-fpga-implementation-of-low-latency-noc-based-mpsoc/] [trunk/] [mpsoc/] [perl_gui/] [lib/] [perl/] [hdr_file_gen.pl] - Blame information for rev 38

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Line No. Rev Author Line
1 17 alirezamon
use lib 'lib/perl';
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use strict;
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use warnings;
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use soc;
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use ip;
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##################
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#     header file gen
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##################
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sub get_instance_global_variable{
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        my ($soc,$id)   = @_;
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        my $module      =$soc->soc_get_module($id);
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        my $module_name =$soc->soc_get_module_name($id);
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        my $category    =$soc->soc_get_category($id);
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        my $inst        =$soc->soc_get_instance_name($id);
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        my @plugs= $soc->soc_get_all_plugs_of_an_instance($id);
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        my %params= $soc->soc_get_module_param($id);
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        #add two extra variable the instance name and base addresses
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        my $core_id= $soc->object_get_attribute('global_param','CORE_ID');
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        $params{CORE_ID}=(defined $core_id)? $core_id: 0;
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        $params{IP}=$inst;
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        $params{CORE}=$id;
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        foreach my $plug (@plugs){
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                my @nums=$soc->soc_list_plug_nums($id,$plug);
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                foreach my $num (@nums){
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                        my ($addr,$base,$end,$name,$connect_id,$connect_socket,$connect_socket_num)=$soc->soc_get_plug($id,$plug,$num);
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                        #wishbone slave address
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                        if((defined $connect_socket) && ($connect_socket eq 'wb_slave')){
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                                #print "$addr,$base,$end,$connect_id,$connect_socket,$connect_socket_num\n";
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                                my $base_hex=sprintf("0X%08x", $base);
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                                my $end_hex=sprintf("0X%08x", $end);
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                                my $val="BASE".$num;
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                                $params{$val}=$base_hex;
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                        }
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                }
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        }
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        $params{BASE}=$params{BASE0} if(defined $params{BASE0});
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        return (\%params);
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}
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sub replace_golb_var{
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        my ($hdr,$ref)=@_;
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        my %params= %{$ref};
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        foreach my $p (sort keys %params){
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                my $pattern=  '\$\{?' . $p . '(\}|\b)';
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                ($hdr=$hdr)=~s/$pattern/$params{$p}/g;
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        }
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        return $hdr;
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}
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sub generate_header_file{
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        my ($soc,$project_dir,$sw_path,$hw_path,$dir)= @_;
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        my $soc_name=$soc->object_get_attribute('soc_name');
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        $soc_name = uc($soc_name);
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        if(!defined $soc_name){$soc_name='soc'};
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        my @instances=$soc->soc_get_all_instances();
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        my $system_h="#ifndef $soc_name\_SYSTEM_H\n\t#define $soc_name\_SYSTEM_H\n";
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        #add_text_to_string(\$system_h, "\n #include <stdio.h> \n #include <stdlib.h> \n #include \"aemb/core.hh\"");
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        my $ip = ip->lib_new ();
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        foreach my $id (@instances){
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                my $module              =$soc->soc_get_module($id);
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                my $module_name =$soc->soc_get_module_name($id);
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                my $category    =$soc->soc_get_category($id);
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                my $inst                =$soc->soc_get_instance_name($id);
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                add_text_to_string(\$system_h,"\n \n /*  $inst   */ \n");
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                #$inst=uc($inst);
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                # print base address
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                my @plugs= $soc->soc_get_all_plugs_of_an_instance($id);
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                my %params= %{get_instance_global_variable($soc,$id)};
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                foreach my $plug (@plugs){
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                        my @nums=$soc->soc_list_plug_nums($id,$plug);
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                        foreach my $num (@nums){
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                                my ($addr,$base,$end,$name,$connect_id,$connect_socket,$connect_socket_num)=$soc->soc_get_plug($id,$plug,$num);
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                                        #intrrupt 
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                                        if((defined $connect_socket) && ($connect_socket eq 'interrupt_peripheral')){
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                                                add_text_to_string(\$system_h,"//intrrupt flag location\n");
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                                                add_text_to_string(\$system_h," #define $inst\_INT (1<<$connect_socket_num)\n") if(scalar (@nums)==1);
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                                                add_text_to_string(\$system_h," #define $inst\_$num\_INT    (1<<$connect_socket_num)\n") if(scalar (@nums)>1);
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                                        }
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                        }
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                }
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                my $hdr                 =$ip->ip_get($category,$module,"system_h");
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                #print "$hdr";
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                #   \$\{?IP(\b|\})
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                if(defined $hdr){
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                        $hdr=replace_golb_var($hdr,\%params);
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                        add_text_to_string(\$system_h,"$hdr\n");
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                }
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                # Write Software gen files
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                my @sw_file_gen = $ip->ip_get_list($category,$module,"gen_sw_files");
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                foreach my $file (@sw_file_gen){
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                        if(defined $file ){
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                                my ($path,$rename)=split('frename_sep_t',$file);
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                                $rename=replace_golb_var($rename,\%params);
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                                #read the file content
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                                my $content=read_file_cntent($path,$project_dir);
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                                $content=replace_golb_var($content,\%params);
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                                if(defined $rename){
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                                        open(FILE,  ">lib/verilog/tmp") || die "Can not open: $!";
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                                        print FILE $content;
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                                        close(FILE) || die "Error closing file: $!";
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                                        move ("$dir/lib/verilog/tmp","$sw_path/$rename");
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                                }
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                        }
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                }
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                # Write Hardware gen files
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                my @hw_file_gen = $ip->ip_get_list($category,$module,"gen_hw_files");
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                foreach my $file (@hw_file_gen){
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                        if(defined $file ){
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                                my ($path,$rename)=split('frename_sep_t',$file);
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                                $rename=replace_golb_var($rename,\%params);
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                                #read the file content
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                                my $content=read_file_cntent($path,$project_dir);
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                                $content=replace_golb_var($content,\%params);
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                                if(defined $rename){
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                                        open(FILE,  ">lib/verilog/tmp") || die "Can not open: $!";
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                                        print FILE $content;
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                                        close(FILE) || die "Error closing file: $!";
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                                        move ("$dir/lib/verilog/tmp","$hw_path/$rename");
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                                }
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                        }
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                }
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        }
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        add_text_to_string(\$system_h,"#endif\n");
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        my $name=$soc->object_get_attribute('soc_name');
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        open(FILE,  ">lib/verilog/$name.h") || die "Can not open: $!";
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                        print FILE $system_h;
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                        close(FILE) || die "Error closing file: $!";
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                        move ("$dir/lib/verilog/$name.h","$sw_path/");
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}
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