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[/] [an-fpga-implementation-of-low-latency-noc-based-mpsoc/] [trunk/] [mpsoc/] [rtl/] [src_modelsim/] [multicast_injector.sv] - Blame information for rev 54

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`timescale  1ns/1ps
/****************************
 * This module can inject and eject packets from the NoC.
 * It can be used in simulation for injecting real application traces to the NoC
 * *************************/
 
 
module multicast_injector
                import pronoc_pkg::*;
        (
                //general
                current_e_addr,
                reset,
                clk,
                //noc port
                chan_in,
                chan_out,
                //control interafce
                pck_injct_in,
                pck_injct_out
        );
 
        //general
        input reset,clk;
        input [EAw-1 :0 ] current_e_addr;
 
        // the destination endpoint address
        //NoC interface
        input   smartflit_chanel_t      chan_in;
        output  smartflit_chanel_t      chan_out;
        //control interafce
 
        input   pck_injct_t pck_injct_in;
        output  pck_injct_t pck_injct_out;
 
 
        wire  [RAw-1 :0 ] current_r_addr;
 
        wire  [DSTPw-1 : 0 ] destport;
        reg flit_wr;
 
 
 
 
 
 
        assign current_r_addr = chan_in.ctrl_chanel.neighbors_r_addr;
 
 
 
        /*
        conventional_routing #(
                .TOPOLOGY(TOPOLOGY),
                .ROUTE_NAME(ROUTE_NAME),
                .ROUTE_TYPE(ROUTE_TYPE),
                .T1(T1),
                .T2(T2),
                .T3(T3),
                .RAw(RAw),
                .EAw(EAw),
                .DSTPw(DSTPw),
                .LOCATED_IN_NI(1)
        )
        routing_module
        (
                .reset(reset),
                .clk(clk),
                .current_r_addr(current_r_addr),
                .dest_e_addr(pck_injct_in.endp_addr),
                .src_e_addr(current_e_addr),
                .destport(destport)
        );
 
*/
 
assign destport = 7;
 
 
        localparam
                HDR_BYTE_NUM =  HDR_MAX_DATw / 8, // = HDR_MAX_DATw / (8 - HDR_MAX_DATw %8)
                HDR_DATA_w_tmp   =  HDR_BYTE_NUM * 8,
                HDR_DATA_w = (PCK_INJ_Dw < HDR_DATA_w_tmp)? PCK_INJ_Dw : HDR_DATA_w_tmp;
 
        wire [HDR_DATA_w-1 : 0] hdr_data_in = pck_injct_in.data [HDR_DATA_w-1 : 0];
        wire [Fw-1 : 0] hdr_flit_out;
 
        header_flit_generator #(
                .DATA_w(HDR_DATA_w)
        )
        the_header_flit_generator
        (
                .flit_out                       (hdr_flit_out),
                .vc_num_in                      (pck_injct_in.vc),
                .class_in                       (pck_injct_in.class_num),
                .dest_e_addr_in         (pck_injct_in.endp_addr),
                .src_e_addr_in          (current_e_addr),
                .weight_in                      (pck_injct_in.init_weight),
                .destport_in            (destport),
                .data_in                        (hdr_data_in),
                .be_in({BEw{1'b1}} )// Be is not used in simulation as we dont sent real data
        );
 
 
        localparam
                REMAIN_DATw =  PCK_INJ_Dw - HDR_DATA_w,
                REMAIN_DAT_FLIT_I = (REMAIN_DATw / Fpay),
                REMAIN_DAT_FLIT_F = (REMAIN_DATw % Fpay == 0)? 0 : 1,
                REMAIN_DAT_FLIT   = REMAIN_DAT_FLIT_I + REMAIN_DAT_FLIT_F,
                CNTw = log2(REMAIN_DAT_FLIT),
                MIN_PCK_SIZ = REMAIN_DAT_FLIT +1;
 
 
        reg [PCK_SIZw-1             :   0]  counter, counter_next;
        reg [CNTw-1                 :   0]  counter2,counter2_next;
        reg tail,head;
 
        wire [Fpay -1 : 0]  remain_dat [REMAIN_DAT_FLIT -1 : 0];
        wire [Fpay-1 : 0] dataIn =  remain_dat[counter2];
        enum {HEADER, BODY,TAIL} flit_type,flit_type_next;
 
 
 
        wire [V-1 : 0]   wr_vc_send = (flit_wr)?   pck_injct_in.vc : {V{1'b0}};
        wire [V-1 : 0]   vc_fifo_full;
 
 
        wire noc_ready;
 
        localparam
                LAST_TMP =PCK_INJ_Dw -  (Fpay*REMAIN_DAT_FLIT_I)-HDR_DATA_w,
                LASTw=(LAST_TMP==0)? Fpay : LAST_TMP;
        genvar i;
        generate
                for(i=0; i
                        assign remain_dat [i] = pck_injct_in.data [Fpay*(i+1)+HDR_DATA_w-1   : (Fpay*i)+HDR_DATA_w];
                end
                if(REMAIN_DAT_FLIT_F ) begin
 
                        assign remain_dat [REMAIN_DAT_FLIT_I][LASTw-1 : 0] = pck_injct_in.data [PCK_INJ_Dw-1   : (Fpay*REMAIN_DAT_FLIT_I)+HDR_DATA_w];
                end
        endgenerate
 
 
 
 
 
                one_hot_mux #(
                        .IN_WIDTH   (V ),
                        .SEL_WIDTH  (V ),
                        .OUT_WIDTH  (1 )
                        ) one_hot_mux1 (
                        .mux_in     (~ vc_fifo_full    ),
                        .mux_out    (noc_ready   ),
                        .sel        (pck_injct_in.vc       ));
 
 
 
 
                always @ (*) begin
                        counter_next = counter;
                        counter2_next =counter2;
                        flit_type_next =flit_type;
                        tail=1'b0;
                        head=1'b0;
                        flit_wr=0;
                        if(noc_ready)begin
                                case(flit_type)
                                        HEADER:begin
                                                if(pck_injct_in.pck_wr)begin
                                                        flit_wr=1;
                                                        counter_next = pck_injct_in.size-1;
                                                        counter2_next=0;
                                                        head=1'b1;
                                                        if(pck_injct_in.size == 1)begin
                                                                tail=1'b1;
                                                        end else if (pck_injct_in.size == 2) begin
                                                                flit_type_next = TAIL;
                                                        end else begin
                                                                flit_type_next = BODY;
                                                        end
                                                end
                                        end
                                        BODY: begin
                                                flit_wr=1;
                                                counter_next = counter -1'b1;
                                                counter2_next =counter2 +1'b1;
                                                if(counter == 2) begin
                                                        flit_type_next = TAIL;
                                                end
                                        end
                                        TAIL: begin
                                                flit_type_next = HEADER;
                                                flit_wr=1;
                                                tail=1'b1;
                                        end
                                endcase
 
                        end
                end
                reg [V-1 : 0] credit_o;
 
                always @ (posedge clk) begin
                        if(reset) begin
                                flit_type<=HEADER;
                                counter<=0;
                                counter2<=0;
                                credit_o<={V{1'b0}};
                        end else begin
                                flit_type<=flit_type_next;
                                counter<=counter_next;
                                counter2<=counter2_next;
                                if (chan_in.flit_chanel.flit_wr) credit_o<=  chan_in.flit_chanel.flit.vc;
                                else credit_o<={V{1'b0}};
                        end
                end
 
 
 
 
 
        injector_ovc_status #(
                .V(V),
                .B(LB),
                .CRDTw(CRDTw)
        )
        the_ovc_status
        (
                .credit_init_val_in ( chan_in.ctrl_chanel.credit_init_val),
                .wr_in(wr_vc_send),
                .credit_in(chan_in.flit_chanel.credit),
                .full_vc(vc_fifo_full),
                .nearly_full_vc( ),
                .empty_vc( ),
                .clk(clk),
                .reset(reset)
        );
 
 
 
 
 
 
 
        wire [HDR_DATA_w-1 : 0] hdr_data_o;
        hdr_flit_t hdr_flit_i;
 
        header_flit_info
        #(
                .DATA_w         (HDR_DATA_w       )
        ) extractor (
                .flit(chan_in.flit_chanel.flit),
                .hdr_flit(hdr_flit_i),
                .data_o(hdr_data_o)
        );
 
        wire [PCK_INJ_Dw-1 : 0]  pck_data_o [V-1 : 0];
        reg  [Fpay-1 : 0] pck_data_o_gen [V-1 : 0][REMAIN_DAT_FLIT : 0];
 
        genvar k;
 
        reg [PCK_SIZw-1 : 0] rsv_counter [V-1 : 0];
        reg [EAw-1 : 0] sender_endp_addr_reg [V-1 : 0];
        logic [15:0] h2t_counter [V-1 : 0];
        logic [15:0] h2t_counter_next [V-1 : 0];
 
 
 
        //synthesis translate_off
        wire [NEw-1 : 0] current_id;
        wire [NEw-1 : 0] sendor_id;
        endp_addr_decoder #( .TOPOLOGY(TOPOLOGY), .T1(T1), .T2(T2), .T3(T3), .EAw(EAw),  .NE(NE)) encode1 ( .id(current_id), .code(current_e_addr));
        endp_addr_decoder #( .TOPOLOGY(TOPOLOGY), .T1(T1), .T2(T2), .T3(T3), .EAw(EAw),  .NE(NE)) encode2 ( .id(sendor_id), .code(pck_injct_out.endp_addr[EAw-1 : 0]));
        //synthesis translate_on
 
 
        generate
                for(i=0; i
                        always@(*) begin
                                h2t_counter_next[i]=h2t_counter[i]+1'b1;
                                if(chan_in.flit_chanel.flit.vc[i] & chan_in.flit_chanel.flit_wr & chan_in.flit_chanel.flit.hdr_flag)begin
                                                        h2t_counter_next[i]= 16'd0; // reset once header flit is received
                                end//hdr flit wr
                        end//always
 
 
 
 
                        always_ff @(posedge clk or posedge reset) begin
                                if (reset)  begin
                                        rsv_counter[i]<= {PCK_SIZw{1'b0}};
                                        h2t_counter[i]<= 16'd0;
                                        sender_endp_addr_reg [i]<= {EAw{1'b0}};
                                end else begin
                                        h2t_counter[i]<=h2t_counter_next[i];
                                        if(chan_in.flit_chanel.flit.vc[i] & chan_in.flit_chanel.flit_wr ) begin
                                                if(chan_in.flit_chanel.flit.hdr_flag)begin
                                                        rsv_counter[i]<= {{(PCK_SIZw-1){1'b0}}, 1'b1};
                                                        sender_endp_addr_reg [i]<= hdr_flit_i.src_e_addr;
                                                        //synthesis translate_off
                                                        if(hdr_flit_i.dest_e_addr != current_e_addr) begin
                                                                $display("%t: ERROR: packet destination address %d does not match reciver endp address %d. %m",$time,hdr_flit_i.dest_e_addr , current_e_addr );
                                                                $finish;
                                                        end//if hdr_flit_i
                                                        //synthesis translate_on
                                                end //if hdr_flag
                                                else rsv_counter[i]<= rsv_counter[i]+1'b1;
                                        end//flit wr
                                end//reset
                        end//always
 
 
 
 
                        for (k=0;k< REMAIN_DAT_FLIT+1;k++)begin : K_
 
                                always_ff @(posedge clk or posedge reset) begin
                                        if (reset)  begin
                                                pck_data_o_gen [i][k] <= {Fpay{1'b0}};
 
                                        end else begin
                                                if(chan_in.flit_chanel.flit.vc[i] & chan_in.flit_chanel.flit_wr ) begin
                                                        if (chan_in.flit_chanel.flit.hdr_flag )begin
                                                                if ( k ==0 ) pck_data_o_gen [i][k][HDR_DATA_w-1 : 0] <= hdr_data_o;
                                                        end
                                                        else begin
                                                                if (rsv_counter[i] == k ) pck_data_o_gen [i][k] <= chan_in.flit_chanel.flit.payload;
 
                                                        end // else
                                                end //if
                                        end //else
                                end// always
 
                                        if   (k == 0 ) assign pck_data_o [i][HDR_DATA_w-1 : 0] = pck_data_o_gen [i][0][HDR_DATA_w-1 : 0];
                                        else if (k == REMAIN_DAT_FLIT) assign pck_data_o [i][PCK_INJ_Dw-1 :    (k-1)*Fpay+ HDR_DATA_w] = pck_data_o_gen [i][k][LASTw-1: 0];
                                        else assign pck_data_o [i][(k)*Fpay+HDR_DATA_w -1 : (k-1)*Fpay+ HDR_DATA_w] = pck_data_o_gen [i][k];
 
                        end //for k
 
 
                        //synthesis translate_off
                        always @(posedge clk) begin
                                if((pck_injct_out.ready[i] == 1'b0 ) & pck_injct_in.vc[i] & pck_injct_in.pck_wr )begin
                                        $display("%t: ERROR: a packet injection request is recived in core(%d), vc (%d) while packet injectore was not ready. %m",$time,current_id,i);
                                        $finish;
                                end
 
                        end
                        //synthesis translate_on
 
 
 
 
                end//for i
        endgenerate
 
        wire [V-1 : 0] vc_reg;
        wire tail_flag_reg, hdr_flag_reg;
 
 
        pronoc_register #(.W(V))   register1 (.in(chan_in.flit_chanel.flit.vc),        .reset  (reset ), .clk (clk),.out(vc_reg));
        pronoc_register #(.W(1))   register2 (.in(chan_in.flit_chanel.flit.hdr_flag),   .reset  (reset ), .clk (clk),.out(hdr_flag_reg));
        pronoc_register #(.W(1))   register3 (.in(chan_in.flit_chanel.flit.tail_flag & chan_in.flit_chanel.flit_wr ),.reset  (reset ), .clk (clk),.out(tail_flag_reg));
 
        wire [Vw-1 : 0] vc_bin;
 
        one_hot_to_bin #(
                .ONE_HOT_WIDTH  (V),
                .BIN_WIDTH      (Vw )
        ) one_hot_to_bin (
                .one_hot_code   (vc_reg  ),
                .bin_code       (vc_bin      )
        );
 
 
        assign pck_injct_out.data  =  pck_data_o[vc_bin];
        assign pck_injct_out.size  =  rsv_counter[vc_bin];
        assign pck_injct_out.h2t_delay = h2t_counter[vc_bin];
        assign pck_injct_out.ready = (flit_type == HEADER)?  ~vc_fifo_full : {V{1'b0}};
        assign pck_injct_out.endp_addr =  sender_endp_addr_reg[vc_bin];
        assign pck_injct_out.vc = vc_reg;
        assign pck_injct_out.pck_wr = tail_flag_reg;
 
        assign chan_out.flit_chanel.flit.hdr_flag =head;
        assign chan_out.flit_chanel.flit.tail_flag=tail;
        assign chan_out.flit_chanel.flit.vc=pck_injct_in.vc;
        assign chan_out.flit_chanel.flit_wr=flit_wr;
 
        assign chan_out.flit_chanel.flit.payload = (flit_type== HEADER)? hdr_flit_out[Fpay-1 : 0] : dataIn;
        assign chan_out.smart_chanel = {SMART_CHANEL_w{1'b0}};
        assign chan_out.flit_chanel.congestion = {CONGw{1'b0}};
        assign chan_out.flit_chanel.credit= credit_o;
        assign chan_out.ctrl_chanel.credit_init_val= LB;
        assign chan_out.ctrl_chanel.endp_port =1'b1;
 
 
        distance_gen #(
                        .TOPOLOGY(TOPOLOGY),
                        .T1(T1),
                        .T2(T2),
                        .T3(T3),
                        .EAw(EAw),
                        .DISTw(DISTw)
                )
                the_distance_gen
                (
                        .src_e_addr(sender_endp_addr_reg[vc_bin]),
                        .dest_e_addr(current_e_addr),
                        .distance(pck_injct_out.distance)
                );
 
 
 
 
 
 
        //synthesis translate_off
        //`define MONITOR_RSV_DAT
 
 
 
        always @(posedge clk) begin
                if((pck_injct_in.vc == {V{1'b0}} ) & pck_injct_in.pck_wr )begin
                        $display("%t: ERROR: a packet injection request is recived while vc is not set. %m",$time);
                        $finish;
                end
                if(pck_injct_in.pck_wr && (pck_injct_in.size
                        $display("%t: ERROR: requested %d flit packet size is smaller than minimum %d flits to send %d bits of data. %m",$time,pck_injct_in.size,MIN_PCK_SIZ, PCK_INJ_Dw );
                        $finish;
                end
 
                `ifdef MONITOR_RSV_DAT
 
 
                if(pck_injct_in.pck_wr) begin
                        $display ("pck_inj(%d) send a packet:  size=%d, data=%h, v=%h",current_id,
                                        pck_injct_in.size, pck_injct_in.data,pck_injct_in.vc);
                end
 
                if(pck_injct_out.pck_wr) begin
                        $display ("pck_inj(%d) got a packet: source=%d, size=%d, data=%h",current_id,
                                        sendor_id,pck_injct_out.size,pck_injct_out.data);
                end
 
 
                `endif
 
        end
 
 
        //synthesis translate_on
 
 
 
 
 
endmodule
 
 
 
 
/******************
 *   ovc_status
 *******************/
 
module injector_ovc_status #(
                parameter V     =   4,
                parameter B =   16,
                parameter CRDTw =4
                )
                (
 
                input   [V-1 : 0] [CRDTw-1 : 0 ] credit_init_val_in,
                input   [V-1            :0] wr_in,
                input   [V-1            :0] credit_in,
                output  [V-1            :0] full_vc,
                output  [V-1            :0] nearly_full_vc,
                output  [V-1            :0] empty_vc,
                input                       clk,
                input                       reset
                );
 
 
        function integer log2;
                input integer number; begin
                        log2=(number <=1) ? 1: 0;
                        while(2**log2
                                log2=log2+1;
                        end
                end
        endfunction // log2
 
 
        localparam  DEPTH_WIDTH =   log2(B+1);
 
 
        reg  [DEPTH_WIDTH-1 : 0] credit    [V-1 : 0];
        wire  [V-1 : 0] cand_vc_next;
 
 
        genvar i;
        generate
                for(i=0;i
                        `ifdef SYNC_RESET_MODE
                                always @ (posedge clk )begin
                                `else
                                        always @ (posedge clk or posedge reset)begin
                                        `endif
                                        if(reset)begin
                                                credit[i]<= credit_init_val_in[i][DEPTH_WIDTH-1:0];
                                        end else begin
                                                if(  wr_in[i]  && ~credit_in[i])   credit[i] <= credit[i]-1'b1;
                                                if( ~wr_in[i]  &&  credit_in[i])   credit[i] <= credit[i]+1'b1;
                                        end //reset
                                end//always
 
                                assign  full_vc[i]   = (credit[i] == {DEPTH_WIDTH{1'b0}});
                                assign  nearly_full_vc[i]=  (credit[i] == 1) |  full_vc[i];
                                assign  empty_vc[i]  = (credit[i] == credit_init_val_in[i][DEPTH_WIDTH-1:0]);
                        end//for
                        endgenerate
endmodule
 
 
 
 
/**************************************
 *
 *
 * ***********************************/
 
 
 
module packet_injector_verilator
import pronoc_pkg::*;
(
        //general
        current_e_addr,
        reset,
        clk,
        //noc port
        chan_in,
        chan_out,
        //control interafce
        pck_injct_in_data,
        pck_injct_in_size,
        pck_injct_in_endp_addr,
        pck_injct_in_class_num,
        pck_injct_in_init_weight,
        pck_injct_in_vc,
        pck_injct_in_pck_wr,
        pck_injct_in_ready,
 
        pck_injct_out_data,
        pck_injct_out_size,
        pck_injct_out_endp_addr,
        pck_injct_out_class_num,
        pck_injct_out_init_weight,
        pck_injct_out_vc,
        pck_injct_out_pck_wr,
        pck_injct_out_ready,
        pck_injct_out_distance,
        pck_injct_out_h2t_delay,
        min_pck_size
 
 
);
 
 
//general
input reset,clk;
input [EAw-1 :0 ] current_e_addr;
 
// the destination endpoint address
//NoC interface
input   smartflit_chanel_t      chan_in;
output  smartflit_chanel_t      chan_out;
//control interafce
 
 
 input [PCK_INJ_Dw-1 : 0] pck_injct_in_data;
 input [PCK_SIZw-1   : 0] pck_injct_in_size;
 input [EAw-1        : 0] pck_injct_in_endp_addr;
 input [Cw-1         : 0] pck_injct_in_class_num;
 input [WEIGHTw-1    : 0] pck_injct_in_init_weight;
 input [V-1          : 0] pck_injct_in_vc;
 input                    pck_injct_in_pck_wr;
 input [V-1          : 0] pck_injct_in_ready;
 
 output [PCK_INJ_Dw-1 : 0] pck_injct_out_data;
 output [PCK_SIZw-1   : 0] pck_injct_out_size;
 output [EAw-1        : 0] pck_injct_out_endp_addr;
 output [Cw-1         : 0] pck_injct_out_class_num;
 output [WEIGHTw-1    : 0] pck_injct_out_init_weight;
 output [V-1          : 0] pck_injct_out_vc;
 output                    pck_injct_out_pck_wr;
 output [V-1          : 0] pck_injct_out_ready;
 output [DISTw-1          : 0] pck_injct_out_distance;
 output [15                       : 0] pck_injct_out_h2t_delay;
 output [4                        : 0] min_pck_size;
 
 pck_injct_t pck_injct_in;
 pck_injct_t pck_injct_out;
 
 assign pck_injct_in.data         = pck_injct_in_data;
 assign pck_injct_in.size         = pck_injct_in_size;
 assign pck_injct_in.endp_addr    = pck_injct_in_endp_addr;
 assign pck_injct_in.class_num    = pck_injct_in_class_num;
 assign pck_injct_in.init_weight  = pck_injct_in_init_weight;
 assign pck_injct_in.vc           = pck_injct_in_vc;
 assign pck_injct_in.pck_wr       = pck_injct_in_pck_wr;
 assign pck_injct_in.ready        = pck_injct_in_ready;
 
 assign pck_injct_out_data        = pck_injct_out.data;
 assign pck_injct_out_size        = pck_injct_out.size;
 assign pck_injct_out_endp_addr   = pck_injct_out.endp_addr;
 assign pck_injct_out_class_num   = pck_injct_out.class_num;
 assign pck_injct_out_init_weight = pck_injct_out.init_weight;
 assign pck_injct_out_vc          = pck_injct_out.vc;
 assign pck_injct_out_pck_wr      = pck_injct_out.pck_wr;
 assign pck_injct_out_ready       = pck_injct_out.ready;
 assign pck_injct_out_distance    = pck_injct_out.distance;
 assign pck_injct_out_h2t_delay   = pck_injct_out.h2t_delay;
 
 packet_injector injector (
        .current_e_addr  (current_e_addr ),
        .reset           (reset          ),
        .clk             (clk            ),
        .chan_in         (chan_in        ),
        .chan_out        (chan_out       ),
        .pck_injct_in    (pck_injct_in   ),
        .pck_injct_out   (pck_injct_out  ));
 
 
 localparam
        HDR_BYTE_NUM =  HDR_MAX_DATw / 8, // = HDR_MAX_DATw / (8 - HDR_MAX_DATw %8)
        HDR_DATA_w_tmp   =  HDR_BYTE_NUM * 8,
        HDR_DATA_w = (PCK_INJ_Dw < HDR_DATA_w_tmp)? PCK_INJ_Dw : HDR_DATA_w_tmp,
        REMAIN_DATw =  PCK_INJ_Dw - HDR_DATA_w,
        REMAIN_DAT_FLIT_I = (REMAIN_DATw / Fpay),
        REMAIN_DAT_FLIT_F = (REMAIN_DATw % Fpay == 0)? 0 : 1,
        REMAIN_DAT_FLIT   = REMAIN_DAT_FLIT_I + REMAIN_DAT_FLIT_F,
        CNTw = log2(REMAIN_DAT_FLIT),
        MIN_PCK_SIZ = REMAIN_DAT_FLIT +1;
 
 assign  min_pck_size = MIN_PCK_SIZ[4:0];
 
 
// `ifdef VERILATOR
//      logic  endp_is_active   /*verilator public_flat_rd*/ ;
//
//      always @ (*) begin
//              endp_is_active  = 1'b0;
//              if (chan_out.flit_chanel.flit_wr) endp_is_active=1'b1;
//              if (chan_out.flit_chanel.credit > {V{1'b0}} ) endp_is_active=1'b1;
//              if (chan_out.smart_chanel.requests > {SMART_NUM{1'b0}} ) endp_is_active=1'b1;
//      end
// `endif
 
 
endmodule

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[/] [an-fpga-implementation-of-low-latency-noc-based-mpsoc/] [trunk/] [mpsoc/] [rtl/] [src_modelsim/] [multicast_injector.sv] - Blame information for rev 54

Line No.	Rev	Author	Line
1	54	alirezamon	`timescale 1ns/1ps
2			`/****************************`
3			`* This module can inject and eject packets from the NoC.`
4			`* It can be used in simulation for injecting real application traces to the NoC`
5			`* *************************/`
6
7
8			`module multicast_injector`
9			`import pronoc_pkg::*;`
10			`(`
11			`//general`
12			`current_e_addr,`
13			`reset,`
14			`clk,`
15			`//noc port`
16			`chan_in,`
17			`chan_out,`
18			`//control interafce`
19			`pck_injct_in,`
20			`pck_injct_out`
21			`);`
22
23			`//general`
24			`input reset,clk;`
25			`input [EAw-1 :0 ] current_e_addr;`
26
27			`// the destination endpoint address`
28			`//NoC interface`
29			`input smartflit_chanel_t chan_in;`
30			`output smartflit_chanel_t chan_out;`
31			`//control interafce`
32
33			`input pck_injct_t pck_injct_in;`
34			`output pck_injct_t pck_injct_out;`
35
36
37			`wire [RAw-1 :0 ] current_r_addr;`
38
39			`wire [DSTPw-1 : 0 ] destport;`
40			`reg flit_wr;`
41
42
43
44
45
46
47			`assign current_r_addr = chan_in.ctrl_chanel.neighbors_r_addr;`
48
49
50
51			`/*`
52			`conventional_routing #(`
53			`.TOPOLOGY(TOPOLOGY),`
54			`.ROUTE_NAME(ROUTE_NAME),`
55			`.ROUTE_TYPE(ROUTE_TYPE),`
56			`.T1(T1),`
57			`.T2(T2),`
58			`.T3(T3),`
59			`.RAw(RAw),`
60			`.EAw(EAw),`
61			`.DSTPw(DSTPw),`
62			`.LOCATED_IN_NI(1)`
63			`)`
64			`routing_module`
65			`(`
66			`.reset(reset),`
67			`.clk(clk),`
68			`.current_r_addr(current_r_addr),`
69			`.dest_e_addr(pck_injct_in.endp_addr),`
70			`.src_e_addr(current_e_addr),`
71			`.destport(destport)`
72			`);`
73
74			`*/`
75
76			`assign destport = 7;`
77
78
79			`localparam`
80			`HDR_BYTE_NUM = HDR_MAX_DATw / 8, // = HDR_MAX_DATw / (8 - HDR_MAX_DATw %8)`
81			`HDR_DATA_w_tmp = HDR_BYTE_NUM * 8,`
82			`HDR_DATA_w = (PCK_INJ_Dw < HDR_DATA_w_tmp)? PCK_INJ_Dw : HDR_DATA_w_tmp;`
83
84			`wire [HDR_DATA_w-1 : 0] hdr_data_in = pck_injct_in.data [HDR_DATA_w-1 : 0];`
85			`wire [Fw-1 : 0] hdr_flit_out;`
86
87			`header_flit_generator #(`
88			`.DATA_w(HDR_DATA_w)`
89			`)`
90			`the_header_flit_generator`
91			`(`
92			`.flit_out (hdr_flit_out),`
93			`.vc_num_in (pck_injct_in.vc),`
94			`.class_in (pck_injct_in.class_num),`
95			`.dest_e_addr_in (pck_injct_in.endp_addr),`
96			`.src_e_addr_in (current_e_addr),`
97			`.weight_in (pck_injct_in.init_weight),`
98			`.destport_in (destport),`
99			`.data_in (hdr_data_in),`
100			`.be_in({BEw{1'b1}} )// Be is not used in simulation as we dont sent real data`
101			`);`
102
103
104			`localparam`
105			`REMAIN_DATw = PCK_INJ_Dw - HDR_DATA_w,`
106			`REMAIN_DAT_FLIT_I = (REMAIN_DATw / Fpay),`
107			`REMAIN_DAT_FLIT_F = (REMAIN_DATw % Fpay == 0)? 0 : 1,`
108			`REMAIN_DAT_FLIT = REMAIN_DAT_FLIT_I + REMAIN_DAT_FLIT_F,`
109			`CNTw = log2(REMAIN_DAT_FLIT),`
110			`MIN_PCK_SIZ = REMAIN_DAT_FLIT +1;`
111
112
113			`reg [PCK_SIZw-1 : 0] counter, counter_next;`
114			`reg [CNTw-1 : 0] counter2,counter2_next;`
115			`reg tail,head;`
116
117			`wire [Fpay -1 : 0] remain_dat [REMAIN_DAT_FLIT -1 : 0];`
118			`wire [Fpay-1 : 0] dataIn = remain_dat[counter2];`
119			`enum {HEADER, BODY,TAIL} flit_type,flit_type_next;`
120
121
122
123			`wire [V-1 : 0] wr_vc_send = (flit_wr)? pck_injct_in.vc : {V{1'b0}};`
124			`wire [V-1 : 0] vc_fifo_full;`
125
126
127			`wire noc_ready;`
128
129			`localparam`
130			`LAST_TMP =PCK_INJ_Dw - (Fpay*REMAIN_DAT_FLIT_I)-HDR_DATA_w,`
131			`LASTw=(LAST_TMP==0)? Fpay : LAST_TMP;`
132			`genvar i;`
133			`generate`
134			`for(i=0; i`
135			`assign remain_dat [i] = pck_injct_in.data [Fpay(i+1)+HDR_DATA_w-1 : (Fpayi)+HDR_DATA_w];`
136			`end`
137			`if(REMAIN_DAT_FLIT_F ) begin`
138
139			`assign remain_dat [REMAIN_DAT_FLIT_I][LASTw-1 : 0] = pck_injct_in.data [PCK_INJ_Dw-1 : (Fpay*REMAIN_DAT_FLIT_I)+HDR_DATA_w];`
140			`end`
141			`endgenerate`
142
143
144
145
146
147			`one_hot_mux #(`
148			`.IN_WIDTH (V ),`
149			`.SEL_WIDTH (V ),`
150			`.OUT_WIDTH (1 )`
151			`) one_hot_mux1 (`
152			`.mux_in (~ vc_fifo_full ),`
153			`.mux_out (noc_ready ),`
154			`.sel (pck_injct_in.vc ));`
155
156
157
158
159			`always @ (*) begin`
160			`counter_next = counter;`
161			`counter2_next =counter2;`
162			`flit_type_next =flit_type;`
163			`tail=1'b0;`
164			`head=1'b0;`
165			`flit_wr=0;`
166			`if(noc_ready)begin`
167			`case(flit_type)`
168			`HEADER:begin`
169			`if(pck_injct_in.pck_wr)begin`
170			`flit_wr=1;`
171			`counter_next = pck_injct_in.size-1;`
172			`counter2_next=0;`
173			`head=1'b1;`
174			`if(pck_injct_in.size == 1)begin`
175			`tail=1'b1;`
176			`end else if (pck_injct_in.size == 2) begin`
177			`flit_type_next = TAIL;`
178			`end else begin`
179			`flit_type_next = BODY;`
180			`end`
181			`end`
182			`end`
183			`BODY: begin`
184			`flit_wr=1;`
185			`counter_next = counter -1'b1;`
186			`counter2_next =counter2 +1'b1;`
187			`if(counter == 2) begin`
188			`flit_type_next = TAIL;`
189			`end`
190			`end`
191			`TAIL: begin`
192			`flit_type_next = HEADER;`
193			`flit_wr=1;`
194			`tail=1'b1;`
195			`end`
196			`endcase`
197
198			`end`
199			`end`
200			`reg [V-1 : 0] credit_o;`
201
202			`always @ (posedge clk) begin`
203			`if(reset) begin`
204			`flit_type<=HEADER;`
205			`counter<=0;`
206			`counter2<=0;`
207			`credit_o<={V{1'b0}};`
208			`end else begin`
209			`flit_type<=flit_type_next;`
210			`counter<=counter_next;`
211			`counter2<=counter2_next;`
212			`if (chan_in.flit_chanel.flit_wr) credit_o<= chan_in.flit_chanel.flit.vc;`
213			`else credit_o<={V{1'b0}};`
214			`end`
215			`end`
216
217
218
219
220
221			`injector_ovc_status #(`
222			`.V(V),`
223			`.B(LB),`
224			`.CRDTw(CRDTw)`
225			`)`
226			`the_ovc_status`
227			`(`
228			`.credit_init_val_in ( chan_in.ctrl_chanel.credit_init_val),`
229			`.wr_in(wr_vc_send),`
230			`.credit_in(chan_in.flit_chanel.credit),`
231			`.full_vc(vc_fifo_full),`
232			`.nearly_full_vc( ),`
233			`.empty_vc( ),`
234			`.clk(clk),`
235			`.reset(reset)`
236			`);`
237
238
239
240
241
242
243
244			`wire [HDR_DATA_w-1 : 0] hdr_data_o;`
245			`hdr_flit_t hdr_flit_i;`
246
247			`header_flit_info`
248			`#(`
249			`.DATA_w (HDR_DATA_w )`
250			`) extractor (`
251			`.flit(chan_in.flit_chanel.flit),`
252			`.hdr_flit(hdr_flit_i),`
253			`.data_o(hdr_data_o)`
254			`);`
255
256			`wire [PCK_INJ_Dw-1 : 0] pck_data_o [V-1 : 0];`
257			`reg [Fpay-1 : 0] pck_data_o_gen [V-1 : 0][REMAIN_DAT_FLIT : 0];`
258
259			`genvar k;`
260
261			`reg [PCK_SIZw-1 : 0] rsv_counter [V-1 : 0];`
262			`reg [EAw-1 : 0] sender_endp_addr_reg [V-1 : 0];`
263			`logic [15:0] h2t_counter [V-1 : 0];`
264			`logic [15:0] h2t_counter_next [V-1 : 0];`
265
266
267
268			`//synthesis translate_off`
269			`wire [NEw-1 : 0] current_id;`
270			`wire [NEw-1 : 0] sendor_id;`
271			`endp_addr_decoder #( .TOPOLOGY(TOPOLOGY), .T1(T1), .T2(T2), .T3(T3), .EAw(EAw), .NE(NE)) encode1 ( .id(current_id), .code(current_e_addr));`
272			`endp_addr_decoder #( .TOPOLOGY(TOPOLOGY), .T1(T1), .T2(T2), .T3(T3), .EAw(EAw), .NE(NE)) encode2 ( .id(sendor_id), .code(pck_injct_out.endp_addr[EAw-1 : 0]));`
273			`//synthesis translate_on`
274
275
276			`generate`
277			`for(i=0; i`
278			`always@(*) begin`
279			`h2t_counter_next[i]=h2t_counter[i]+1'b1;`
280			`if(chan_in.flit_chanel.flit.vc[i] & chan_in.flit_chanel.flit_wr & chan_in.flit_chanel.flit.hdr_flag)begin`
281			`h2t_counter_next[i]= 16'd0; // reset once header flit is received`
282			`end//hdr flit wr`
283			`end//always`
284
285
286
287
288			`always_ff @(posedge clk or posedge reset) begin`
289			`if (reset) begin`
290			`rsv_counter[i]<= {PCK_SIZw{1'b0}};`
291			`h2t_counter[i]<= 16'd0;`
292			`sender_endp_addr_reg [i]<= {EAw{1'b0}};`
293			`end else begin`
294			`h2t_counter[i]<=h2t_counter_next[i];`
295			`if(chan_in.flit_chanel.flit.vc[i] & chan_in.flit_chanel.flit_wr ) begin`
296			`if(chan_in.flit_chanel.flit.hdr_flag)begin`
297			`rsv_counter[i]<= {{(PCK_SIZw-1){1'b0}}, 1'b1};`
298			`sender_endp_addr_reg [i]<= hdr_flit_i.src_e_addr;`
299			`//synthesis translate_off`
300			`if(hdr_flit_i.dest_e_addr != current_e_addr) begin`
301			`$display("%t: ERROR: packet destination address %d does not match reciver endp address %d. %m",$time,hdr_flit_i.dest_e_addr , current_e_addr );`
302			`$finish;`
303			`end//if hdr_flit_i`
304			`//synthesis translate_on`
305			`end //if hdr_flag`
306			`else rsv_counter[i]<= rsv_counter[i]+1'b1;`
307			`end//flit wr`
308			`end//reset`
309			`end//always`
310
311
312
313
314			`for (k=0;k< REMAIN_DAT_FLIT+1;k++)begin : K_`
315
316			`always_ff @(posedge clk or posedge reset) begin`
317			`if (reset) begin`
318			`pck_data_o_gen [i][k] <= {Fpay{1'b0}};`
319
320			`end else begin`
321			`if(chan_in.flit_chanel.flit.vc[i] & chan_in.flit_chanel.flit_wr ) begin`
322			`if (chan_in.flit_chanel.flit.hdr_flag )begin`
323			`if ( k ==0 ) pck_data_o_gen [i][k][HDR_DATA_w-1 : 0] <= hdr_data_o;`
324			`end`
325			`else begin`
326			`if (rsv_counter[i] == k ) pck_data_o_gen [i][k] <= chan_in.flit_chanel.flit.payload;`
327
328			`end // else`
329			`end //if`
330			`end //else`
331			`end// always`
332
333			`if (k == 0 ) assign pck_data_o [i][HDR_DATA_w-1 : 0] = pck_data_o_gen [i][0][HDR_DATA_w-1 : 0];`
334			`else if (k == REMAIN_DAT_FLIT) assign pck_data_o [i][PCK_INJ_Dw-1 : (k-1)*Fpay+ HDR_DATA_w] = pck_data_o_gen [i][k][LASTw-1: 0];`
335			`else assign pck_data_o [i][(k)Fpay+HDR_DATA_w -1 : (k-1)Fpay+ HDR_DATA_w] = pck_data_o_gen [i][k];`
336
337			`end //for k`
338
339
340			`//synthesis translate_off`
341			`always @(posedge clk) begin`
342			`if((pck_injct_out.ready[i] == 1'b0 ) & pck_injct_in.vc[i] & pck_injct_in.pck_wr )begin`
343			`$display("%t: ERROR: a packet injection request is recived in core(%d), vc (%d) while packet injectore was not ready. %m",$time,current_id,i);`
344			`$finish;`
345			`end`
346
347			`end`
348			`//synthesis translate_on`
349
350
351
352
353			`end//for i`
354			`endgenerate`
355
356			`wire [V-1 : 0] vc_reg;`
357			`wire tail_flag_reg, hdr_flag_reg;`
358
359
360			`pronoc_register #(.W(V)) register1 (.in(chan_in.flit_chanel.flit.vc), .reset (reset ), .clk (clk),.out(vc_reg));`
361			`pronoc_register #(.W(1)) register2 (.in(chan_in.flit_chanel.flit.hdr_flag), .reset (reset ), .clk (clk),.out(hdr_flag_reg));`
362			`pronoc_register #(.W(1)) register3 (.in(chan_in.flit_chanel.flit.tail_flag & chan_in.flit_chanel.flit_wr ),.reset (reset ), .clk (clk),.out(tail_flag_reg));`
363
364			`wire [Vw-1 : 0] vc_bin;`
365
366			`one_hot_to_bin #(`
367			`.ONE_HOT_WIDTH (V),`
368			`.BIN_WIDTH (Vw )`
369			`) one_hot_to_bin (`
370			`.one_hot_code (vc_reg ),`
371			`.bin_code (vc_bin )`
372			`);`
373
374
375			`assign pck_injct_out.data = pck_data_o[vc_bin];`
376			`assign pck_injct_out.size = rsv_counter[vc_bin];`
377			`assign pck_injct_out.h2t_delay = h2t_counter[vc_bin];`
378			`assign pck_injct_out.ready = (flit_type == HEADER)? ~vc_fifo_full : {V{1'b0}};`
379			`assign pck_injct_out.endp_addr = sender_endp_addr_reg[vc_bin];`
380			`assign pck_injct_out.vc = vc_reg;`
381			`assign pck_injct_out.pck_wr = tail_flag_reg;`
382
383			`assign chan_out.flit_chanel.flit.hdr_flag =head;`
384			`assign chan_out.flit_chanel.flit.tail_flag=tail;`
385			`assign chan_out.flit_chanel.flit.vc=pck_injct_in.vc;`
386			`assign chan_out.flit_chanel.flit_wr=flit_wr;`
387
388			`assign chan_out.flit_chanel.flit.payload = (flit_type== HEADER)? hdr_flit_out[Fpay-1 : 0] : dataIn;`
389			`assign chan_out.smart_chanel = {SMART_CHANEL_w{1'b0}};`
390			`assign chan_out.flit_chanel.congestion = {CONGw{1'b0}};`
391			`assign chan_out.flit_chanel.credit= credit_o;`
392			`assign chan_out.ctrl_chanel.credit_init_val= LB;`
393			`assign chan_out.ctrl_chanel.endp_port =1'b1;`
394
395
396			`distance_gen #(`
397			`.TOPOLOGY(TOPOLOGY),`
398			`.T1(T1),`
399			`.T2(T2),`
400			`.T3(T3),`
401			`.EAw(EAw),`
402			`.DISTw(DISTw)`
403			`)`
404			`the_distance_gen`
405			`(`
406			`.src_e_addr(sender_endp_addr_reg[vc_bin]),`
407			`.dest_e_addr(current_e_addr),`
408			`.distance(pck_injct_out.distance)`
409			`);`
410
411
412
413
414
415
416			`//synthesis translate_off`
417			//`define MONITOR_RSV_DAT
418
419
420
421			`always @(posedge clk) begin`
422			`if((pck_injct_in.vc == {V{1'b0}} ) & pck_injct_in.pck_wr )begin`
423			`$display("%t: ERROR: a packet injection request is recived while vc is not set. %m",$time);`
424			`$finish;`
425			`end`
426			`if(pck_injct_in.pck_wr && (pck_injct_in.size`
427			`$display("%t: ERROR: requested %d flit packet size is smaller than minimum %d flits to send %d bits of data. %m",$time,pck_injct_in.size,MIN_PCK_SIZ, PCK_INJ_Dw );`
428			`$finish;`
429			`end`
430
431			`ifdef MONITOR_RSV_DAT
432
433
434			`if(pck_injct_in.pck_wr) begin`
435			`$display ("pck_inj(%d) send a packet: size=%d, data=%h, v=%h",current_id,`
436			`pck_injct_in.size, pck_injct_in.data,pck_injct_in.vc);`
437			`end`
438
439			`if(pck_injct_out.pck_wr) begin`
440			`$display ("pck_inj(%d) got a packet: source=%d, size=%d, data=%h",current_id,`
441			`sendor_id,pck_injct_out.size,pck_injct_out.data);`
442			`end`
443
444
445			`endif
446
447			`end`
448
449
450			`//synthesis translate_on`
451
452
453
454
455
456			`endmodule`
457
458
459
460
461			`/******************`
462			`* ovc_status`
463			`*******************/`
464
465			`module injector_ovc_status #(`
466			`parameter V = 4,`
467			`parameter B = 16,`
468			`parameter CRDTw =4`
469			`)`
470			`(`
471
472			`input [V-1 : 0] [CRDTw-1 : 0 ] credit_init_val_in,`
473			`input [V-1 :0] wr_in,`
474			`input [V-1 :0] credit_in,`
475			`output [V-1 :0] full_vc,`
476			`output [V-1 :0] nearly_full_vc,`
477			`output [V-1 :0] empty_vc,`
478			`input clk,`
479			`input reset`
480			`);`
481
482
483			`function integer log2;`
484			`input integer number; begin`
485			`log2=(number <=1) ? 1: 0;`
486			`while(2**log2`
487			`log2=log2+1;`
488			`end`
489			`end`
490			`endfunction // log2`
491
492
493			`localparam DEPTH_WIDTH = log2(B+1);`
494
495
496			`reg [DEPTH_WIDTH-1 : 0] credit [V-1 : 0];`
497			`wire [V-1 : 0] cand_vc_next;`
498
499
500			`genvar i;`
501			`generate`
502			`for(i=0;i`
503			`ifdef SYNC_RESET_MODE
504			`always @ (posedge clk )begin`
505			`else
506			`always @ (posedge clk or posedge reset)begin`
507			`endif
508			`if(reset)begin`
509			`credit[i]<= credit_init_val_in[i][DEPTH_WIDTH-1:0];`
510			`end else begin`
511			`if( wr_in[i] && ~credit_in[i]) credit[i] <= credit[i]-1'b1;`
512			`if( ~wr_in[i] && credit_in[i]) credit[i] <= credit[i]+1'b1;`
513			`end //reset`
514			`end//always`
515
516			`assign full_vc[i] = (credit[i] == {DEPTH_WIDTH{1'b0}});`
517			`assign nearly_full_vc[i]= (credit[i] == 1) \| full_vc[i];`
518			`assign empty_vc[i] = (credit[i] == credit_init_val_in[i][DEPTH_WIDTH-1:0]);`
519			`end//for`
520			`endgenerate`
521			`endmodule`
522
523
524
525
526			`/**************************************`
527			`*`
528			`*`
529			`* ***********************************/`
530
531
532
533			`module packet_injector_verilator`
534			`import pronoc_pkg::*;`
535			`(`
536			`//general`
537			`current_e_addr,`
538			`reset,`
539			`clk,`
540			`//noc port`
541			`chan_in,`
542			`chan_out,`
543			`//control interafce`
544			`pck_injct_in_data,`
545			`pck_injct_in_size,`
546			`pck_injct_in_endp_addr,`
547			`pck_injct_in_class_num,`
548			`pck_injct_in_init_weight,`
549			`pck_injct_in_vc,`
550			`pck_injct_in_pck_wr,`
551			`pck_injct_in_ready,`
552
553			`pck_injct_out_data,`
554			`pck_injct_out_size,`
555			`pck_injct_out_endp_addr,`
556			`pck_injct_out_class_num,`
557			`pck_injct_out_init_weight,`
558			`pck_injct_out_vc,`
559			`pck_injct_out_pck_wr,`
560			`pck_injct_out_ready,`
561			`pck_injct_out_distance,`
562			`pck_injct_out_h2t_delay,`
563			`min_pck_size`
564
565
566			`);`
567
568
569			`//general`
570			`input reset,clk;`
571			`input [EAw-1 :0 ] current_e_addr;`
572
573			`// the destination endpoint address`
574			`//NoC interface`
575			`input smartflit_chanel_t chan_in;`
576			`output smartflit_chanel_t chan_out;`
577			`//control interafce`
578
579
580			`input [PCK_INJ_Dw-1 : 0] pck_injct_in_data;`
581			`input [PCK_SIZw-1 : 0] pck_injct_in_size;`
582			`input [EAw-1 : 0] pck_injct_in_endp_addr;`
583			`input [Cw-1 : 0] pck_injct_in_class_num;`
584			`input [WEIGHTw-1 : 0] pck_injct_in_init_weight;`
585			`input [V-1 : 0] pck_injct_in_vc;`
586			`input pck_injct_in_pck_wr;`
587			`input [V-1 : 0] pck_injct_in_ready;`
588
589			`output [PCK_INJ_Dw-1 : 0] pck_injct_out_data;`
590			`output [PCK_SIZw-1 : 0] pck_injct_out_size;`
591			`output [EAw-1 : 0] pck_injct_out_endp_addr;`
592			`output [Cw-1 : 0] pck_injct_out_class_num;`
593			`output [WEIGHTw-1 : 0] pck_injct_out_init_weight;`
594			`output [V-1 : 0] pck_injct_out_vc;`
595			`output pck_injct_out_pck_wr;`
596			`output [V-1 : 0] pck_injct_out_ready;`
597			`output [DISTw-1 : 0] pck_injct_out_distance;`
598			`output [15 : 0] pck_injct_out_h2t_delay;`
599			`output [4 : 0] min_pck_size;`
600
601			`pck_injct_t pck_injct_in;`
602			`pck_injct_t pck_injct_out;`
603
604			`assign pck_injct_in.data = pck_injct_in_data;`
605			`assign pck_injct_in.size = pck_injct_in_size;`
606			`assign pck_injct_in.endp_addr = pck_injct_in_endp_addr;`
607			`assign pck_injct_in.class_num = pck_injct_in_class_num;`
608			`assign pck_injct_in.init_weight = pck_injct_in_init_weight;`
609			`assign pck_injct_in.vc = pck_injct_in_vc;`
610			`assign pck_injct_in.pck_wr = pck_injct_in_pck_wr;`
611			`assign pck_injct_in.ready = pck_injct_in_ready;`
612
613			`assign pck_injct_out_data = pck_injct_out.data;`
614			`assign pck_injct_out_size = pck_injct_out.size;`
615			`assign pck_injct_out_endp_addr = pck_injct_out.endp_addr;`
616			`assign pck_injct_out_class_num = pck_injct_out.class_num;`
617			`assign pck_injct_out_init_weight = pck_injct_out.init_weight;`
618			`assign pck_injct_out_vc = pck_injct_out.vc;`
619			`assign pck_injct_out_pck_wr = pck_injct_out.pck_wr;`
620			`assign pck_injct_out_ready = pck_injct_out.ready;`
621			`assign pck_injct_out_distance = pck_injct_out.distance;`
622			`assign pck_injct_out_h2t_delay = pck_injct_out.h2t_delay;`
623
624			`packet_injector injector (`
625			`.current_e_addr (current_e_addr ),`
626			`.reset (reset ),`
627			`.clk (clk ),`
628			`.chan_in (chan_in ),`
629			`.chan_out (chan_out ),`
630			`.pck_injct_in (pck_injct_in ),`
631			`.pck_injct_out (pck_injct_out ));`
632
633
634			`localparam`
635			`HDR_BYTE_NUM = HDR_MAX_DATw / 8, // = HDR_MAX_DATw / (8 - HDR_MAX_DATw %8)`
636			`HDR_DATA_w_tmp = HDR_BYTE_NUM * 8,`
637			`HDR_DATA_w = (PCK_INJ_Dw < HDR_DATA_w_tmp)? PCK_INJ_Dw : HDR_DATA_w_tmp,`
638			`REMAIN_DATw = PCK_INJ_Dw - HDR_DATA_w,`
639			`REMAIN_DAT_FLIT_I = (REMAIN_DATw / Fpay),`
640			`REMAIN_DAT_FLIT_F = (REMAIN_DATw % Fpay == 0)? 0 : 1,`
641			`REMAIN_DAT_FLIT = REMAIN_DAT_FLIT_I + REMAIN_DAT_FLIT_F,`
642			`CNTw = log2(REMAIN_DAT_FLIT),`
643			`MIN_PCK_SIZ = REMAIN_DAT_FLIT +1;`
644
645			`assign min_pck_size = MIN_PCK_SIZ[4:0];`
646
647
648			// `ifdef VERILATOR
649			`// logic endp_is_active /verilator public_flat_rd/ ;`
650			`//`
651			`// always @ (*) begin`
652			`// endp_is_active = 1'b0;`
653			`// if (chan_out.flit_chanel.flit_wr) endp_is_active=1'b1;`
654			`// if (chan_out.flit_chanel.credit > {V{1'b0}} ) endp_is_active=1'b1;`
655			`// if (chan_out.smart_chanel.requests > {SMART_NUM{1'b0}} ) endp_is_active=1'b1;`
656			`// end`
657			// `endif
658
659
660			`endmodule`