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[/] [an-fpga-implementation-of-low-latency-noc-based-mpsoc/] [trunk/] [mpsoc/] [rtl/] [src_noc/] [debug.v] - Blame information for rev 54

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`timescale 1ns / 1ps
 
/**************************************
* Module: debug
* Date:2019-04-01
* Author: alireza
*
* Description: this file contain modules which are used for error checking/debiging of the NoC.
***************************************/
 
//check if flits are recived in correct order in a VC
 
module check_flit_chanel_type_is_in_order #(
    parameter V=4,
    parameter PCK_TYPE = "SINGLE_FLIT",
    parameter MIN_PCK_SIZE=2
)(
    hdr_flg_in,
    flit_in_wr,
    tail_flg_in,
    vc_num_in,
    clk,
    reset
 
);
 
    input clk, reset;
    input hdr_flg_in, tail_flg_in, flit_in_wr;
    input [V-1 : 0] vc_num_in;
 
 
 
 
    wire [V-1 : 0] vc_num_hdr_wr, vc_num_tail_wr,vc_num_bdy_wr ;
    wire [V-1 : 0] hdr_passed;
    reg  [V-1 : 0] hdr_passed_next;
    wire [V-1 : 0] single_flit_pck;
 
    assign  vc_num_hdr_wr =(hdr_flg_in & flit_in_wr) ?    vc_num_in : 0;
    assign  vc_num_tail_wr =(tail_flg_in & flit_in_wr)?    vc_num_in : 0;
    assign  vc_num_bdy_wr =({hdr_flg_in,tail_flg_in} == 2'b00 && flit_in_wr)?    vc_num_in : 0;
    assign  single_flit_pck = vc_num_hdr_wr & vc_num_tail_wr;
    always @(*)begin
        hdr_passed_next = (hdr_passed | vc_num_hdr_wr) & ~vc_num_tail_wr;
    end
 
    // synthesis translate_off
 
    pronoc_register #(
           .W(V)
      ) reg2 (
           .in(hdr_passed_next),
           .reset(reset),
           .clk(clk),
           .out(hdr_passed)
      );
 
 
 
    always @ (posedge clk ) begin
            if(( hdr_passed & vc_num_hdr_wr)>0  )begin
                $display("%t ERROR: a header flit is received in  an active IVC %m",$time);
                $finish;
            end
            if((~hdr_passed & vc_num_tail_wr & ~single_flit_pck )>0 ) begin
                $display("%t ERROR: a tail flit is received in an inactive IVC %m",$time);
                $finish;
            end
            if ((~hdr_passed & vc_num_bdy_wr    )>0)begin
                $display("%t ERROR: a body flit is received in an inactive IVC %m",$time);
                $finish;
            end
            /* verilator lint_off WIDTH */
            if((PCK_TYPE == "SINGLE_FLIT") &  flit_in_wr & ~(hdr_flg_in &  tail_flg_in )) begin
                $display("%t ERROR: both tail and header flit flags must be asserted in SINGLE_FLIT mode %m",$time);
                $finish;
            end
            /* verilator lint_on WIDTH */
            if( (MIN_PCK_SIZE !=1) &  flit_in_wr & hdr_flg_in &  tail_flg_in ) begin
                $display("%t ERROR: A single flit packet is injected while the minimum packet size is set to %d.  %m",$time,MIN_PCK_SIZE);
                $finish;
            end
            //TODO check that the injected packet size meets the MIN_PCK_SIZE            
 
    end//always
    // synthesis translate_on
endmodule
 
 
 
 
 
 
module debug_mesh_tori_route_ckeck #(
    parameter T1=4,
    parameter T2=4,
    parameter T3=4,
    parameter ROUTE_TYPE = "FULL_ADAPTIVE",
    parameter V=4,
    parameter AVC_ATOMIC_EN=1,
    parameter SW_LOC = 0,
    parameter [V-1 : 0] ESCAP_VC_MASK= 4'b0001,
    parameter TOPOLOGY="MESH",
    parameter DSTPw=4,
    parameter RAw=4,
    parameter EAw=4,
    parameter DAw=EAw
)(
    reset,
    clk,
    hdr_flg_in,
    flit_in_wr,
    flit_is_tail,
    ivc_num_getting_sw_grant,
    vc_num_in,
    current_r_addr,
    dest_e_addr_in,
    src_e_addr_in,
    destport_in
);
 
    function integer log2;
        input integer number; begin
           log2=(number <=1) ? 1: 0;
           while(2**log2<number) begin
              log2=log2+1;
           end
        end
    endfunction // log2 
 
 
    input reset,clk;
    input hdr_flg_in , flit_in_wr;
    input [V-1 : 0] vc_num_in, flit_is_tail,  ivc_num_getting_sw_grant;
    input [RAw-1 : 0] current_r_addr;
    input [DAw-1 : 0] dest_e_addr_in;
    input [EAw-1 : 0] src_e_addr_in;
    input [DSTPw-1 : 0]  destport_in;
 
    localparam
      NX = T1,
      NY = T2,
      RXw = log2(NX),    // number of node in x axis
      RYw = log2(NY),
      EXw = log2(NX),    // number of node in x axis
      EYw = log2(NY);   // number of node in y axis
 
 
    wire [RXw-1 : 0] current_x;
    wire [EXw-1 : 0] x_dst_in,x_src_in;
    wire [RYw-1 : 0] current_y;
    wire [EYw-1 : 0] y_dst_in,y_src_in;
 
    mesh_tori_router_addr_decode #(
        .TOPOLOGY(TOPOLOGY),
        .T1(T1),
        .T2(T2),
        .T3(T3),
        .RAw(RAw)
    )
    r_addr_decode
    (
        .r_addr(current_r_addr),
        .rx(current_x),
        .ry(current_y),
        .valid()
    );
 
    mesh_tori_endp_addr_decode #(
        .TOPOLOGY(TOPOLOGY),
        .T1(T1),
        .T2(T2),
        .T3(T3),
        .EAw(EAw)
    )
    dst_addr_decode
    (
        .e_addr(dest_e_addr_in),
        .ex(x_dst_in),
        .ey(y_dst_in),
        .el( ),
        .valid()
    );
 
    mesh_tori_endp_addr_decode #(
        .TOPOLOGY(TOPOLOGY),
        .T1(T1),
        .T2(T2),
        .T3(T3),
        .EAw(EAw)
    )
    src_addr_decode
    (
        .e_addr(src_e_addr_in),
        .ex(x_src_in),
        .ey(y_src_in),
        .el( ),
        .valid()
    );
 
 
localparam
    LOCAL =  0,
    NORTH =  2,
    SOUTH =  4;
 // synthesis translate_off 
generate
 
/* verilator lint_off WIDTH */
if(ROUTE_TYPE == "DETERMINISTIC")begin :dtrmn
/* verilator lint_on WIDTH */
 
 
    always@( posedge clk)begin
        if(flit_in_wr & hdr_flg_in )
               if( destport_in[1:0]==2'b11) begin
                    $display ( "%t\t  ERROR: destport port %x is illegal for determistic routing.  %m",$time,destport_in );
                    $finish;
               end
        end//if
    end//always
 
 
/* verilator lint_off WIDTH */
if(ROUTE_TYPE == "FULL_ADAPTIVE")begin :full_adpt
/* verilator lint_on WIDTH */
 
    wire [V-1 : 0] not_empty;
    reg  [V-1 : 0] not_empty_next;
 
    pronoc_register #(
           .W(V)
      ) reg2 (
           .in(not_empty_next),
           .reset(reset),
           .clk(clk),
           .out(not_empty)
      );
 
     always@(*) begin
        not_empty_next = not_empty;
        if(hdr_flg_in & flit_in_wr) begin
            not_empty_next = not_empty | vc_num_in;
        end//hdr_wr_in
        if((flit_is_tail & ivc_num_getting_sw_grant)>0)begin
            not_empty_next = not_empty & ~ivc_num_getting_sw_grant;
        end//tail wr out
     end//always
 
    always@( posedge clk ) begin
        if(hdr_flg_in & flit_in_wr) begin
            if( ((AVC_ATOMIC_EN==1)&& (SW_LOC!= LOCAL)) || (SW_LOC== NORTH) || (SW_LOC== SOUTH) )begin
                if((vc_num_in  & ~ESCAP_VC_MASK)>0) begin // adaptive VCs
                    if( (not_empty & vc_num_in)>0) $display("%t  :Error AVC allocated nonatomicly in %d port %m",$time,SW_LOC);
                end
             end//( AVC_ATOMIC_EN || SW_LOC== NORTH || SW_LOC== SOUTH )
             if((vc_num_in  & ESCAP_VC_MASK)>0 && (SW_LOC== SOUTH || SW_LOC== NORTH) )  begin // escape vc
                       // if (a & b) $display("%t  :Error EVC allocation violate subfunction routing rules %m",$time);
                    if ((current_x - x_dst_in) !=0 && (current_y- y_dst_in) !=0) $display("%t  :Error EVC allocation violate subfunction routing rules src_x=%d src_y=%d dst_x%d   dst_y=%d %m",$time,x_src_in, y_src_in, x_dst_in,y_dst_in);
             end
         end//hdr_wr_in            
        end//always
    end //SW_LOC
 
 
    /* verilator lint_off WIDTH */
    if(TOPOLOGY=="MESH")begin :mesh
    /* verilator lint_on WIDTH */
        wire  [EXw-1 : 0] low_x,high_x;
        wire  [EYw-1 : 0] low_y,high_y;
 
 
 
        assign low_x = (x_src_in < x_dst_in)?  x_src_in : x_dst_in;
        assign low_y = (y_src_in < y_dst_in)?  y_src_in : y_dst_in;
        assign high_x = (x_src_in < x_dst_in)?  x_dst_in : x_src_in;
        assign high_y = (y_src_in < y_dst_in)?  y_dst_in : y_src_in;
 
 
        always@( posedge clk)begin
               if((current_x <low_x) | (current_x > high_x) | (current_y <low_y) | (current_y > high_y) )
                    if(flit_in_wr & hdr_flg_in )begin
                        $display ( "%t\t  ERROR: non_minimal routing %m",$time );
                        $finish;
                    end
 
        end
 
 
    end// mesh  
  endgenerate
 
  // synthesis translate_on
 
  endmodule
 
 
 module debug_mesh_edges #(
    parameter T1=2,
    parameter T2=2,
    parameter T3=3,
    parameter T4=3,
    parameter RAw=4,
    parameter P=5
 )(
    clk,
    current_r_addr,
    flit_out_wr_all
 );
 
    function integer log2;
        input integer number; begin
           log2=(number <=1) ? 1: 0;
           while(2**log2<number) begin
              log2=log2+1;
           end
        end
    endfunction // log2 
 
    input clk;
    input  [RAw-1 :  0]  current_r_addr;
    input  [P-1 :  0]  flit_out_wr_all;
 
    localparam
        RXw = log2(T1),    // number of node in x axis
        RYw = log2(T2);    // number of node in y axis
 
 
  wire [RXw-1 : 0] current_rx;
  wire [RYw-1 : 0] current_ry;
 
    mesh_tori_router_addr_decode #(
        .TOPOLOGY("MESH"),
        .T1(T1),
        .T2(T2),
        .T3(T3),
        .RAw(RAw)
    )
    addr_decode
    (
        .r_addr(current_r_addr),
        .rx(current_rx),
        .ry(current_ry),
        .valid()
    );
 
 
    localparam
        EAST = 1,
        NORTH = 2,
        WEST = 3,
        SOUTH = 4;
  // synthesis translate_off 
        always @(posedge clk) begin
        /* verilator lint_off WIDTH */
                if(current_rx == {RXw{1'b0}}         && flit_out_wr_all[WEST]) $display ( "%t\t  ERROR: a packet is going to the WEST in a router located in first column in mesh topology %m",$time );
                if(current_rx == T1-1     && flit_out_wr_all[EAST]) $display ( "%t\t   ERROR: a packet is going to the EAST in a router located in last column in mesh topology %m",$time );
                if(current_ry == {RYw{1'b0}}         && flit_out_wr_all[NORTH])$display ( "%t\t  ERROR: a packet is going to the NORTH in a router located in first row in mesh topology %m",$time );
                if(current_ry == T2-1    && flit_out_wr_all[SOUTH])$display ( "%t\t  ERROR: a packet is going to the SOUTH in a router located in last row in mesh topology %m",$time);
      /* verilator lint_on WIDTH */
        end//always
  // synthesis translate_on  
endmodule
 
 
/*******************
 *
 * *****************/
 
 module check_destination_addr #(
    parameter TOPOLOGY = "MESH",
    parameter T1=2,
    parameter T2=2,
    parameter T3=2,
    parameter T4=2,
    parameter EAw=2,
    parameter DAw=2,
    parameter SELF_LOOP_EN="NO",
    parameter CAST_TYPE = "UNICAST",
    parameter NE=8
 )(
     dest_is_valid,
     dest_e_addr,
     current_e_addr
 );
 
    input [DAw-1 : 0]  dest_e_addr;
    input [EAw-1 : 0]  current_e_addr;
    output dest_is_valid;
 
    // general rules
    /* verilator lint_off WIDTH */
    wire valid_dst  = (SELF_LOOP_EN   == "NO")? dest_e_addr  !=  current_e_addr : 1'b1;
    /* verilator lint_on WIDTH */
    wire valid;
    generate
    if(CAST_TYPE != "UNICAST") begin
 
            wire [NE-1 : 0] dest_mcast_all_endp;
 
            mcast_dest_list_decode decode (
                .dest_e_addr(dest_e_addr),
                .dest_o(dest_mcast_all_endp),
                .row_has_any_dest( ),
                .is_unicast()
            );
        //wire valid_dst_multi_r1  = (SELF_LOOP_EN   == "NO") ? ~(dest_mcast_all_endp[current_e_addr] == 1'b1) : 1'b1;
        wire valid_dst_multi_r2  = ~(dest_mcast_all_endp == {NE{1'b0}}); // there should be atleast one asserted destination
 
        assign  dest_is_valid =  valid_dst_multi_r2;// & valid_dst_multi_r1 ;  
    end else
    /* verilator lint_off WIDTH */
    if(TOPOLOGY=="MESH" || TOPOLOGY == "TORUS" || TOPOLOGY=="RING" || TOPOLOGY == "LINE") begin : mesh
   /* verilator lint_on WIDTH */
        mesh_tori_endp_addr_decode #(
                .TOPOLOGY(TOPOLOGY),
                .T1(T1),
                .T2(T2),
                .T3(T3),
                .EAw(EAw)
        )
        mesh_tori_endp_addr_decode(
                .e_addr(dest_e_addr),
                .ex(),
                .ey(),
                .el(),
                .valid(valid)
        );
       assign  dest_is_valid = valid_dst & valid;
 
    end else begin : tree
        assign  dest_is_valid = valid_dst;
    end
    endgenerate
 
 endmodule
 
 
 
module  endp_addr_encoder #(
    parameter TOPOLOGY ="MESH",
    parameter T1=4,
    parameter T2=4,
    parameter T3=4,
    parameter EAw=4,
    parameter NE=16
)
(
    id,
    code
 );
 
    function integer log2;
      input integer number; begin
         log2=(number <=1) ? 1: 0;
         while(2**log2<number) begin
            log2=log2+1;
         end
      end
    endfunction // log2 
 
    localparam NEw= log2(NE);
 
     input [NEw-1 :0] id;
     output [EAw-1 : 0] code;
 
     generate
     /* verilator lint_off WIDTH */
     if(TOPOLOGY == "FATTREE" || TOPOLOGY == "TREE" ) begin : tree
     /* verilator lint_on WIDTH */
       fattree_addr_encoder #(
        .K(T1),
        .L(T2)
       )
       addr_encoder
       (
        .id(id),
        .code(code)
       );
 
     /* verilator lint_off WIDTH */
     end else if  (TOPOLOGY == "MESH" || TOPOLOGY == "TORUS" || TOPOLOGY == "RING" || TOPOLOGY == "LINE") begin :tori
     /* verilator lint_on WIDTH */
        mesh_tori_addr_encoder #(
            .NX(T1),
            .NY(T2),
            .NL(T3),
            .NE(NE),
            .EAw(EAw),
            .TOPOLOGY(TOPOLOGY)
        )
        addr_encoder
        (
            .id(id),
            .code(code)
        );
     end else if (TOPOLOGY == "FMESH") begin :fmesh
        fmesh_addr_encoder #(
            .NX(T1),
            .NY(T2),
            .NL(T3),
            .NE(NE),
            .EAw(EAw)
        )
        addr_encoder
        (
        .id(id),
        .code(code)
        );
 
     end else begin :custom
 
        assign code =id;
 
     end
     endgenerate
endmodule
 
 
module endp_addr_decoder  #(
        parameter TOPOLOGY ="MESH",
        parameter T1=4,
        parameter T2=4,
        parameter T3=4,
        parameter EAw=4,
        parameter NE=16
        )
        (
        id,
        code
        );
 
    function integer log2;
        input integer number; begin
            log2=(number <=1) ? 1: 0;
            while(2**log2<number) begin
                log2=log2+1;
            end
        end
    endfunction // log2 
 
    localparam NEw= log2(NE);
 
    output [NEw-1 :0] id;
    input  [EAw-1 : 0] code;
 
    generate
    /* verilator lint_off WIDTH */
    if(TOPOLOGY == "FATTREE" || TOPOLOGY == "TREE" ) begin : tree
    /* verilator lint_on WIDTH */
        fattree_addr_decoder #(
                .K(T1),
                .L(T2)
 
            )decoder(
                .id(id),
                .code(code)
            );
    /* verilator lint_off WIDTH */
    end else if  (TOPOLOGY == "MESH" || TOPOLOGY == "TORUS" || TOPOLOGY == "RING" || TOPOLOGY == "LINE") begin :tori
    /* verilator lint_on WIDTH */
        mesh_tori_addr_coder #(
            .NX    (T1   ),
            .NY    (T2   ),
            .NL    (T3   ),
            .NE    (NE   ),
            .EAw   (EAw  )
            ) addr_coder (
            .id    (id   ),
            .code  (code ));
      /* verilator lint_off WIDTH */
     end else if (TOPOLOGY == "FMESH") begin :fmesh
      /* verilator lint_on WIDTH */
        fmesh_addr_coder #(
            .NX(T1),
            .NY(T2),
            .NL(T3),
            .NE(NE),
            .EAw(EAw)
        )
        addr_coder
        (
        .id(id),
        .code(code)
        );
 
    end else begin :custom
 
        assign id = code;
 
    end
    endgenerate
endmodule
 
 
module check_pck_size #(
    parameter V=2,
    parameter MIN_PCK_SIZE=2,
    parameter Fw=36,
    parameter DAw=4,
    parameter CAST_TYPE="UNICAST",
    parameter NE=4,
    parameter B=4,
    parameter LB=4
)(
    hdr_flg_in,
    flit_in_wr,
    tail_flg_in,
    vc_num_in,
    dest_e_addr_in,
    clk,
    reset
 
);
 
    input clk, reset;
    input hdr_flg_in, tail_flg_in, flit_in_wr;
    input [V-1 : 0] vc_num_in;
    input [DAw-1: 0] dest_e_addr_in;
 
    wire [NE-1 : 0] dest_mcast_all_endp [V-1 : 0];
    wire [31 : 0] pck_size_counter [V-1: 0];
    reg  [31 : 0] pck_size_counter_next [V-1: 0];
    wire [DAw-1 : 0] dest_e_addr [V-1:0];
    wire [V-1 : 0] vc_hdr_wr_en;
    wire [V-1 : 0] onehot;
 
    localparam MIN_B =  (B<LB)? B : LB;
 
 
 
 
 
 
   genvar i;
   generate
   for (i=0;i<V;i=i+1) begin
 
        always @(*) begin
            pck_size_counter_next [i] = pck_size_counter [i];
            if (vc_num_in == i)begin
                if(flit_in_wr) begin
                    if(hdr_flg_in) pck_size_counter_next[i]= 1;
                    else pck_size_counter_next[i]=pck_size_counter[i]+1;
                end
            end
        end
 
 
        pronoc_register #(.W(32)) reg1(
            .in     (pck_size_counter_next[i]),
            .reset  (reset ),
            .clk    (clk   ),
            .out    (pck_size_counter[i]   ));
 
         always @(posedge clk) begin
            if (vc_num_in == i)begin
                if(flit_in_wr & tail_flg_in) begin
                    if( pck_size_counter_next[i] < MIN_PCK_SIZE) begin
                        $display ( "%t\t  ERROR: A packet is injected to the router with packet size (%d flits) that is smaller than MIN_PCK_SIZE (%d flits) parameter  %m",$time,pck_size_counter_next[i],MIN_PCK_SIZE);
                        $finish;
                    end
                end
            end
         end
 
        /* verilator lint_off WIDTH */
        if(CAST_TYPE!="UNICAST") begin
        /* verilator lint_on WIDTH */
        //Check that the size of multicast/broadcast packets <= buffer size
            assign vc_hdr_wr_en [i] = flit_in_wr & hdr_flg_in & (vc_num_in == i);
            pronoc_register_ld_en #(.W(DAw)) reg2(
                .in     (dest_e_addr_in),
                .reset  (reset ),
                .clk    (clk   ),
                .ld     (vc_hdr_wr_en [i] ),
                .out    (dest_e_addr[i])
            );
 
 
            mcast_dest_list_decode decode (
                .dest_e_addr(dest_e_addr[i]),
                .dest_o(dest_mcast_all_endp[i]),
                .row_has_any_dest(),
                .is_unicast()
            );
 
            is_onehot0 #(
                .IN_WIDTH(NE)
            )
            one_h
            (
                .in(dest_mcast_all_endp[i]),
                .result(onehot[i])
 
            );
 
 
 
 
            always @(posedge clk) begin
                if (vc_num_in == i)begin
                    if(flit_in_wr & ~onehot[i])begin
                        if(pck_size_counter_next[i]>MIN_B) begin
                            $display ( "%t\t  ERROR: A multicast packet is injected to the router with packet size (%d flits) that is larger than the minimum router buffer size (%d flits) parameter  %m",$time,pck_size_counter_next[i],MIN_B);
                            $finish;
                        end// size
                    end//flit_wr
                end//vc_num
            end//always
 
        end//multicast
 
 
 
 
   end  //for
   endgenerate
 
 
 
endmodule
 

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[/] [an-fpga-implementation-of-low-latency-noc-based-mpsoc/] [trunk/] [mpsoc/] [rtl/] [src_noc/] [debug.v] - Blame information for rev 54

Line No.	Rev	Author	Line
1	48	alirezamon	`timescale 1ns / 1ps
2
3			`/**************************************`
4			`* Module: debug`
5			`* Date:2019-04-01`
6			`* Author: alireza`
7			`*`
8			`* Description: this file contain modules which are used for error checking/debiging of the NoC.`
9			`***************************************/`
10
11			`//check if flits are recived in correct order in a VC`
12
13			`module check_flit_chanel_type_is_in_order #(`
14			`parameter V=4,`
15			`parameter PCK_TYPE = "SINGLE_FLIT",`
16			`parameter MIN_PCK_SIZE=2`
17			`)(`
18			`hdr_flg_in,`
19			`flit_in_wr,`
20			`tail_flg_in,`
21			`vc_num_in,`
22			`clk,`
23			`reset`
24
25			`);`
26
27			`input clk, reset;`
28			`input hdr_flg_in, tail_flg_in, flit_in_wr;`
29			`input [V-1 : 0] vc_num_in;`
30
31
32
33
34			`wire [V-1 : 0] vc_num_hdr_wr, vc_num_tail_wr,vc_num_bdy_wr ;`
35	54	alirezamon	`wire [V-1 : 0] hdr_passed;`
36			`reg [V-1 : 0] hdr_passed_next;`
37	48	alirezamon	`wire [V-1 : 0] single_flit_pck;`
38
39			`assign vc_num_hdr_wr =(hdr_flg_in & flit_in_wr) ? vc_num_in : 0;`
40			`assign vc_num_tail_wr =(tail_flg_in & flit_in_wr)? vc_num_in : 0;`
41			`assign vc_num_bdy_wr =({hdr_flg_in,tail_flg_in} == 2'b00 && flit_in_wr)? vc_num_in : 0;`
42			`assign single_flit_pck = vc_num_hdr_wr & vc_num_tail_wr;`
43			`always @(*)begin`
44			`hdr_passed_next = (hdr_passed \| vc_num_hdr_wr) & ~vc_num_tail_wr;`
45			`end`
46
47			`// synthesis translate_off`
48	54	alirezamon
49			`pronoc_register #(`
50			`.W(V)`
51			`) reg2 (`
52			`.in(hdr_passed_next),`
53			`.reset(reset),`
54			`.clk(clk),`
55			`.out(hdr_passed)`
56			`);`
57
58
59
60			`always @ (posedge clk ) begin`
61	48	alirezamon	`if(( hdr_passed & vc_num_hdr_wr)>0 )begin`
62			`$display("%t ERROR: a header flit is received in an active IVC %m",$time);`
63			`$finish;`
64			`end`
65			`if((~hdr_passed & vc_num_tail_wr & ~single_flit_pck )>0 ) begin`
66			`$display("%t ERROR: a tail flit is received in an inactive IVC %m",$time);`
67			`$finish;`
68			`end`
69			`if ((~hdr_passed & vc_num_bdy_wr )>0)begin`
70			`$display("%t ERROR: a body flit is received in an inactive IVC %m",$time);`
71			`$finish;`
72			`end`
73			`/* verilator lint_off WIDTH */`
74			`if((PCK_TYPE == "SINGLE_FLIT") & flit_in_wr & ~(hdr_flg_in & tail_flg_in )) begin`
75			`$display("%t ERROR: both tail and header flit flags must be asserted in SINGLE_FLIT mode %m",$time);`
76			`$finish;`
77			`end`
78			`/* verilator lint_on WIDTH */`
79			`if( (MIN_PCK_SIZE !=1) & flit_in_wr & hdr_flg_in & tail_flg_in ) begin`
80			`$display("%t ERROR: A single flit packet is injected while the minimum packet size is set to %d. %m",$time,MIN_PCK_SIZE);`
81			`$finish;`
82			`end`
83	54	alirezamon	`//TODO check that the injected packet size meets the MIN_PCK_SIZE`
84
85	48	alirezamon	`end//always`
86			`// synthesis translate_on`
87			`endmodule`
88
89
90
91
92
93
94			`module debug_mesh_tori_route_ckeck #(`
95			`parameter T1=4,`
96			`parameter T2=4,`
97			`parameter T3=4,`
98			`parameter ROUTE_TYPE = "FULL_ADAPTIVE",`
99			`parameter V=4,`
100			`parameter AVC_ATOMIC_EN=1,`
101			`parameter SW_LOC = 0,`
102			`parameter [V-1 : 0] ESCAP_VC_MASK= 4'b0001,`
103			`parameter TOPOLOGY="MESH",`
104			`parameter DSTPw=4,`
105			`parameter RAw=4,`
106	54	alirezamon	`parameter EAw=4,`
107			`parameter DAw=EAw`
108	48	alirezamon	`)(`
109			`reset,`
110			`clk,`
111			`hdr_flg_in,`
112			`flit_in_wr,`
113			`flit_is_tail,`
114			`ivc_num_getting_sw_grant,`
115			`vc_num_in,`
116			`current_r_addr,`
117			`dest_e_addr_in,`
118			`src_e_addr_in,`
119			`destport_in`
120			`);`
121
122			`function integer log2;`
123			`input integer number; begin`
124			`log2=(number <=1) ? 1: 0;`
125			`while(2**log2<number) begin`
126			`log2=log2+1;`
127			`end`
128			`end`
129			`endfunction // log2`
130
131
132			`input reset,clk;`
133			`input hdr_flg_in , flit_in_wr;`
134			`input [V-1 : 0] vc_num_in, flit_is_tail, ivc_num_getting_sw_grant;`
135			`input [RAw-1 : 0] current_r_addr;`
136	54	alirezamon	`input [DAw-1 : 0] dest_e_addr_in;`
137			`input [EAw-1 : 0] src_e_addr_in;`
138	48	alirezamon	`input [DSTPw-1 : 0] destport_in;`
139
140			`localparam`
141			`NX = T1,`
142			`NY = T2,`
143			`RXw = log2(NX), // number of node in x axis`
144			`RYw = log2(NY),`
145			`EXw = log2(NX), // number of node in x axis`
146			`EYw = log2(NY); // number of node in y axis`
147
148
149			`wire [RXw-1 : 0] current_x;`
150			`wire [EXw-1 : 0] x_dst_in,x_src_in;`
151			`wire [RYw-1 : 0] current_y;`
152			`wire [EYw-1 : 0] y_dst_in,y_src_in;`
153
154			`mesh_tori_router_addr_decode #(`
155			`.TOPOLOGY(TOPOLOGY),`
156			`.T1(T1),`
157			`.T2(T2),`
158			`.T3(T3),`
159			`.RAw(RAw)`
160			`)`
161			`r_addr_decode`
162			`(`
163			`.r_addr(current_r_addr),`
164			`.rx(current_x),`
165			`.ry(current_y),`
166			`.valid()`
167			`);`
168
169			`mesh_tori_endp_addr_decode #(`
170			`.TOPOLOGY(TOPOLOGY),`
171			`.T1(T1),`
172			`.T2(T2),`
173			`.T3(T3),`
174			`.EAw(EAw)`
175			`)`
176			`dst_addr_decode`
177			`(`
178			`.e_addr(dest_e_addr_in),`
179			`.ex(x_dst_in),`
180			`.ey(y_dst_in),`
181			`.el( ),`
182			`.valid()`
183			`);`
184
185			`mesh_tori_endp_addr_decode #(`
186			`.TOPOLOGY(TOPOLOGY),`
187			`.T1(T1),`
188			`.T2(T2),`
189			`.T3(T3),`
190			`.EAw(EAw)`
191			`)`
192			`src_addr_decode`
193			`(`
194			`.e_addr(src_e_addr_in),`
195			`.ex(x_src_in),`
196			`.ey(y_src_in),`
197			`.el( ),`
198			`.valid()`
199			`);`
200
201
202			`localparam`
203			`LOCAL = 0,`
204			`NORTH = 2,`
205			`SOUTH = 4;`
206			`// synthesis translate_off`
207			`generate`
208
209			`/* verilator lint_off WIDTH */`
210			`if(ROUTE_TYPE == "DETERMINISTIC")begin :dtrmn`
211			`/* verilator lint_on WIDTH */`
212
213
214			`always@( posedge clk)begin`
215			`if(flit_in_wr & hdr_flg_in )`
216			`if( destport_in[1:0]==2'b11) begin`
217			`$display ( "%t\t ERROR: destport port %x is illegal for determistic routing. %m",$time,destport_in );`
218			`$finish;`
219			`end`
220			`end//if`
221			`end//always`
222
223
224			`/* verilator lint_off WIDTH */`
225			`if(ROUTE_TYPE == "FULL_ADAPTIVE")begin :full_adpt`
226			`/* verilator lint_on WIDTH */`
227
228	54	alirezamon	`wire [V-1 : 0] not_empty;`
229			`reg [V-1 : 0] not_empty_next;`
230
231			`pronoc_register #(`
232			`.W(V)`
233			`) reg2 (`
234			`.in(not_empty_next),`
235			`.reset(reset),`
236			`.clk(clk),`
237			`.out(not_empty)`
238			`);`
239
240			`always@(*) begin`
241			`not_empty_next = not_empty;`
242			`if(hdr_flg_in & flit_in_wr) begin`
243			`not_empty_next = not_empty \| vc_num_in;`
244			`end//hdr_wr_in`
245			`if((flit_is_tail & ivc_num_getting_sw_grant)>0)begin`
246			`not_empty_next = not_empty & ~ivc_num_getting_sw_grant;`
247			`end//tail wr out`
248			`end//always`
249
250			`always@( posedge clk ) begin`
251			`if(hdr_flg_in & flit_in_wr) begin`
252			`if( ((AVC_ATOMIC_EN==1)&& (SW_LOC!= LOCAL)) \|\| (SW_LOC== NORTH) \|\| (SW_LOC== SOUTH) )begin`
253			`if((vc_num_in & ~ESCAP_VC_MASK)>0) begin // adaptive VCs`
254			`if( (not_empty & vc_num_in)>0) $display("%t :Error AVC allocated nonatomicly in %d port %m",$time,SW_LOC);`
255			`end`
256			`end//( AVC_ATOMIC_EN \|\| SW_LOC== NORTH \|\| SW_LOC== SOUTH )`
257			`if((vc_num_in & ESCAP_VC_MASK)>0 && (SW_LOC== SOUTH \|\| SW_LOC== NORTH) ) begin // escape vc`
258			`// if (a & b) $display("%t :Error EVC allocation violate subfunction routing rules %m",$time);`
259			`if ((current_x - x_dst_in) !=0 && (current_y- y_dst_in) !=0) $display("%t :Error EVC allocation violate subfunction routing rules src_x=%d src_y=%d dst_x%d dst_y=%d %m",$time,x_src_in, y_src_in, x_dst_in,y_dst_in);`
260			`end`
261			`end//hdr_wr_in`
262	48	alirezamon	`end//always`
263			`end //SW_LOC`
264
265
266			`/* verilator lint_off WIDTH */`
267			`if(TOPOLOGY=="MESH")begin :mesh`
268			`/* verilator lint_on WIDTH */`
269			`wire [EXw-1 : 0] low_x,high_x;`
270			`wire [EYw-1 : 0] low_y,high_y;`
271
272
273
274			`assign low_x = (x_src_in < x_dst_in)? x_src_in : x_dst_in;`
275			`assign low_y = (y_src_in < y_dst_in)? y_src_in : y_dst_in;`
276			`assign high_x = (x_src_in < x_dst_in)? x_dst_in : x_src_in;`
277			`assign high_y = (y_src_in < y_dst_in)? y_dst_in : y_src_in;`
278
279
280			`always@( posedge clk)begin`
281			`if((current_x <low_x) \| (current_x > high_x) \| (current_y <low_y) \| (current_y > high_y) )`
282			`if(flit_in_wr & hdr_flg_in )begin`
283			`$display ( "%t\t ERROR: non_minimal routing %m",$time );`
284			`$finish;`
285			`end`
286
287			`end`
288
289
290			`end// mesh`
291			`endgenerate`
292
293			`// synthesis translate_on`
294
295			`endmodule`
296
297
298			`module debug_mesh_edges #(`
299			`parameter T1=2,`
300			`parameter T2=2,`
301			`parameter T3=3,`
302			`parameter T4=3,`
303			`parameter RAw=4,`
304			`parameter P=5`
305			`)(`
306			`clk,`
307			`current_r_addr,`
308			`flit_out_wr_all`
309			`);`
310
311			`function integer log2;`
312			`input integer number; begin`
313			`log2=(number <=1) ? 1: 0;`
314			`while(2**log2<number) begin`
315			`log2=log2+1;`
316			`end`
317			`end`
318			`endfunction // log2`
319
320			`input clk;`
321			`input [RAw-1 : 0] current_r_addr;`
322			`input [P-1 : 0] flit_out_wr_all;`
323
324			`localparam`
325			`RXw = log2(T1), // number of node in x axis`
326			`RYw = log2(T2); // number of node in y axis`
327
328
329			`wire [RXw-1 : 0] current_rx;`
330			`wire [RYw-1 : 0] current_ry;`
331
332			`mesh_tori_router_addr_decode #(`
333			`.TOPOLOGY("MESH"),`
334			`.T1(T1),`
335			`.T2(T2),`
336			`.T3(T3),`
337			`.RAw(RAw)`
338			`)`
339			`addr_decode`
340			`(`
341			`.r_addr(current_r_addr),`
342			`.rx(current_rx),`
343			`.ry(current_ry),`
344			`.valid()`
345			`);`
346
347
348			`localparam`
349			`EAST = 1,`
350			`NORTH = 2,`
351			`WEST = 3,`
352			`SOUTH = 4;`
353			`// synthesis translate_off`
354			`always @(posedge clk) begin`
355			`/* verilator lint_off WIDTH */`
356			`if(current_rx == {RXw{1'b0}} && flit_out_wr_all[WEST]) $display ( "%t\t ERROR: a packet is going to the WEST in a router located in first column in mesh topology %m",$time );`
357			`if(current_rx == T1-1 && flit_out_wr_all[EAST]) $display ( "%t\t ERROR: a packet is going to the EAST in a router located in last column in mesh topology %m",$time );`
358			`if(current_ry == {RYw{1'b0}} && flit_out_wr_all[NORTH])$display ( "%t\t ERROR: a packet is going to the NORTH in a router located in first row in mesh topology %m",$time );`
359			`if(current_ry == T2-1 && flit_out_wr_all[SOUTH])$display ( "%t\t ERROR: a packet is going to the SOUTH in a router located in last row in mesh topology %m",$time);`
360			`/* verilator lint_on WIDTH */`
361			`end//always`
362			`// synthesis translate_on`
363			`endmodule`
364
365
366			`/*******************`
367			`*`
368			`* *****************/`
369
370			`module check_destination_addr #(`
371			`parameter TOPOLOGY = "MESH",`
372			`parameter T1=2,`
373			`parameter T2=2,`
374			`parameter T3=2,`
375			`parameter T4=2,`
376			`parameter EAw=2,`
377	54	alirezamon	`parameter DAw=2,`
378			`parameter SELF_LOOP_EN="NO",`
379			`parameter CAST_TYPE = "UNICAST",`
380			`parameter NE=8`
381	48	alirezamon	`)(`
382			`dest_is_valid,`
383			`dest_e_addr,`
384			`current_e_addr`
385			`);`
386
387	54	alirezamon	`input [DAw-1 : 0] dest_e_addr;`
388			`input [EAw-1 : 0] current_e_addr;`
389	48	alirezamon	`output dest_is_valid;`
390
391			`// general rules`
392			`/* verilator lint_off WIDTH */`
393			`wire valid_dst = (SELF_LOOP_EN == "NO")? dest_e_addr != current_e_addr : 1'b1;`
394			`/* verilator lint_on WIDTH */`
395			`wire valid;`
396			`generate`
397	54	alirezamon	`if(CAST_TYPE != "UNICAST") begin`
398
399			`wire [NE-1 : 0] dest_mcast_all_endp;`
400
401			`mcast_dest_list_decode decode (`
402			`.dest_e_addr(dest_e_addr),`
403			`.dest_o(dest_mcast_all_endp),`
404			`.row_has_any_dest( ),`
405			`.is_unicast()`
406			`);`
407			`//wire valid_dst_multi_r1 = (SELF_LOOP_EN == "NO") ? ~(dest_mcast_all_endp[current_e_addr] == 1'b1) : 1'b1;`
408			`wire valid_dst_multi_r2 = ~(dest_mcast_all_endp == {NE{1'b0}}); // there should be atleast one asserted destination`
409
410			`assign dest_is_valid = valid_dst_multi_r2;// & valid_dst_multi_r1 ;`
411			`end else`
412	48	alirezamon	`/* verilator lint_off WIDTH */`
413			`if(TOPOLOGY=="MESH" \|\| TOPOLOGY == "TORUS" \|\| TOPOLOGY=="RING" \|\| TOPOLOGY == "LINE") begin : mesh`
414			`/* verilator lint_on WIDTH */`
415			`mesh_tori_endp_addr_decode #(`
416			`.TOPOLOGY(TOPOLOGY),`
417			`.T1(T1),`
418			`.T2(T2),`
419			`.T3(T3),`
420			`.EAw(EAw)`
421			`)`
422			`mesh_tori_endp_addr_decode(`
423			`.e_addr(dest_e_addr),`
424			`.ex(),`
425			`.ey(),`
426			`.el(),`
427			`.valid(valid)`
428			`);`
429			`assign dest_is_valid = valid_dst & valid;`
430
431			`end else begin : tree`
432			`assign dest_is_valid = valid_dst;`
433			`end`
434			`endgenerate`
435
436			`endmodule`
437
438
439
440			`module endp_addr_encoder #(`
441			`parameter TOPOLOGY ="MESH",`
442			`parameter T1=4,`
443			`parameter T2=4,`
444			`parameter T3=4,`
445			`parameter EAw=4,`
446			`parameter NE=16`
447			`)`
448			`(`
449			`id,`
450			`code`
451			`);`
452
453			`function integer log2;`
454			`input integer number; begin`
455			`log2=(number <=1) ? 1: 0;`
456			`while(2**log2<number) begin`
457			`log2=log2+1;`
458			`end`
459			`end`
460			`endfunction // log2`
461
462			`localparam NEw= log2(NE);`
463
464			`input [NEw-1 :0] id;`
465			`output [EAw-1 : 0] code;`
466
467			`generate`
468			`/* verilator lint_off WIDTH */`
469			`if(TOPOLOGY == "FATTREE" \|\| TOPOLOGY == "TREE" ) begin : tree`
470			`/* verilator lint_on WIDTH */`
471			`fattree_addr_encoder #(`
472			`.K(T1),`
473			`.L(T2)`
474			`)`
475			`addr_encoder`
476			`(`
477			`.id(id),`
478			`.code(code)`
479			`);`
480
481			`/* verilator lint_off WIDTH */`
482			`end else if (TOPOLOGY == "MESH" \|\| TOPOLOGY == "TORUS" \|\| TOPOLOGY == "RING" \|\| TOPOLOGY == "LINE") begin :tori`
483			`/* verilator lint_on WIDTH */`
484			`mesh_tori_addr_encoder #(`
485			`.NX(T1),`
486			`.NY(T2),`
487			`.NL(T3),`
488			`.NE(NE),`
489			`.EAw(EAw),`
490			`.TOPOLOGY(TOPOLOGY)`
491			`)`
492			`addr_encoder`
493			`(`
494			`.id(id),`
495			`.code(code)`
496			`);`
497			`end else if (TOPOLOGY == "FMESH") begin :fmesh`
498			`fmesh_addr_encoder #(`
499			`.NX(T1),`
500			`.NY(T2),`
501			`.NL(T3),`
502			`.NE(NE),`
503			`.EAw(EAw)`
504			`)`
505			`addr_encoder`
506			`(`
507			`.id(id),`
508			`.code(code)`
509			`);`
510
511			`end else begin :custom`
512
513			`assign code =id;`
514
515			`end`
516			`endgenerate`
517			`endmodule`
518
519
520			`module endp_addr_decoder #(`
521			`parameter TOPOLOGY ="MESH",`
522			`parameter T1=4,`
523			`parameter T2=4,`
524			`parameter T3=4,`
525			`parameter EAw=4,`
526			`parameter NE=16`
527			`)`
528			`(`
529			`id,`
530			`code`
531			`);`
532
533			`function integer log2;`
534			`input integer number; begin`
535			`log2=(number <=1) ? 1: 0;`
536			`while(2**log2<number) begin`
537			`log2=log2+1;`
538			`end`
539			`end`
540			`endfunction // log2`
541
542			`localparam NEw= log2(NE);`
543
544			`output [NEw-1 :0] id;`
545			`input [EAw-1 : 0] code;`
546
547			`generate`
548			`/* verilator lint_off WIDTH */`
549			`if(TOPOLOGY == "FATTREE" \|\| TOPOLOGY == "TREE" ) begin : tree`
550			`/* verilator lint_on WIDTH */`
551			`fattree_addr_decoder #(`
552			`.K(T1),`
553			`.L(T2)`
554
555			`)decoder(`
556			`.id(id),`
557			`.code(code)`
558			`);`
559			`/* verilator lint_off WIDTH */`
560			`end else if (TOPOLOGY == "MESH" \|\| TOPOLOGY == "TORUS" \|\| TOPOLOGY == "RING" \|\| TOPOLOGY == "LINE") begin :tori`
561			`/* verilator lint_on WIDTH */`
562			`mesh_tori_addr_coder #(`
563			`.NX (T1 ),`
564			`.NY (T2 ),`
565			`.NL (T3 ),`
566			`.NE (NE ),`
567			`.EAw (EAw )`
568			`) addr_coder (`
569			`.id (id ),`
570			`.code (code ));`
571	54	alirezamon	`/* verilator lint_off WIDTH */`
572	48	alirezamon	`end else if (TOPOLOGY == "FMESH") begin :fmesh`
573	54	alirezamon	`/* verilator lint_on WIDTH */`
574	48	alirezamon	`fmesh_addr_coder #(`
575			`.NX(T1),`
576			`.NY(T2),`
577			`.NL(T3),`
578			`.NE(NE),`
579			`.EAw(EAw)`
580			`)`
581			`addr_coder`
582			`(`
583			`.id(id),`
584			`.code(code)`
585			`);`
586
587			`end else begin :custom`
588
589			`assign id = code;`
590
591			`end`
592			`endgenerate`
593			`endmodule`
594
595
596	54	alirezamon	`module check_pck_size #(`
597			`parameter V=2,`
598			`parameter MIN_PCK_SIZE=2,`
599			`parameter Fw=36,`
600			`parameter DAw=4,`
601			`parameter CAST_TYPE="UNICAST",`
602			`parameter NE=4,`
603			`parameter B=4,`
604			`parameter LB=4`
605			`)(`
606			`hdr_flg_in,`
607			`flit_in_wr,`
608			`tail_flg_in,`
609			`vc_num_in,`
610			`dest_e_addr_in,`
611			`clk,`
612			`reset`
613
614			`);`
615
616			`input clk, reset;`
617			`input hdr_flg_in, tail_flg_in, flit_in_wr;`
618			`input [V-1 : 0] vc_num_in;`
619			`input [DAw-1: 0] dest_e_addr_in;`
620
621			`wire [NE-1 : 0] dest_mcast_all_endp [V-1 : 0];`
622			`wire [31 : 0] pck_size_counter [V-1: 0];`
623			`reg [31 : 0] pck_size_counter_next [V-1: 0];`
624			`wire [DAw-1 : 0] dest_e_addr [V-1:0];`
625			`wire [V-1 : 0] vc_hdr_wr_en;`
626			`wire [V-1 : 0] onehot;`
627
628			`localparam MIN_B = (B<LB)? B : LB;`
629
630
631
632
633
634
635			`genvar i;`
636			`generate`
637			`for (i=0;i<V;i=i+1) begin`
638
639			`always @(*) begin`
640			`pck_size_counter_next [i] = pck_size_counter [i];`
641			`if (vc_num_in == i)begin`
642			`if(flit_in_wr) begin`
643			`if(hdr_flg_in) pck_size_counter_next[i]= 1;`
644			`else pck_size_counter_next[i]=pck_size_counter[i]+1;`
645			`end`
646			`end`
647			`end`
648
649
650			`pronoc_register #(.W(32)) reg1(`
651			`.in (pck_size_counter_next[i]),`
652			`.reset (reset ),`
653			`.clk (clk ),`
654			`.out (pck_size_counter[i] ));`
655
656			`always @(posedge clk) begin`
657			`if (vc_num_in == i)begin`
658			`if(flit_in_wr & tail_flg_in) begin`
659			`if( pck_size_counter_next[i] < MIN_PCK_SIZE) begin`
660			`$display ( "%t\t ERROR: A packet is injected to the router with packet size (%d flits) that is smaller than MIN_PCK_SIZE (%d flits) parameter %m",$time,pck_size_counter_next[i],MIN_PCK_SIZE);`
661			`$finish;`
662			`end`
663			`end`
664			`end`
665			`end`
666
667			`/* verilator lint_off WIDTH */`
668			`if(CAST_TYPE!="UNICAST") begin`
669			`/* verilator lint_on WIDTH */`
670			`//Check that the size of multicast/broadcast packets <= buffer size`
671			`assign vc_hdr_wr_en [i] = flit_in_wr & hdr_flg_in & (vc_num_in == i);`
672			`pronoc_register_ld_en #(.W(DAw)) reg2(`
673			`.in (dest_e_addr_in),`
674			`.reset (reset ),`
675			`.clk (clk ),`
676			`.ld (vc_hdr_wr_en [i] ),`
677			`.out (dest_e_addr[i])`
678			`);`
679
680
681			`mcast_dest_list_decode decode (`
682			`.dest_e_addr(dest_e_addr[i]),`
683			`.dest_o(dest_mcast_all_endp[i]),`
684			`.row_has_any_dest(),`
685			`.is_unicast()`
686			`);`
687
688			`is_onehot0 #(`
689			`.IN_WIDTH(NE)`
690			`)`
691			`one_h`
692			`(`
693			`.in(dest_mcast_all_endp[i]),`
694			`.result(onehot[i])`
695
696			`);`
697
698
699
700
701			`always @(posedge clk) begin`
702			`if (vc_num_in == i)begin`
703			`if(flit_in_wr & ~onehot[i])begin`
704			`if(pck_size_counter_next[i]>MIN_B) begin`
705			`$display ( "%t\t ERROR: A multicast packet is injected to the router with packet size (%d flits) that is larger than the minimum router buffer size (%d flits) parameter %m",$time,pck_size_counter_next[i],MIN_B);`
706			`$finish;`
707			`end// size`
708			`end//flit_wr`
709			`end//vc_num`
710			`end//always`
711
712			`end//multicast`
713
714
715
716
717			`end //for`
718			`endgenerate`
719
720
721
722			`endmodule`
723