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`timescale    1ns/1ps
//`define MONITORE_PATH
 
/**********************************************************************
**      File: input_ports.v
**
**      Copyright (C) 2014-2017  Alireza Monemi
**
**      This file is part of ProNoC
**
**      ProNoC ( stands for Prototype Network-on-chip)  is free software:
**      you can redistribute it and/or modify it under the terms of the GNU
**      Lesser General Public License as published by the Free Software Foundation,
**      either version 2 of the License, or (at your option) any later version.
**
**      ProNoC is distributed in the hope that it will be useful, but WITHOUT
**      ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
**      or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU Lesser General
**      Public License for more details.
**
**      You should have received a copy of the GNU Lesser General Public
**      License along with ProNoC. If not, see .
**
**
**      Description:
**      NoC router input Port. It consists of input buffer, control FIFO
**      and request masking/generation control modules
**
**************************************************************/
 
 
/**************************
 
    iport_reg_base
 
**************************/
 
module iport_reg_base  #(
    parameter PCK_TYPE = "MULTI_FLIT",
    parameter V = 4,     // vc_num_per_port
    parameter P = 5,     // router port num
    parameter B = 4,     // buffer space :flit per VC
    parameter T1= 8,
    parameter T2= 8,
    parameter T3= 8,
    parameter T4= 8,
    parameter RAw = 3,
    parameter EAw = 3,
    parameter C = 4,    //    number of flit class
    parameter Fpay = 32,
    parameter SW_LOC = 0,
    parameter VC_REALLOCATION_TYPE =  "ATOMIC",
    parameter COMBINATION_TYPE= "BASELINE",// "BASELINE", "COMB_SPEC1", "COMB_SPEC2", "COMB_NONSPEC"
    parameter TOPOLOGY =  "MESH",//"MESH","TORUS"
    parameter ROUTE_NAME="XY",// "XY", "TRANC_XY"
    parameter ROUTE_TYPE="DETERMINISTIC",// "DETERMINISTIC", "FULL_ADAPTIVE", "PAR_ADAPTIVE"
    parameter DEBUG_EN =1,
    parameter AVC_ATOMIC_EN= 0,
    parameter CVw=(C==0)? V : C * V,
    parameter [CVw-1: 0] CLASS_SETTING = {CVw{1'b1}}, // shows how each class can use VCs
    parameter [V-1  : 0] ESCAP_VC_MASK = 4'b1000,  // mask scape vc, valid only for full adaptive
    parameter DSTPw = P-1,
    parameter SSA_EN="YES", // "YES" , "NO"
    parameter SWA_ARBITER_TYPE ="RRA",// "RRA","WRRA"
    parameter WEIGHTw=4,
    parameter WRRA_CONFIG_INDEX=0,
    parameter PPSw=4,
    parameter MIN_PCK_SIZE=2, //minimum packet size in flits. The minimum value is 1.
    parameter BYTE_EN=0
 
)(
    current_r_addr,
    neighbors_r_addr,
    ivc_num_getting_sw_grant,// for non spec ivc_num_getting_first_sw_grant,
    any_ivc_sw_request_granted,
    flit_in,
    flit_in_wr,
    reset_ivc,
    flit_is_tail,
    ivc_request,
    dest_port_encoded,
    dest_port,
    candidate_ovcs,
    flit_out,
    assigned_ovc_num,
    sel,
    port_pre_sel,
    swap_port_presel,
    reset,
    clk,
    nonspec_first_arbiter_granted_ivc,
    destport_clear,
    ssa_ivc_num_getting_sw_grant,
    iport_weight,
    oports_weight,
    vc_weight_is_consumed,
    iport_weight_is_consumed,
    refresh_w_counter,
    granted_dest_port
);
 
 
    function integer log2;
      input integer number; begin
         log2=(number <=1) ? 1: 0;
         while(2**log2
            log2=log2+1;
         end
      end
    endfunction // log2
 
 
    localparam
        VV = V * V,
        VDSTPw = V * DSTPw,
        Cw = (C>1)? log2(C): 1,
        Fw = 2+V+Fpay,   //flit width;
        W = WEIGHTw,
        WP = W * P,
        P_1=P-1,
        VP_1 = V * P_1;
 
    localparam
         /* verilator lint_off WIDTH */
         OFFSET = (B%MIN_PCK_SIZE)? 1 :0,
         NON_ATOM_PCKS =  (B>MIN_PCK_SIZE)?  (B/MIN_PCK_SIZE)+ OFFSET : 1,
         MAX_PCK = (VC_REALLOCATION_TYPE== "ATOMIC")?  1 : NON_ATOM_PCKS;// min packet size is two hence the max packet number in buffer is (B/2)
        /* verilator lint_on WIDTH */
 
     localparam
        ELw = log2(T3),
        VELw= V * ELw,
        PRAw= P * RAw;
 
 
    input reset, clk;
    input   [RAw-1 : 0] current_r_addr;
    input   [PRAw-1:  0]  neighbors_r_addr;
    input   [V-1 : 0] ivc_num_getting_sw_grant;
    input                      any_ivc_sw_request_granted;
    input   [Fw-1 : 0] flit_in;
    input                       flit_in_wr;
    input   [V-1 : 0] reset_ivc;
    output  [V-1 : 0] flit_is_tail;
    output  [V-1 : 0] ivc_request;
    output  [VDSTPw-1 : 0] dest_port_encoded;
    output  [VP_1-1 : 0] dest_port;
    output  [VV-1 : 0] candidate_ovcs;
    output  [Fw-1 : 0] flit_out;
    input   [VV-1 : 0] assigned_ovc_num;
    input   [V-1 : 0] sel;
    input   [V-1 : 0] nonspec_first_arbiter_granted_ivc;
    input   [V-1 : 0] ssa_ivc_num_getting_sw_grant;
    input   [(DSTPw*V)-1 : 0] destport_clear;
    output reg [WEIGHTw-1 : 0] iport_weight;
    output  [V-1 : 0] vc_weight_is_consumed;
    output  iport_weight_is_consumed;
    input   refresh_w_counter;
    input   [P_1-1 : 0] granted_dest_port;
    output  [WP-1 : 0] oports_weight;
    input   [PPSw-1 : 0] port_pre_sel;
    input   [V-1  : 0]  swap_port_presel;
 
 
 
    wire [Cw-1 : 0] class_in;
    wire [DSTPw-1 : 0] destport_in,destport_in_encoded;
    wire [VDSTPw-1 : 0] lk_destination_encoded;
    wire [EAw-1 : 0] dest_e_addr_in;
    wire [EAw-1 : 0] src_e_addr_in;
    wire [V-1 : 0] vc_num_in;
    wire [V-1 : 0] hdr_flit_wr,flit_wr;
    reg  [V-1 : 0] hdr_flit_wr_delayed;
    wire [V-1 : 0] class_rd_fifo,dst_rd_fifo;
    reg  [V-1 : 0] lk_dst_rd_fifo;
    wire [DSTPw-1 : 0] lk_destination_in_encoded;
    wire [WEIGHTw-1  : 0] weight_in;
    wire [Fw-1 : 0] buffer_out;
    wire hdr_flg_in,tail_flg_in;
    wire [V-1 : 0] ivc_not_empty;
    wire [Cw-1 : 0] class_out [V-1 : 0];
    wire  [VELw-1 : 0] endp_localp_num;
    wire [ELw-1 : 0] endp_l_in;
 
 
//extract header flit info
    extract_header_flit_info #(
        .DATA_w(0)
     )
     header_extractor
     (
         .flit_in(flit_in),
         .flit_in_wr(flit_in_wr),
         .class_o(class_in),
         .destport_o(destport_in),
         .dest_e_addr_o(dest_e_addr_in),
         .src_e_addr_o(src_e_addr_in),
         .vc_num_o(vc_num_in),
         .hdr_flit_wr_o(hdr_flit_wr),
         .hdr_flg_o(hdr_flg_in),
         .tail_flg_o(tail_flg_in),
         .weight_o(weight_in),
         .be_o( ),
         .data_o( )
     );
 
 
 
 
    // synopsys  translate_off
    // synthesis translate_off
     `ifdef MONITORE_PATH
 
    genvar j;
    reg[V-1 :0] t1;
    generate
    for (j=0;j
    always @(posedge clk) begin
        if(reset)begin
             t1[j]<=1'b0;
        end else begin
            if(flit_in_wr >0 && vc_num_in[j] && t1[j]==0)begin
                $display("%t : Parser: class_in=%x, destport_in=%x, dest_e_addr_in=%x, src_e_addr_in=%x, vc_num_in=%x,hdr_flit_wr=%x, hdr_flg_in=%x,tail_flg_in=%x ",$time,class_in, destport_in, dest_e_addr_in, src_e_addr_in, vc_num_in,hdr_flit_wr, hdr_flg_in,tail_flg_in);
                t1[j]<=1;
            end
        end
    end
    end
    endgenerate
    `endif
    // synthesis translate_on
    // synopsys  translate_on
 
 
`ifdef SYNC_RESET_MODE
    always @ (posedge clk )begin
`else
    always @ (posedge clk or posedge reset)begin
`endif
        if(reset) begin
              iport_weight <= 1;
        end else begin
              if(hdr_flit_wr != {V{1'b0}})  iport_weight <= (weight_in=={WEIGHTw{1'b0}})? 1 : weight_in; // the minimum weight is 1
        end
    end
 
// genrate write enable for lk_routing result with one clock cycle latency after reciveing the flit
`ifdef SYNC_RESET_MODE
    always @ (posedge clk )begin
`else
    always @ (posedge clk or posedge reset)begin
`endif
        if(reset) begin
            hdr_flit_wr_delayed <= {V{1'b0}};
            //lk_dst_rd_fifo          <= {V{1'b0}};
        end else begin
            hdr_flit_wr_delayed <= hdr_flit_wr;
        //    lk_dst_rd_fifo          <= dst_rd_fifo;
        end
    end
 
 
genvar i;
generate
    /* verilator lint_off WIDTH */
    if (( TOPOLOGY == "RING" || TOPOLOGY == "LINE" || TOPOLOGY == "MESH" || TOPOLOGY == "TORUS") && (T3>1)) begin : multi_local
    /* verilator lint_on WIDTH */
        mesh_tori_endp_addr_decode #(
            .TOPOLOGY("MESH"),
            .T1(T1),
            .T2(T2),
            .T3(T3),
            .EAw(EAw)
        )
        endp_addr_decode
        (
            .e_addr(dest_e_addr_in),
            .ex( ),
            .ey( ),
            .el(endp_l_in),
            .valid( )
        );
   end
 
    /* verilator lint_off WIDTH */
    if(TOPOLOGY=="FATTREE" && ROUTE_NAME == "NCA_STRAIGHT_UP") begin : fat
    /* verilator lint_on WIDTH */
 
     fattree_destport_up_select #(
         .K(T1),
         .SW_LOC(SW_LOC)
     )
     static_sel
     (
        .destport_in(destport_in),
        .destport_o(destport_in_encoded)
     );
 
    end else begin : other
        assign destport_in_encoded = destport_in;
    end
 
 
      wire odd_column = current_r_addr[0];
 
    for (i=0;i
 
        class_ovc_table #(
            .CVw(CVw),
            .CLASS_SETTING(CLASS_SETTING),
            .C(C),
            .V(V)
        )
        class_table
        (
            .class_in(class_out[i]),
            .candidate_ovcs(candidate_ovcs [(i+1)*V-1 : i*V])
        );
 
        //tail fifo
        fwft_fifo #(
            .DATA_WIDTH(1),
            .MAX_DEPTH (B),
            .IGNORE_SAME_LOC_RD_WR_WARNING(SSA_EN)
        )
        tail_fifo
        (
            .din (tail_flg_in),
            .wr_en (flit_wr[i]),   // Write enable
            .rd_en (ivc_num_getting_sw_grant[i]),   // Read the next word
            .dout (flit_is_tail[i]),    // Data out
            .full ( ),
            .nearly_full ( ),
            .recieve_more_than_0 ( ),
            .recieve_more_than_1 ( ),
            .reset (reset),
            .clk (clk)
        );
 
        //class_fifo
        if(C>1)begin :cb1
            fwft_fifo #(
                .DATA_WIDTH(Cw),
                .MAX_DEPTH (MAX_PCK)
            )
            class_fifo
            (
                .din (class_in),
                .wr_en (hdr_flit_wr[i]),   // Write enable
                .rd_en (class_rd_fifo[i]),   // Read the next word
                .dout (class_out[i]),    // Data out
                .full ( ),
                .nearly_full ( ),
                .recieve_more_than_0 ( ),
                .recieve_more_than_1 ( ),
                .reset (reset),
                .clk (clk)
 
            );
       end else begin :c_num_1
           assign class_out[i] = 1'b0;
       end
 
       //lk_dst_fifo
        fwft_fifo #(
            .DATA_WIDTH(DSTPw),
            .MAX_DEPTH (MAX_PCK)
        )
        lk_dest_fifo
        (
             .din (lk_destination_in_encoded),
             .wr_en (hdr_flit_wr_delayed [i]),   // Write enable
             .rd_en (lk_dst_rd_fifo [i]),   // Read the next word
             .dout (lk_destination_encoded  [(i+1)*DSTPw-1 : i*DSTPw]),    // Data out
             .full (),
             .nearly_full (),
             .recieve_more_than_0 (),
             .recieve_more_than_1 (),
             .reset (reset),
             .clk (clk)
 
        );
 
        /* verilator lint_off WIDTH */
        if( ROUTE_TYPE=="DETERMINISTIC") begin : dtrmn_dest
        /* verilator lint_on WIDTH */
            //destport_fifo
            fwft_fifo #(
                 .DATA_WIDTH(DSTPw),
                 .MAX_DEPTH (MAX_PCK)
            )
            dest_fifo
            (
                 .din(destport_in_encoded),
                 .wr_en(hdr_flit_wr[i]),   // Write enable
                 .rd_en(dst_rd_fifo[i]),   // Read the next word
                 .dout(dest_port_encoded[(i+1)*DSTPw-1 : i*DSTPw]),    // Data out
                 .full(),
                 .nearly_full(),
                 .recieve_more_than_0(),
                 .recieve_more_than_1(),
                 .reset(reset),
                 .clk(clk)
            );
 
        end else begin : adptv_dest
 
            fwft_fifo_with_output_clear #(
                .DATA_WIDTH(DSTPw),
                .MAX_DEPTH (MAX_PCK)
            )
            dest_fifo
            (
                .din(destport_in_encoded),
                .wr_en(hdr_flit_wr[i]),   // Write enable
                .rd_en(dst_rd_fifo[i]),   // Read the next word
                .dout(dest_port_encoded[(i+1)*DSTPw-1 : i*DSTPw]),    // Data out
                .full(),
                .nearly_full(),
                .recieve_more_than_0(),
                .recieve_more_than_1(),
                .reset(reset),
                .clk(clk),
                .clear(destport_clear[(i+1)*DSTPw-1 : i*DSTPw])   // clear other destination ports once one of them is selected
            );
 
 
        end
 
 
 
        destp_generator #(
            .TOPOLOGY(TOPOLOGY),
            .ROUTE_NAME(ROUTE_NAME),
            .ROUTE_TYPE(ROUTE_TYPE),
            .T1(T1),
            .NL(T3),
            .P(P),
            .DSTPw(DSTPw),
            .ELw(ELw),
            .PPSw(PPSw),
            .SW_LOC(SW_LOC)
        )
        decoder
        (
            .destport_one_hot(),
            .dest_port_encoded(dest_port_encoded[(i+1)*DSTPw-1 : i*DSTPw]),
            .dest_port_out(dest_port[(i+1)*P_1-1 : i*P_1]),
            .endp_localp_num(endp_localp_num[(i+1)*ELw-1 : i*ELw]),
            .swap_port_presel(swap_port_presel[i]),
            .port_pre_sel(port_pre_sel),
            .odd_column(odd_column)
        );
 
 
         /* verilator lint_off WIDTH */
        if (( TOPOLOGY == "RING" || TOPOLOGY == "LINE" || TOPOLOGY == "MESH" || TOPOLOGY == "TORUS") && (T3>1)) begin : multi_local
          /* verilator lint_on WIDTH */
            // the router has multiple local ports. Save the destination local port
 
 
            fwft_fifo #(
                 .DATA_WIDTH(ELw),
                 .MAX_DEPTH (MAX_PCK)
            )
            local_dest_fifo
            (
                 .din(endp_l_in),
                 .wr_en(hdr_flit_wr[i]),   // Write enable
                 .rd_en(dst_rd_fifo[i]),   // Read the next word
                 .dout(endp_localp_num[(i+1)*ELw-1 : i*ELw]),    // Data out
                 .full( ),
                 .nearly_full( ),
                 .recieve_more_than_0(),
                 .recieve_more_than_1(),
                 .reset(reset),
                 .clk(clk)
            );
 
        end else begin : slp
            assign endp_localp_num[(i+1)*ELw-1 : i*ELw] = {ELw{1'bx}};
        end
 
        /* verilator lint_off WIDTH */
        if(SWA_ARBITER_TYPE != "RRA")begin  : wrra
        /* verilator lint_on WIDTH */
               /*
                weight_control #(
                    .WEIGHTw(WEIGHTw)
                )
                wctrl_per_vc
                (
                    .sw_is_granted(ivc_num_getting_sw_grant[i]),
                    .flit_is_tail(flit_is_tail[i]),
                    .weight_is_consumed_o(vc_weight_is_consumed[i]),
                    .iport_weight(1),  //(iport_weight),
                    .clk(clk),
                    .reset(reset)
                );
                */
            assign vc_weight_is_consumed[i] = 1'b1;
        end else begin :no_wrra
            assign vc_weight_is_consumed[i] = 1'bX;
        end
 
    end//for i
 
 
    /* verilator lint_off WIDTH */
    if(SWA_ARBITER_TYPE != "RRA")begin  : wrra
    /* verilator lint_on WIDTH */
        wire granted_flit_is_tail;
 
        onehot_mux_1D #(
                .W(1),
                .N(V)
        )
        onehot_mux(
                .in(flit_is_tail),
                .out(granted_flit_is_tail),
                .sel(ivc_num_getting_sw_grant)
        );
 
        weight_control#(
            .ARBITER_TYPE(SWA_ARBITER_TYPE),
            .SW_LOC(SW_LOC),
            .WEIGHTw(WEIGHTw),
            .WRRA_CONFIG_INDEX(WRRA_CONFIG_INDEX),
            .P(P)
        )
        wctrl_iport
        (
            .sw_is_granted(any_ivc_sw_request_granted),
            .flit_is_tail(granted_flit_is_tail),
            .weight_is_consumed_o(iport_weight_is_consumed),
            .iport_weight(iport_weight),
            .oports_weight(oports_weight),
            .granted_dest_port(granted_dest_port),
            .refresh_w_counter(refresh_w_counter),
            .clk(clk),
            .reset(reset)
        );
 
        end else begin :no_wrra
            assign iport_weight_is_consumed=1'bX;
            assign oports_weight = {WP{1'bX}};
        end
 
    /* verilator lint_off WIDTH */
    if(COMBINATION_TYPE == "COMB_NONSPEC") begin  : nonspec
    /* verilator lint_on WIDTH */
 
        flit_buffer #(
            .V(V),
            .B(B),   // buffer space :flit per VC
            .PCK_TYPE(PCK_TYPE),
            .Fw(Fw),
            .DEBUG_EN(DEBUG_EN),
            .SSA_EN(SSA_EN)
        )
        the_flit_buffer
        (
            .din(flit_in),     // Data in
            .vc_num_wr(vc_num_in),//write vertual chanel
            .vc_num_rd(nonspec_first_arbiter_granted_ivc),//read vertual chanel
            .wr_en(flit_in_wr),   // Write enable
            .rd_en(any_ivc_sw_request_granted),     // Read the next word
            .dout(buffer_out),    // Data out
            .vc_not_empty(ivc_not_empty),
            .reset(reset),
            .clk(clk),
            .ssa_rd(ssa_ivc_num_getting_sw_grant)
        );
 
 
 
         localparam VCw = V *Cw;
        wire [Fw-1:0] new_buffer_out;
        wire [V-1 : 0] new_ivc_not_empty;
        wire [VCw-1 : 0] class_all;
 
 
 
        flit_buffer_reg_base #(
            .PCK_TYPE(PCK_TYPE),
            .V(V),
            .B(B),
            .Fpay(Fpay),
            .DEBUG_EN(DEBUG_EN),
 
            .DSTPw(DSTPw)
 
        )
        nn
        (
            .din(flit_in),
            .vc_num_wr(vc_num_in),
            .wr_en(flit_in_wr),
            .vc_num_rd(nonspec_first_arbiter_granted_ivc),
            .rd_en(any_ivc_sw_request_granted),
            .dout(new_buffer_out),
            .vc_not_empty(new_ivc_not_empty),
            .reset(reset),
            .clk(clk),
            .class_all()
        );
 
        //synthesis translate_off
        //synopsys  translate_off
        reg check_dout;
        always @(posedge clk )begin
            check_dout<=any_ivc_sw_request_granted;
            if(new_ivc_not_empty != ivc_not_empty) begin
                $display("%t: Error: new_iv_not_empty (%h) != iv_not_empty (%h)",$time, new_ivc_not_empty, ivc_not_empty);
                $stop;
            end
 
           if( check_dout & ( new_buffer_out[Fpay-1 : 0] != buffer_out[Fpay-1 : 0])) begin
                $display("%t: Error: new_buffer_out (%h) != buffer_out (%h)",$time, new_buffer_out, buffer_out);
                $stop;
           end
        end
        //synopsys  translate_on
        //synthesis translate_on
 
 
 
 
        // for (i=0;i
 
        // end
 
 
 
    end else begin :spec//not nonspec comb
 
 
        flit_buffer #(
            .V(V),
            .B(B),   // buffer space :flit per VC
            .PCK_TYPE(PCK_TYPE),
            .Fw(Fw),
            .DEBUG_EN(DEBUG_EN),
            .SSA_EN(SSA_EN)
        )
        the_flit_buffer
        (
            .din(flit_in),     // Data in
            .vc_num_wr(vc_num_in),//write vertual chanel
            .vc_num_rd(ivc_num_getting_sw_grant),//read vertual chanel
            .wr_en(flit_in_wr),   // Write enable
            .rd_en(any_ivc_sw_request_granted),     // Read the next word
            .dout(buffer_out),    // Data out
            .vc_not_empty(ivc_not_empty),
            .reset(reset),
            .clk(clk),
            .ssa_rd(ssa_ivc_num_getting_sw_grant)
        );
 
    end
endgenerate
 
    look_ahead_routing #(
        .T1(T1),
        .T2(T2),
        .T3(T3),
        .T4(T4),
        .P(P),
        .RAw(RAw),
        .EAw(EAw),
        .DSTPw(DSTPw),
        .SW_LOC(SW_LOC),
        .TOPOLOGY(TOPOLOGY),
        .ROUTE_NAME(ROUTE_NAME),
        .ROUTE_TYPE(ROUTE_TYPE)
    )
    lk_routing
    (
        .current_r_addr(current_r_addr),
        .neighbors_r_addr(neighbors_r_addr),
        .dest_e_addr(dest_e_addr_in),
        .src_e_addr(src_e_addr_in),
        .destport_encoded(destport_in_encoded),
        .lkdestport_encoded(lk_destination_in_encoded),
        .reset(reset),
        .clk(clk)
     );
 
    header_flit_update_lk_route_ovc #(
        .V(V),
        .P(P),
 
        .TOPOLOGY(TOPOLOGY),
        .EAw(EAw),
        .DSTPw(DSTPw),
        .SSA_EN(SSA_EN),
        .ROUTE_TYPE(ROUTE_TYPE)
 
    )
    the_flit_update
    (
        .flit_in (buffer_out),
        .flit_out (flit_out),
        .vc_num_in(ivc_num_getting_sw_grant),
        .lk_dest_all_in (lk_destination_encoded),
        .assigned_ovc_num (assigned_ovc_num),
        .any_ivc_sw_request_granted(any_ivc_sw_request_granted),
        .lk_dest_not_registered(lk_destination_in_encoded),
        .sel (sel),
        .reset (reset),
        .clk (clk)
    );
 
    assign flit_wr =(flit_in_wr )? vc_num_in : {V{1'b0}};
 
`ifdef SYNC_RESET_MODE
    always @ (posedge clk )begin
`else
    always @ (posedge clk or posedge reset)begin
`endif
        if(reset) begin
                lk_dst_rd_fifo          <= {V{1'b0}};
        end else begin
                lk_dst_rd_fifo          <= dst_rd_fifo;
            end
    end//always
 
 
    assign    dst_rd_fifo = reset_ivc;
    assign    class_rd_fifo = (C>1)? reset_ivc : {V{1'bx}};
    assign    ivc_request = ivc_not_empty;
 
//synthesis translate_off
//synopsys  translate_off
generate
if(DEBUG_EN) begin :dbg
 
    debug_IVC_flit_type_order_check #(
        .V(V)
    )
    IVC_flit_type_check
    (
        .clk(clk),
        .reset(reset),
        .hdr_flg_in(hdr_flg_in),
        .tail_flg_in(tail_flg_in),
        .flit_in_wr(flit_in_wr),
        .vc_num_in(vc_num_in),
        .reset_all_errors(1'b0),
        .active_IVC_hdr_flit_received_err( ),
        .inactive_IVC_tail_flit_received_err( ),
        .inactive_IVC_body_flit_received_err( )
    );
 
     /* verilator lint_off WIDTH */
     if (( TOPOLOGY == "RING" || TOPOLOGY == "LINE" || TOPOLOGY == "MESH" || TOPOLOGY == "TORUS")) begin : mesh_based
     /* verilator lint_on WIDTH */
 
        debug_mesh_tori_route_ckeck #(
            .T1(T1),
            .T2(T2),
            .T3(T3),
            .ROUTE_TYPE(ROUTE_TYPE),
            .V(V),
            .AVC_ATOMIC_EN(AVC_ATOMIC_EN),
            .SW_LOC(SW_LOC),
            .ESCAP_VC_MASK(ESCAP_VC_MASK),
            .TOPOLOGY(TOPOLOGY),
            .DSTPw(DSTPw),
            .RAw(RAw),
            .EAw(EAw)
        )
        route_ckeck
        (
            .reset(reset),
            .clk(clk),
            .hdr_flg_in(hdr_flg_in),
            .flit_in_wr(flit_in_wr),
            .vc_num_in(vc_num_in),
            .flit_is_tail(flit_is_tail),
            .ivc_num_getting_sw_grant(ivc_num_getting_sw_grant),
            .current_r_addr(current_r_addr),
            .dest_e_addr_in(dest_e_addr_in),
            .src_e_addr_in(src_e_addr_in),
            .destport_in(destport_in)
        );
    end//mesh
end//DEBUG_EN
endgenerate
//synopsys  translate_on
//synthesis translate_on
 
 
endmodule

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[/] [an-fpga-implementation-of-low-latency-noc-based-mpsoc/] [trunk/] [mpsoc/] [rtl/] [src_noc/] [iport_reg_base.sv] - Blame information for rev 48

Line No.	Rev	Author	Line
1	48	alirezamon	`timescale 1ns/1ps
2			//`define MONITORE_PATH
3
4			`/**********************************************************************`
5			`** File: input_ports.v`
6			`**`
7			`** Copyright (C) 2014-2017 Alireza Monemi`
8			`**`
9			`** This file is part of ProNoC`
10			`**`
11			`** ProNoC ( stands for Prototype Network-on-chip) is free software:`
12			`** you can redistribute it and/or modify it under the terms of the GNU`
13			`** Lesser General Public License as published by the Free Software Foundation,`
14			`** either version 2 of the License, or (at your option) any later version.`
15			`**`
16			`** ProNoC is distributed in the hope that it will be useful, but WITHOUT`
17			`** ANY WARRANTY; without even the implied warranty of MERCHANTABILITY`
18			`** or FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General`
19			`** Public License for more details.`
20			`**`
21			`** You should have received a copy of the GNU Lesser General Public`
22			`** License along with ProNoC. If not, see .`
23			`**`
24			`**`
25			`** Description:`
26			`** NoC router input Port. It consists of input buffer, control FIFO`
27			`** and request masking/generation control modules`
28			`**`
29			`**************************************************************/`
30
31
32			`/**************************`
33
34			`iport_reg_base`
35
36			`**************************/`
37
38			`module iport_reg_base #(`
39			`parameter PCK_TYPE = "MULTI_FLIT",`
40			`parameter V = 4, // vc_num_per_port`
41			`parameter P = 5, // router port num`
42			`parameter B = 4, // buffer space :flit per VC`
43			`parameter T1= 8,`
44			`parameter T2= 8,`
45			`parameter T3= 8,`
46			`parameter T4= 8,`
47			`parameter RAw = 3,`
48			`parameter EAw = 3,`
49			`parameter C = 4, // number of flit class`
50			`parameter Fpay = 32,`
51			`parameter SW_LOC = 0,`
52			`parameter VC_REALLOCATION_TYPE = "ATOMIC",`
53			`parameter COMBINATION_TYPE= "BASELINE",// "BASELINE", "COMB_SPEC1", "COMB_SPEC2", "COMB_NONSPEC"`
54			`parameter TOPOLOGY = "MESH",//"MESH","TORUS"`
55			`parameter ROUTE_NAME="XY",// "XY", "TRANC_XY"`
56			`parameter ROUTE_TYPE="DETERMINISTIC",// "DETERMINISTIC", "FULL_ADAPTIVE", "PAR_ADAPTIVE"`
57			`parameter DEBUG_EN =1,`
58			`parameter AVC_ATOMIC_EN= 0,`
59			`parameter CVw=(C==0)? V : C * V,`
60			`parameter [CVw-1: 0] CLASS_SETTING = {CVw{1'b1}}, // shows how each class can use VCs`
61			`parameter [V-1 : 0] ESCAP_VC_MASK = 4'b1000, // mask scape vc, valid only for full adaptive`
62			`parameter DSTPw = P-1,`
63			`parameter SSA_EN="YES", // "YES" , "NO"`
64			`parameter SWA_ARBITER_TYPE ="RRA",// "RRA","WRRA"`
65			`parameter WEIGHTw=4,`
66			`parameter WRRA_CONFIG_INDEX=0,`
67			`parameter PPSw=4,`
68			`parameter MIN_PCK_SIZE=2, //minimum packet size in flits. The minimum value is 1.`
69			`parameter BYTE_EN=0`
70
71			`)(`
72			`current_r_addr,`
73			`neighbors_r_addr,`
74			`ivc_num_getting_sw_grant,// for non spec ivc_num_getting_first_sw_grant,`
75			`any_ivc_sw_request_granted,`
76			`flit_in,`
77			`flit_in_wr,`
78			`reset_ivc,`
79			`flit_is_tail,`
80			`ivc_request,`
81			`dest_port_encoded,`
82			`dest_port,`
83			`candidate_ovcs,`
84			`flit_out,`
85			`assigned_ovc_num,`
86			`sel,`
87			`port_pre_sel,`
88			`swap_port_presel,`
89			`reset,`
90			`clk,`
91			`nonspec_first_arbiter_granted_ivc,`
92			`destport_clear,`
93			`ssa_ivc_num_getting_sw_grant,`
94			`iport_weight,`
95			`oports_weight,`
96			`vc_weight_is_consumed,`
97			`iport_weight_is_consumed,`
98			`refresh_w_counter,`
99			`granted_dest_port`
100			`);`
101
102
103			`function integer log2;`
104			`input integer number; begin`
105			`log2=(number <=1) ? 1: 0;`
106			`while(2**log2`
107			`log2=log2+1;`
108			`end`
109			`end`
110			`endfunction // log2`
111
112
113			`localparam`
114			`VV = V * V,`
115			`VDSTPw = V * DSTPw,`
116			`Cw = (C>1)? log2(C): 1,`
117			`Fw = 2+V+Fpay, //flit width;`
118			`W = WEIGHTw,`
119			`WP = W * P,`
120			`P_1=P-1,`
121			`VP_1 = V * P_1;`
122
123			`localparam`
124			`/* verilator lint_off WIDTH */`
125			`OFFSET = (B%MIN_PCK_SIZE)? 1 :0,`
126			`NON_ATOM_PCKS = (B>MIN_PCK_SIZE)? (B/MIN_PCK_SIZE)+ OFFSET : 1,`
127			`MAX_PCK = (VC_REALLOCATION_TYPE== "ATOMIC")? 1 : NON_ATOM_PCKS;// min packet size is two hence the max packet number in buffer is (B/2)`
128			`/* verilator lint_on WIDTH */`
129
130			`localparam`
131			`ELw = log2(T3),`
132			`VELw= V * ELw,`
133			`PRAw= P * RAw;`
134
135
136			`input reset, clk;`
137			`input [RAw-1 : 0] current_r_addr;`
138			`input [PRAw-1: 0] neighbors_r_addr;`
139			`input [V-1 : 0] ivc_num_getting_sw_grant;`
140			`input any_ivc_sw_request_granted;`
141			`input [Fw-1 : 0] flit_in;`
142			`input flit_in_wr;`
143			`input [V-1 : 0] reset_ivc;`
144			`output [V-1 : 0] flit_is_tail;`
145			`output [V-1 : 0] ivc_request;`
146			`output [VDSTPw-1 : 0] dest_port_encoded;`
147			`output [VP_1-1 : 0] dest_port;`
148			`output [VV-1 : 0] candidate_ovcs;`
149			`output [Fw-1 : 0] flit_out;`
150			`input [VV-1 : 0] assigned_ovc_num;`
151			`input [V-1 : 0] sel;`
152			`input [V-1 : 0] nonspec_first_arbiter_granted_ivc;`
153			`input [V-1 : 0] ssa_ivc_num_getting_sw_grant;`
154			`input [(DSTPw*V)-1 : 0] destport_clear;`
155			`output reg [WEIGHTw-1 : 0] iport_weight;`
156			`output [V-1 : 0] vc_weight_is_consumed;`
157			`output iport_weight_is_consumed;`
158			`input refresh_w_counter;`
159			`input [P_1-1 : 0] granted_dest_port;`
160			`output [WP-1 : 0] oports_weight;`
161			`input [PPSw-1 : 0] port_pre_sel;`
162			`input [V-1 : 0] swap_port_presel;`
163
164
165
166			`wire [Cw-1 : 0] class_in;`
167			`wire [DSTPw-1 : 0] destport_in,destport_in_encoded;`
168			`wire [VDSTPw-1 : 0] lk_destination_encoded;`
169			`wire [EAw-1 : 0] dest_e_addr_in;`
170			`wire [EAw-1 : 0] src_e_addr_in;`
171			`wire [V-1 : 0] vc_num_in;`
172			`wire [V-1 : 0] hdr_flit_wr,flit_wr;`
173			`reg [V-1 : 0] hdr_flit_wr_delayed;`
174			`wire [V-1 : 0] class_rd_fifo,dst_rd_fifo;`
175			`reg [V-1 : 0] lk_dst_rd_fifo;`
176			`wire [DSTPw-1 : 0] lk_destination_in_encoded;`
177			`wire [WEIGHTw-1 : 0] weight_in;`
178			`wire [Fw-1 : 0] buffer_out;`
179			`wire hdr_flg_in,tail_flg_in;`
180			`wire [V-1 : 0] ivc_not_empty;`
181			`wire [Cw-1 : 0] class_out [V-1 : 0];`
182			`wire [VELw-1 : 0] endp_localp_num;`
183			`wire [ELw-1 : 0] endp_l_in;`
184
185
186			`//extract header flit info`
187			`extract_header_flit_info #(`
188			`.DATA_w(0)`
189			`)`
190			`header_extractor`
191			`(`
192			`.flit_in(flit_in),`
193			`.flit_in_wr(flit_in_wr),`
194			`.class_o(class_in),`
195			`.destport_o(destport_in),`
196			`.dest_e_addr_o(dest_e_addr_in),`
197			`.src_e_addr_o(src_e_addr_in),`
198			`.vc_num_o(vc_num_in),`
199			`.hdr_flit_wr_o(hdr_flit_wr),`
200			`.hdr_flg_o(hdr_flg_in),`
201			`.tail_flg_o(tail_flg_in),`
202			`.weight_o(weight_in),`
203			`.be_o( ),`
204			`.data_o( )`
205			`);`
206
207
208
209
210			`// synopsys translate_off`
211			`// synthesis translate_off`
212			`ifdef MONITORE_PATH
213
214			`genvar j;`
215			`reg[V-1 :0] t1;`
216			`generate`
217			`for (j=0;j`
218			`always @(posedge clk) begin`
219			`if(reset)begin`
220			`t1[j]<=1'b0;`
221			`end else begin`
222			`if(flit_in_wr >0 && vc_num_in[j] && t1[j]==0)begin`
223			`$display("%t : Parser: class_in=%x, destport_in=%x, dest_e_addr_in=%x, src_e_addr_in=%x, vc_num_in=%x,hdr_flit_wr=%x, hdr_flg_in=%x,tail_flg_in=%x ",$time,class_in, destport_in, dest_e_addr_in, src_e_addr_in, vc_num_in,hdr_flit_wr, hdr_flg_in,tail_flg_in);`
224			`t1[j]<=1;`
225			`end`
226			`end`
227			`end`
228			`end`
229			`endgenerate`
230			`endif
231			`// synthesis translate_on`
232			`// synopsys translate_on`
233
234
235			`ifdef SYNC_RESET_MODE
236			`always @ (posedge clk )begin`
237			`else
238			`always @ (posedge clk or posedge reset)begin`
239			`endif
240			`if(reset) begin`
241			`iport_weight <= 1;`
242			`end else begin`
243			`if(hdr_flit_wr != {V{1'b0}}) iport_weight <= (weight_in=={WEIGHTw{1'b0}})? 1 : weight_in; // the minimum weight is 1`
244			`end`
245			`end`
246
247			`// genrate write enable for lk_routing result with one clock cycle latency after reciveing the flit`
248			`ifdef SYNC_RESET_MODE
249			`always @ (posedge clk )begin`
250			`else
251			`always @ (posedge clk or posedge reset)begin`
252			`endif
253			`if(reset) begin`
254			`hdr_flit_wr_delayed <= {V{1'b0}};`
255			`//lk_dst_rd_fifo <= {V{1'b0}};`
256			`end else begin`
257			`hdr_flit_wr_delayed <= hdr_flit_wr;`
258			`// lk_dst_rd_fifo <= dst_rd_fifo;`
259			`end`
260			`end`
261
262
263			`genvar i;`
264			`generate`
265			`/* verilator lint_off WIDTH */`
266			`if (( TOPOLOGY == "RING" \|\| TOPOLOGY == "LINE" \|\| TOPOLOGY == "MESH" \|\| TOPOLOGY == "TORUS") && (T3>1)) begin : multi_local`
267			`/* verilator lint_on WIDTH */`
268			`mesh_tori_endp_addr_decode #(`
269			`.TOPOLOGY("MESH"),`
270			`.T1(T1),`
271			`.T2(T2),`
272			`.T3(T3),`
273			`.EAw(EAw)`
274			`)`
275			`endp_addr_decode`
276			`(`
277			`.e_addr(dest_e_addr_in),`
278			`.ex( ),`
279			`.ey( ),`
280			`.el(endp_l_in),`
281			`.valid( )`
282			`);`
283			`end`
284
285			`/* verilator lint_off WIDTH */`
286			`if(TOPOLOGY=="FATTREE" && ROUTE_NAME == "NCA_STRAIGHT_UP") begin : fat`
287			`/* verilator lint_on WIDTH */`
288
289			`fattree_destport_up_select #(`
290			`.K(T1),`
291			`.SW_LOC(SW_LOC)`
292			`)`
293			`static_sel`
294			`(`
295			`.destport_in(destport_in),`
296			`.destport_o(destport_in_encoded)`
297			`);`
298
299			`end else begin : other`
300			`assign destport_in_encoded = destport_in;`
301			`end`
302
303
304			`wire odd_column = current_r_addr[0];`
305
306			`for (i=0;i`
307
308			`class_ovc_table #(`
309			`.CVw(CVw),`
310			`.CLASS_SETTING(CLASS_SETTING),`
311			`.C(C),`
312			`.V(V)`
313			`)`
314			`class_table`
315			`(`
316			`.class_in(class_out[i]),`
317			`.candidate_ovcs(candidate_ovcs [(i+1)V-1 : iV])`
318			`);`
319
320			`//tail fifo`
321			`fwft_fifo #(`
322			`.DATA_WIDTH(1),`
323			`.MAX_DEPTH (B),`
324			`.IGNORE_SAME_LOC_RD_WR_WARNING(SSA_EN)`
325			`)`
326			`tail_fifo`
327			`(`
328			`.din (tail_flg_in),`
329			`.wr_en (flit_wr[i]), // Write enable`
330			`.rd_en (ivc_num_getting_sw_grant[i]), // Read the next word`
331			`.dout (flit_is_tail[i]), // Data out`
332			`.full ( ),`
333			`.nearly_full ( ),`
334			`.recieve_more_than_0 ( ),`
335			`.recieve_more_than_1 ( ),`
336			`.reset (reset),`
337			`.clk (clk)`
338			`);`
339
340			`//class_fifo`
341			`if(C>1)begin :cb1`
342			`fwft_fifo #(`
343			`.DATA_WIDTH(Cw),`
344			`.MAX_DEPTH (MAX_PCK)`
345			`)`
346			`class_fifo`
347			`(`
348			`.din (class_in),`
349			`.wr_en (hdr_flit_wr[i]), // Write enable`
350			`.rd_en (class_rd_fifo[i]), // Read the next word`
351			`.dout (class_out[i]), // Data out`
352			`.full ( ),`
353			`.nearly_full ( ),`
354			`.recieve_more_than_0 ( ),`
355			`.recieve_more_than_1 ( ),`
356			`.reset (reset),`
357			`.clk (clk)`
358
359			`);`
360			`end else begin :c_num_1`
361			`assign class_out[i] = 1'b0;`
362			`end`
363
364			`//lk_dst_fifo`
365			`fwft_fifo #(`
366			`.DATA_WIDTH(DSTPw),`
367			`.MAX_DEPTH (MAX_PCK)`
368			`)`
369			`lk_dest_fifo`
370			`(`
371			`.din (lk_destination_in_encoded),`
372			`.wr_en (hdr_flit_wr_delayed [i]), // Write enable`
373			`.rd_en (lk_dst_rd_fifo [i]), // Read the next word`
374			`.dout (lk_destination_encoded [(i+1)DSTPw-1 : iDSTPw]), // Data out`
375			`.full (),`
376			`.nearly_full (),`
377			`.recieve_more_than_0 (),`
378			`.recieve_more_than_1 (),`
379			`.reset (reset),`
380			`.clk (clk)`
381
382			`);`
383
384			`/* verilator lint_off WIDTH */`
385			`if( ROUTE_TYPE=="DETERMINISTIC") begin : dtrmn_dest`
386			`/* verilator lint_on WIDTH */`
387			`//destport_fifo`
388			`fwft_fifo #(`
389			`.DATA_WIDTH(DSTPw),`
390			`.MAX_DEPTH (MAX_PCK)`
391			`)`
392			`dest_fifo`
393			`(`
394			`.din(destport_in_encoded),`
395			`.wr_en(hdr_flit_wr[i]), // Write enable`
396			`.rd_en(dst_rd_fifo[i]), // Read the next word`
397			`.dout(dest_port_encoded[(i+1)DSTPw-1 : iDSTPw]), // Data out`
398			`.full(),`
399			`.nearly_full(),`
400			`.recieve_more_than_0(),`
401			`.recieve_more_than_1(),`
402			`.reset(reset),`
403			`.clk(clk)`
404			`);`
405
406			`end else begin : adptv_dest`
407
408			`fwft_fifo_with_output_clear #(`
409			`.DATA_WIDTH(DSTPw),`
410			`.MAX_DEPTH (MAX_PCK)`
411			`)`
412			`dest_fifo`
413			`(`
414			`.din(destport_in_encoded),`
415			`.wr_en(hdr_flit_wr[i]), // Write enable`
416			`.rd_en(dst_rd_fifo[i]), // Read the next word`
417			`.dout(dest_port_encoded[(i+1)DSTPw-1 : iDSTPw]), // Data out`
418			`.full(),`
419			`.nearly_full(),`
420			`.recieve_more_than_0(),`
421			`.recieve_more_than_1(),`
422			`.reset(reset),`
423			`.clk(clk),`
424			`.clear(destport_clear[(i+1)DSTPw-1 : iDSTPw]) // clear other destination ports once one of them is selected`
425			`);`
426
427
428			`end`
429
430
431
432			`destp_generator #(`
433			`.TOPOLOGY(TOPOLOGY),`
434			`.ROUTE_NAME(ROUTE_NAME),`
435			`.ROUTE_TYPE(ROUTE_TYPE),`
436			`.T1(T1),`
437			`.NL(T3),`
438			`.P(P),`
439			`.DSTPw(DSTPw),`
440			`.ELw(ELw),`
441			`.PPSw(PPSw),`
442			`.SW_LOC(SW_LOC)`
443			`)`
444			`decoder`
445			`(`
446			`.destport_one_hot(),`
447			`.dest_port_encoded(dest_port_encoded[(i+1)DSTPw-1 : iDSTPw]),`
448			`.dest_port_out(dest_port[(i+1)P_1-1 : iP_1]),`
449			`.endp_localp_num(endp_localp_num[(i+1)ELw-1 : iELw]),`
450			`.swap_port_presel(swap_port_presel[i]),`
451			`.port_pre_sel(port_pre_sel),`
452			`.odd_column(odd_column)`
453			`);`
454
455
456			`/* verilator lint_off WIDTH */`
457			`if (( TOPOLOGY == "RING" \|\| TOPOLOGY == "LINE" \|\| TOPOLOGY == "MESH" \|\| TOPOLOGY == "TORUS") && (T3>1)) begin : multi_local`
458			`/* verilator lint_on WIDTH */`
459			`// the router has multiple local ports. Save the destination local port`
460
461
462			`fwft_fifo #(`
463			`.DATA_WIDTH(ELw),`
464			`.MAX_DEPTH (MAX_PCK)`
465			`)`
466			`local_dest_fifo`
467			`(`
468			`.din(endp_l_in),`
469			`.wr_en(hdr_flit_wr[i]), // Write enable`
470			`.rd_en(dst_rd_fifo[i]), // Read the next word`
471			`.dout(endp_localp_num[(i+1)ELw-1 : iELw]), // Data out`
472			`.full( ),`
473			`.nearly_full( ),`
474			`.recieve_more_than_0(),`
475			`.recieve_more_than_1(),`
476			`.reset(reset),`
477			`.clk(clk)`
478			`);`
479
480			`end else begin : slp`
481			`assign endp_localp_num[(i+1)ELw-1 : iELw] = {ELw{1'bx}};`
482			`end`
483
484			`/* verilator lint_off WIDTH */`
485			`if(SWA_ARBITER_TYPE != "RRA")begin : wrra`
486			`/* verilator lint_on WIDTH */`
487			`/*`
488			`weight_control #(`
489			`.WEIGHTw(WEIGHTw)`
490			`)`
491			`wctrl_per_vc`
492			`(`
493			`.sw_is_granted(ivc_num_getting_sw_grant[i]),`
494			`.flit_is_tail(flit_is_tail[i]),`
495			`.weight_is_consumed_o(vc_weight_is_consumed[i]),`
496			`.iport_weight(1), //(iport_weight),`
497			`.clk(clk),`
498			`.reset(reset)`
499			`);`
500			`*/`
501			`assign vc_weight_is_consumed[i] = 1'b1;`
502			`end else begin :no_wrra`
503			`assign vc_weight_is_consumed[i] = 1'bX;`
504			`end`
505
506			`end//for i`
507
508
509			`/* verilator lint_off WIDTH */`
510			`if(SWA_ARBITER_TYPE != "RRA")begin : wrra`
511			`/* verilator lint_on WIDTH */`
512			`wire granted_flit_is_tail;`
513
514			`onehot_mux_1D #(`
515			`.W(1),`
516			`.N(V)`
517			`)`
518			`onehot_mux(`
519			`.in(flit_is_tail),`
520			`.out(granted_flit_is_tail),`
521			`.sel(ivc_num_getting_sw_grant)`
522			`);`
523
524			`weight_control#(`
525			`.ARBITER_TYPE(SWA_ARBITER_TYPE),`
526			`.SW_LOC(SW_LOC),`
527			`.WEIGHTw(WEIGHTw),`
528			`.WRRA_CONFIG_INDEX(WRRA_CONFIG_INDEX),`
529			`.P(P)`
530			`)`
531			`wctrl_iport`
532			`(`
533			`.sw_is_granted(any_ivc_sw_request_granted),`
534			`.flit_is_tail(granted_flit_is_tail),`
535			`.weight_is_consumed_o(iport_weight_is_consumed),`
536			`.iport_weight(iport_weight),`
537			`.oports_weight(oports_weight),`
538			`.granted_dest_port(granted_dest_port),`
539			`.refresh_w_counter(refresh_w_counter),`
540			`.clk(clk),`
541			`.reset(reset)`
542			`);`
543
544			`end else begin :no_wrra`
545			`assign iport_weight_is_consumed=1'bX;`
546			`assign oports_weight = {WP{1'bX}};`
547			`end`
548
549			`/* verilator lint_off WIDTH */`
550			`if(COMBINATION_TYPE == "COMB_NONSPEC") begin : nonspec`
551			`/* verilator lint_on WIDTH */`
552
553			`flit_buffer #(`
554			`.V(V),`
555			`.B(B), // buffer space :flit per VC`
556			`.PCK_TYPE(PCK_TYPE),`
557			`.Fw(Fw),`
558			`.DEBUG_EN(DEBUG_EN),`
559			`.SSA_EN(SSA_EN)`
560			`)`
561			`the_flit_buffer`
562			`(`
563			`.din(flit_in), // Data in`
564			`.vc_num_wr(vc_num_in),//write vertual chanel`
565			`.vc_num_rd(nonspec_first_arbiter_granted_ivc),//read vertual chanel`
566			`.wr_en(flit_in_wr), // Write enable`
567			`.rd_en(any_ivc_sw_request_granted), // Read the next word`
568			`.dout(buffer_out), // Data out`
569			`.vc_not_empty(ivc_not_empty),`
570			`.reset(reset),`
571			`.clk(clk),`
572			`.ssa_rd(ssa_ivc_num_getting_sw_grant)`
573			`);`
574
575
576
577			`localparam VCw = V *Cw;`
578			`wire [Fw-1:0] new_buffer_out;`
579			`wire [V-1 : 0] new_ivc_not_empty;`
580			`wire [VCw-1 : 0] class_all;`
581
582
583
584			`flit_buffer_reg_base #(`
585			`.PCK_TYPE(PCK_TYPE),`
586			`.V(V),`
587			`.B(B),`
588			`.Fpay(Fpay),`
589			`.DEBUG_EN(DEBUG_EN),`
590
591			`.DSTPw(DSTPw)`
592
593			`)`
594			`nn`
595			`(`
596			`.din(flit_in),`
597			`.vc_num_wr(vc_num_in),`
598			`.wr_en(flit_in_wr),`
599			`.vc_num_rd(nonspec_first_arbiter_granted_ivc),`
600			`.rd_en(any_ivc_sw_request_granted),`
601			`.dout(new_buffer_out),`
602			`.vc_not_empty(new_ivc_not_empty),`
603			`.reset(reset),`
604			`.clk(clk),`
605			`.class_all()`
606			`);`
607
608			`//synthesis translate_off`
609			`//synopsys translate_off`
610			`reg check_dout;`
611			`always @(posedge clk )begin`
612			`check_dout<=any_ivc_sw_request_granted;`
613			`if(new_ivc_not_empty != ivc_not_empty) begin`
614			`$display("%t: Error: new_iv_not_empty (%h) != iv_not_empty (%h)",$time, new_ivc_not_empty, ivc_not_empty);`
615			`$stop;`
616			`end`
617
618			`if( check_dout & ( new_buffer_out[Fpay-1 : 0] != buffer_out[Fpay-1 : 0])) begin`
619			`$display("%t: Error: new_buffer_out (%h) != buffer_out (%h)",$time, new_buffer_out, buffer_out);`
620			`$stop;`
621			`end`
622			`end`
623			`//synopsys translate_on`
624			`//synthesis translate_on`
625
626
627
628
629			`// for (i=0;i`
630
631			`// end`
632
633
634
635			`end else begin :spec//not nonspec comb`
636
637
638			`flit_buffer #(`
639			`.V(V),`
640			`.B(B), // buffer space :flit per VC`
641			`.PCK_TYPE(PCK_TYPE),`
642			`.Fw(Fw),`
643			`.DEBUG_EN(DEBUG_EN),`
644			`.SSA_EN(SSA_EN)`
645			`)`
646			`the_flit_buffer`
647			`(`
648			`.din(flit_in), // Data in`
649			`.vc_num_wr(vc_num_in),//write vertual chanel`
650			`.vc_num_rd(ivc_num_getting_sw_grant),//read vertual chanel`
651			`.wr_en(flit_in_wr), // Write enable`
652			`.rd_en(any_ivc_sw_request_granted), // Read the next word`
653			`.dout(buffer_out), // Data out`
654			`.vc_not_empty(ivc_not_empty),`
655			`.reset(reset),`
656			`.clk(clk),`
657			`.ssa_rd(ssa_ivc_num_getting_sw_grant)`
658			`);`
659
660			`end`
661			`endgenerate`
662
663			`look_ahead_routing #(`
664			`.T1(T1),`
665			`.T2(T2),`
666			`.T3(T3),`
667			`.T4(T4),`
668			`.P(P),`
669			`.RAw(RAw),`
670			`.EAw(EAw),`
671			`.DSTPw(DSTPw),`
672			`.SW_LOC(SW_LOC),`
673			`.TOPOLOGY(TOPOLOGY),`
674			`.ROUTE_NAME(ROUTE_NAME),`
675			`.ROUTE_TYPE(ROUTE_TYPE)`
676			`)`
677			`lk_routing`
678			`(`
679			`.current_r_addr(current_r_addr),`
680			`.neighbors_r_addr(neighbors_r_addr),`
681			`.dest_e_addr(dest_e_addr_in),`
682			`.src_e_addr(src_e_addr_in),`
683			`.destport_encoded(destport_in_encoded),`
684			`.lkdestport_encoded(lk_destination_in_encoded),`
685			`.reset(reset),`
686			`.clk(clk)`
687			`);`
688
689			`header_flit_update_lk_route_ovc #(`
690			`.V(V),`
691			`.P(P),`
692
693			`.TOPOLOGY(TOPOLOGY),`
694			`.EAw(EAw),`
695			`.DSTPw(DSTPw),`
696			`.SSA_EN(SSA_EN),`
697			`.ROUTE_TYPE(ROUTE_TYPE)`
698
699			`)`
700			`the_flit_update`
701			`(`
702			`.flit_in (buffer_out),`
703			`.flit_out (flit_out),`
704			`.vc_num_in(ivc_num_getting_sw_grant),`
705			`.lk_dest_all_in (lk_destination_encoded),`
706			`.assigned_ovc_num (assigned_ovc_num),`
707			`.any_ivc_sw_request_granted(any_ivc_sw_request_granted),`
708			`.lk_dest_not_registered(lk_destination_in_encoded),`
709			`.sel (sel),`
710			`.reset (reset),`
711			`.clk (clk)`
712			`);`
713
714			`assign flit_wr =(flit_in_wr )? vc_num_in : {V{1'b0}};`
715
716			`ifdef SYNC_RESET_MODE
717			`always @ (posedge clk )begin`
718			`else
719			`always @ (posedge clk or posedge reset)begin`
720			`endif
721			`if(reset) begin`
722			`lk_dst_rd_fifo <= {V{1'b0}};`
723			`end else begin`
724			`lk_dst_rd_fifo <= dst_rd_fifo;`
725			`end`
726			`end//always`
727
728
729			`assign dst_rd_fifo = reset_ivc;`
730			`assign class_rd_fifo = (C>1)? reset_ivc : {V{1'bx}};`
731			`assign ivc_request = ivc_not_empty;`
732
733			`//synthesis translate_off`
734			`//synopsys translate_off`
735			`generate`
736			`if(DEBUG_EN) begin :dbg`
737
738			`debug_IVC_flit_type_order_check #(`
739			`.V(V)`
740			`)`
741			`IVC_flit_type_check`
742			`(`
743			`.clk(clk),`
744			`.reset(reset),`
745			`.hdr_flg_in(hdr_flg_in),`
746			`.tail_flg_in(tail_flg_in),`
747			`.flit_in_wr(flit_in_wr),`
748			`.vc_num_in(vc_num_in),`
749			`.reset_all_errors(1'b0),`
750			`.active_IVC_hdr_flit_received_err( ),`
751			`.inactive_IVC_tail_flit_received_err( ),`
752			`.inactive_IVC_body_flit_received_err( )`
753			`);`
754
755			`/* verilator lint_off WIDTH */`
756			`if (( TOPOLOGY == "RING" \|\| TOPOLOGY == "LINE" \|\| TOPOLOGY == "MESH" \|\| TOPOLOGY == "TORUS")) begin : mesh_based`
757			`/* verilator lint_on WIDTH */`
758
759			`debug_mesh_tori_route_ckeck #(`
760			`.T1(T1),`
761			`.T2(T2),`
762			`.T3(T3),`
763			`.ROUTE_TYPE(ROUTE_TYPE),`
764			`.V(V),`
765			`.AVC_ATOMIC_EN(AVC_ATOMIC_EN),`
766			`.SW_LOC(SW_LOC),`
767			`.ESCAP_VC_MASK(ESCAP_VC_MASK),`
768			`.TOPOLOGY(TOPOLOGY),`
769			`.DSTPw(DSTPw),`
770			`.RAw(RAw),`
771			`.EAw(EAw)`
772			`)`
773			`route_ckeck`
774			`(`
775			`.reset(reset),`
776			`.clk(clk),`
777			`.hdr_flg_in(hdr_flg_in),`
778			`.flit_in_wr(flit_in_wr),`
779			`.vc_num_in(vc_num_in),`
780			`.flit_is_tail(flit_is_tail),`
781			`.ivc_num_getting_sw_grant(ivc_num_getting_sw_grant),`
782			`.current_r_addr(current_r_addr),`
783			`.dest_e_addr_in(dest_e_addr_in),`
784			`.src_e_addr_in(src_e_addr_in),`
785			`.destport_in(destport_in)`
786			`);`
787			`end//mesh`
788			`end//DEBUG_EN`
789			`endgenerate`
790			`//synopsys translate_on`
791			`//synthesis translate_on`
792
793
794			`endmodule`