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[/] [an-fpga-implementation-of-low-latency-noc-based-mpsoc/] [trunk/] [mpsoc/] [rtl/] [src_noc/] [packet_injector.sv] - Blame information for rev 54

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`include "pronoc_def.v"
 
/****************************
 * This module can inject and eject packets from the NoC.
 * It can be used in simulation for injecting real application traces to the NoC
 * *************************/
 
 
module packet_injector
                import pronoc_pkg::*;
        (
                //general
                current_e_addr,
                reset,
                clk,
                //noc port
                chan_in,
                chan_out,
                //control interafce
                pck_injct_in,
                pck_injct_out
        );
 
        //general
        input reset,clk;
        input [EAw-1 :0 ] current_e_addr;
 
        // the destination endpoint address
        //NoC interface
        input   smartflit_chanel_t      chan_in;
        output  smartflit_chanel_t      chan_out;
        //control interafce
 
        input   pck_injct_t pck_injct_in;
        output  pck_injct_t pck_injct_out;
 
 
        wire  [RAw-1 :0 ] current_r_addr;
 
        wire  [DSTPw-1 : 0 ] destport;
        reg flit_wr;
 
 
 
 
 
 
        assign current_r_addr = chan_in.ctrl_chanel.neighbors_r_addr;
 
 
        generate if(CAST_TYPE == "UNICAST") begin : uni
 
                        conventional_routing #(
                                        .TOPOLOGY(TOPOLOGY),
                                        .ROUTE_NAME(ROUTE_NAME),
                                        .ROUTE_TYPE(ROUTE_TYPE),
                                        .T1(T1),
                                        .T2(T2),
                                        .T3(T3),
                                        .RAw(RAw),
                                        .EAw(EAw),
                                        .DSTPw(DSTPw),
                                        .LOCATED_IN_NI(1)
                                )
                                routing_module
                                (
                                        .reset(reset),
                                        .clk(clk),
                                        .current_r_addr(current_r_addr),
                                        .dest_e_addr(pck_injct_in.endp_addr),
                                        .src_e_addr(current_e_addr),
                                        .destport(destport)
                                );
                end endgenerate
 
 
        localparam
                HDR_BYTE_NUM =  HDR_MAX_DATw / 8, // = HDR_MAX_DATw / (8 - HDR_MAX_DATw %8)
                HDR_DATA_w_tmp   =  HDR_BYTE_NUM * 8,
                HDR_DATA_w =
                (PCK_INJ_Dw < HDR_DATA_w_tmp)? PCK_INJ_Dw :
                (HDR_DATA_w_tmp==0)? 1: HDR_DATA_w_tmp;
 
        wire [HDR_DATA_w-1 : 0] hdr_data_in = pck_injct_in.data [HDR_DATA_w-1 : 0];
        wire [Fw-1 : 0] hdr_flit_out;
 
        header_flit_generator #(
                        .DATA_w(HDR_DATA_w)
                )
                the_header_flit_generator
                (
                        .flit_out                       (hdr_flit_out),
                        .vc_num_in                      (pck_injct_in.vc),
                        .class_in                       (pck_injct_in.class_num),
                        .dest_e_addr_in         (pck_injct_in.endp_addr),
                        .src_e_addr_in          (current_e_addr),
                        .weight_in                      (pck_injct_in.init_weight),
                        .destport_in            (destport),
                        .data_in                        (hdr_data_in),
                        .be_in({BEw{1'b1}} )// Be is not used in simulation as we dont sent real data
                );
 
 
        localparam
                REMAIN_DATw =  PCK_INJ_Dw - HDR_DATA_w,
                REMAIN_DAT_FLIT_I = (REMAIN_DATw / Fpay),
                REMAIN_DAT_FLIT_F = (REMAIN_DATw % Fpay == 0)? 0 : 1,
                REMAIN_DAT_FLIT   = REMAIN_DAT_FLIT_I + REMAIN_DAT_FLIT_F,
                CNTw = log2(REMAIN_DAT_FLIT),
                MIN_PCK_SIZ = REMAIN_DAT_FLIT +1;
 
 
        logic [PCK_SIZw-1             :   0]  counter, counter_next;
        logic [CNTw-1                 :   0]  counter2,counter2_next;
        reg tail,head;
 
        wire [Fpay -1 : 0]  remain_dat [REMAIN_DAT_FLIT -1 : 0];
        wire [Fpay-1 : 0] dataIn =  remain_dat[counter2];
        enum  bit [2:0] {HEADER, BODY,TAIL} flit_type,flit_type_next;
 
 
 
        wire [V-1 : 0]   wr_vc_send = (flit_wr)?   pck_injct_in.vc : {V{1'b0}};
        wire [V-1 : 0]   vc_fifo_full;
 
 
        wire noc_ready;
 
        localparam
                LAST_TMP =PCK_INJ_Dw -  (Fpay*REMAIN_DAT_FLIT_I)-HDR_DATA_w,
                LASTw=(LAST_TMP==0)? Fpay : LAST_TMP;
        genvar i;
        generate
                for(i=0; i
                        assign remain_dat [i] = pck_injct_in.data [Fpay*(i+1)+HDR_DATA_w-1   : (Fpay*i)+HDR_DATA_w];
                end
                if(REMAIN_DAT_FLIT_F ) begin :flt
 
                        assign remain_dat [REMAIN_DAT_FLIT_I][LASTw-1 : 0] = pck_injct_in.data [PCK_INJ_Dw-1   : (Fpay*REMAIN_DAT_FLIT_I)+HDR_DATA_w];
                end
        endgenerate
 
 
 
 
 
        one_hot_mux #(
                        .IN_WIDTH   (V ),
                        .SEL_WIDTH  (V ),
                        .OUT_WIDTH  (1 )
                ) one_hot_mux1 (
                        .mux_in     (~ vc_fifo_full    ),
                        .mux_out    (noc_ready   ),
                        .sel        (pck_injct_in.vc       ));
 
 
 
 
        always @ (*) begin
                counter_next = counter;
                counter2_next =counter2;
                flit_type_next =flit_type;
                tail=1'b0;
                head=1'b0;
                flit_wr=0;
                if(noc_ready)begin
                        case(flit_type)
                                HEADER:begin
                                        if(pck_injct_in.pck_wr)begin
                                                flit_wr=1;
                                                counter_next = pck_injct_in.size-1;
                                                counter2_next=0;
                                                head=1'b1;
                                                if(pck_injct_in.size == 1)begin
                                                        tail=1'b1;
                                                end else if (pck_injct_in.size == 2) begin
                                                        flit_type_next = TAIL;
                                                end else begin
                                                        flit_type_next = BODY;
                                                end
                                        end
                                end
                                BODY: begin
                                        flit_wr=1;
                                        counter_next = counter -1'b1;
                                        counter2_next =counter2 +1'b1;
                                        if(counter == 2) begin
                                                flit_type_next = TAIL;
                                        end
                                end
                                TAIL: begin
                                        flit_type_next = HEADER;
                                        flit_wr=1;
                                        tail=1'b1;
                                end
                                default: begin
 
                                end
                        endcase
 
                end
        end
 
        logic [V-1 : 0] credit_o, credit_o_next;
 
        //pronoc_register #(.W(3),.RESET_TO(HEADER) ) reg1 (.in(flit_type_next ), .out(flit_type), .reset(reset), .clk(clk));
        pronoc_register #(.W(PCK_SIZw)) reg2 (.in(counter_next ), .out(counter), .reset(reset), .clk(clk));
        pronoc_register #(.W(CNTw))     reg3 (.in(counter2_next ), .out(counter2), .reset(reset), .clk(clk));
        pronoc_register #(.W(V))     reg4 (.in(credit_o_next ), .out(credit_o), .reset(reset), .clk(clk));
 
 
        always @ (*) begin
                credit_o_next = credit_o;
                if (chan_in.flit_chanel.flit_wr) credit_o_next =  chan_in.flit_chanel.flit.vc;
                else credit_o_next = {V{1'b0}};
        end
 
        always @(`pronoc_clk_reset_edge)begin
                if(`pronoc_reset) flit_type<=HEADER;
                else flit_type <= flit_type_next;
        end
 
 
 
        injector_ovc_status #(
                        .V(V),
                        .B(LB),
                        .CRDTw(CRDTw)
                )
                the_ovc_status
                (
                        .credit_init_val_in ( chan_in.ctrl_chanel.credit_init_val),
                        .wr_in(wr_vc_send),
                        .credit_in(chan_in.flit_chanel.credit),
                        .full_vc(vc_fifo_full),
                        .nearly_full_vc( ),
                        .empty_vc( ),
                        .clk(clk),
                        .reset(reset)
                );
 
 
 
 
 
 
 
        wire [HDR_DATA_w-1 : 0] hdr_data_o;
        hdr_flit_t hdr_flit_i;
 
        header_flit_info
                #(
                        .DATA_w         (HDR_DATA_w       )
                ) extractor (
                        .flit(chan_in.flit_chanel.flit),
                        .hdr_flit(hdr_flit_i),
                        .data_o(hdr_data_o)
                );
 
        wire [PCK_INJ_Dw-1 : 0]  pck_data_o [V-1 : 0];
        reg  [Fpay-1 : 0] pck_data_o_gen [V-1 : 0][REMAIN_DAT_FLIT : 0];
 
        genvar k;
 
        reg [PCK_SIZw-1 : 0] rsv_counter [V-1 : 0];
        reg [EAw-1 : 0] sender_endp_addr_reg [V-1 : 0];
        logic [15:0] h2t_counter [V-1 : 0];
        logic [15:0] h2t_counter_next [V-1 : 0];
 
 
 
        //synthesis translate_off
        wire [NEw-1 : 0] current_id;
        wire [NEw-1 : 0] sendor_id;
        endp_addr_decoder #( .TOPOLOGY(TOPOLOGY), .T1(T1), .T2(T2), .T3(T3), .EAw(EAw),  .NE(NE)) encode1 ( .id(current_id), .code(current_e_addr));
        endp_addr_decoder #( .TOPOLOGY(TOPOLOGY), .T1(T1), .T2(T2), .T3(T3), .EAw(EAw),  .NE(NE)) encode2 ( .id(sendor_id), .code(pck_injct_out.endp_addr[EAw-1 : 0]));
        //synthesis translate_on
 
        wire [NE-1 :0] dest_mcast_all_endp;
 
 
 
 
        generate
                if(CAST_TYPE != "UNICAST") begin
                        mcast_dest_list_decode decode (
                                        .dest_e_addr(hdr_flit_i.dest_e_addr),
                                        .dest_o(dest_mcast_all_endp),
                                        .row_has_any_dest(),
                                        .is_unicast()
                                );
                end
 
                for(i=0; i
                        always@(*) begin
                                h2t_counter_next[i]=h2t_counter[i]+1'b1;
                                if(chan_in.flit_chanel.flit.vc[i] & chan_in.flit_chanel.flit_wr & chan_in.flit_chanel.flit.hdr_flag)begin
                                        h2t_counter_next[i]= 16'd0; // reset once header flit is received
                                end//hdr flit wr
                        end//always
 
 
 
 
                        always @ (`pronoc_clk_reset_edge )begin
                                if(`pronoc_reset)  begin
                                        rsv_counter[i]<= {PCK_SIZw{1'b0}};
                                        h2t_counter[i]<= 16'd0;
                                        sender_endp_addr_reg [i]<= {EAw{1'b0}};
                                end else begin
                                        h2t_counter[i]<=h2t_counter_next[i];
                                        if(chan_in.flit_chanel.flit.vc[i] & chan_in.flit_chanel.flit_wr ) begin
                                                if(chan_in.flit_chanel.flit.hdr_flag)begin
                                                        rsv_counter[i]<= {{(PCK_SIZw-1){1'b0}}, 1'b1};
                                                        sender_endp_addr_reg [i]<= hdr_flit_i.src_e_addr;
                                                        //synthesis translate_off
                                                        if(CAST_TYPE == "UNICAST") begin
                                                                if(hdr_flit_i.dest_e_addr[EAw-1:0] != current_e_addr) begin
                                                                        $display("%t: ERROR: packet destination address %d does not match reciver endp address %d. %m",$time,hdr_flit_i.dest_e_addr , current_e_addr );
                                                                        $finish;
                                                                end//if hdr_flit_i
                                                        end else begin
                                                                if(dest_mcast_all_endp[current_id] !=1'b1 ) begin
                                                                        $display("%t: ERROR: packet destination address %b does not match reciver endp address %d. %m",$time,hdr_flit_i.dest_e_addr , current_e_addr ,current_id );
                                                                        $finish;
                                                                end
                                                        end//if hdr_flit_i
                                                        //synthesis translate_on
                                                end //if hdr_flag
                                                else rsv_counter[i]<= rsv_counter[i]+1'b1;
                                        end//flit wr
                                end//reset
                        end//always
 
 
 
 
                        for (k=0;k< REMAIN_DAT_FLIT+1;k++)begin : K_
 
                                always @ (`pronoc_clk_reset_edge )begin
                                        if(`pronoc_reset)  begin
                                                pck_data_o_gen [i][k] <= {Fpay{1'b0}};
 
                                        end else begin
                                                if(chan_in.flit_chanel.flit.vc[i] & chan_in.flit_chanel.flit_wr ) begin
                                                        if (chan_in.flit_chanel.flit.hdr_flag )begin
                                                                if ( k ==0 ) pck_data_o_gen [i][k][HDR_DATA_w-1 : 0] <= hdr_data_o;
                                                        end
                                                        else begin
                                                                if (rsv_counter[i] == k ) pck_data_o_gen [i][k] <= chan_in.flit_chanel.flit.payload[Fpay-1 : 0];
 
                                                        end // else
                                                end //if
                                        end //else
                                end// always
 
                                if   (k == 0 ) assign pck_data_o [i][HDR_DATA_w-1 : 0] = pck_data_o_gen [i][0][HDR_DATA_w-1 : 0];
                                else if (k == REMAIN_DAT_FLIT) assign pck_data_o [i][PCK_INJ_Dw-1 :    (k-1)*Fpay+ HDR_DATA_w] = pck_data_o_gen [i][k][LASTw-1: 0];
                                else assign pck_data_o [i][(k)*Fpay+HDR_DATA_w -1 : (k-1)*Fpay+ HDR_DATA_w] = pck_data_o_gen [i][k];
 
                        end //for k
 
 
                        //synthesis translate_off
                        always @(posedge clk) begin
                                if((pck_injct_out.ready[i] == 1'b0 ) & pck_injct_in.vc[i] & pck_injct_in.pck_wr )begin
                                        $display("%t: ERROR: a packet injection request is recived in core(%d), vc (%d) while packet injectore was not ready. %m",$time,current_id,i);
                                        $finish;
                                end
 
                        end
                        //synthesis translate_on
 
 
 
 
                end//for i
        endgenerate
 
        wire [V-1 : 0] vc_reg;
        wire tail_flag_reg, hdr_flag_reg;
 
 
        pronoc_register #(.W(V))   register1 (.in(chan_in.flit_chanel.flit.vc),        .reset  (reset ), .clk (clk),.out(vc_reg));
        pronoc_register #(.W(1))   register2 (.in(chan_in.flit_chanel.flit.hdr_flag),   .reset  (reset ), .clk (clk),.out(hdr_flag_reg));
        pronoc_register #(.W(1))   register3 (.in(chan_in.flit_chanel.flit.tail_flag & chan_in.flit_chanel.flit_wr ),.reset  (reset ), .clk (clk),.out(tail_flag_reg));
 
        wire [Vw-1 : 0] vc_bin;
 
        one_hot_to_bin #(
                        .ONE_HOT_WIDTH  (V),
                        .BIN_WIDTH      (Vw )
                ) one_hot_to_bin (
                        .one_hot_code   (vc_reg  ),
                        .bin_code       (vc_bin      )
                );
 
 
        assign pck_injct_out.data  =  pck_data_o[vc_bin];
        assign pck_injct_out.size  =  rsv_counter[vc_bin];
        assign pck_injct_out.h2t_delay = h2t_counter[vc_bin];
        assign pck_injct_out.ready = (flit_type == HEADER)?  ~vc_fifo_full : {V{1'b0}};
        assign pck_injct_out.endp_addr[EAw-1 : 0] =  sender_endp_addr_reg[vc_bin];
        assign pck_injct_out.vc = vc_reg;
        assign pck_injct_out.pck_wr = tail_flag_reg;
 
        assign chan_out.flit_chanel.flit.hdr_flag =head;
        assign chan_out.flit_chanel.flit.tail_flag=tail;
        assign chan_out.flit_chanel.flit.vc=pck_injct_in.vc;
        assign chan_out.flit_chanel.flit_wr=flit_wr;
 
        generate
        /* verilator lint_off WIDTH */
                if(PCK_TYPE == "SINGLE_FLIT" ) begin : single_f
                        /* verilator lint_on WIDTH */
                        assign chan_out.flit_chanel.flit.payload = hdr_flit_out[FPAYw-1 : 0];
                end else begin
                        assign chan_out.flit_chanel.flit.payload = (flit_type== HEADER)? hdr_flit_out[Fpay-1 : 0] : dataIn;
                end
        endgenerate
 
        assign chan_out.smart_chanel = {SMART_CHANEL_w{1'b0}};
        assign chan_out.flit_chanel.congestion = {CONGw{1'b0}};
        assign chan_out.flit_chanel.credit= credit_o;
        assign chan_out.ctrl_chanel.credit_init_val= LB;
        assign chan_out.ctrl_chanel.credit_release_en={V{1'b0}};
        assign chan_out.ctrl_chanel.endp_port =1'b1;
 
 
 
        distance_gen #(
                        .TOPOLOGY(TOPOLOGY),
                        .T1(T1),
                        .T2(T2),
                        .T3(T3),
                        .EAw(EAw),
                        .DISTw(DISTw)
                )
                the_distance_gen
                (
                        .src_e_addr(sender_endp_addr_reg[vc_bin]),
                        .dest_e_addr(current_e_addr),
                        .distance(pck_injct_out.distance)
                );
 
 
 
 
 
 
        //synthesis translate_off
        //`define MONITOR_RSV_DAT
 
 
 
        always @(posedge clk) begin
                if((pck_injct_in.vc == {V{1'b0}} ) & pck_injct_in.pck_wr )begin
                        $display("%t: ERROR: a packet injection request is recived while vc is not set. %m",$time);
                        $finish;
                end
                if(pck_injct_in.pck_wr && (pck_injct_in.size
                        $display("%t: ERROR: requested %d flit packet size is smaller than minimum %d flits to send %d bits of data. %m",$time,pck_injct_in.size,MIN_PCK_SIZ, PCK_INJ_Dw );
                        $finish;
                end
 
                `ifdef MONITOR_RSV_DAT
 
 
                        if(pck_injct_in.pck_wr) begin
                                $display ("pck_inj(%d) send a packet:  size=%d, data=%h, v=%h",current_id,
                                                pck_injct_in.size, pck_injct_in.data,pck_injct_in.vc);
                        end
 
                        if(pck_injct_out.pck_wr) begin
                                $display ("pck_inj(%d) got a packet: source=%d, size=%d, data=%h",current_id,
                                                sendor_id,pck_injct_out.size,pck_injct_out.data);
                        end
 
 
                `endif
 
        end
 
 
        //synthesis translate_on
 
 
 
 
 
endmodule
 
 
 
 
/******************
 *   ovc_status
 *******************/
 
module injector_ovc_status #(
                parameter V     =   4,
                parameter B =   16,
                parameter CRDTw =4
                )
                (
 
                input   [V-1 : 0] [CRDTw-1 : 0 ] credit_init_val_in,
                input   [V-1            :0] wr_in,
                input   [V-1            :0] credit_in,
                output  [V-1            :0] full_vc,
                output  [V-1            :0] nearly_full_vc,
                output  [V-1            :0] empty_vc,
                input                       clk,
                input                       reset
                );
 
 
        function integer log2;
                input integer number; begin
                        log2=(number <=1) ? 1: 0;
                        while(2**log2
                                log2=log2+1;
                        end
                end
        endfunction // log2
 
 
        localparam  DEPTH_WIDTH =   log2(B+1);
 
 
        reg  [DEPTH_WIDTH-1 : 0] credit    [V-1 : 0];
        wire  [V-1 : 0] cand_vc_next;
 
 
        genvar i;
        generate
                for(i=0;i
                        always @ (`pronoc_clk_reset_edge )begin
                                if(`pronoc_reset) begin
                                        credit[i]<= credit_init_val_in[i][DEPTH_WIDTH-1:0];
                                end else begin
                                        if(  wr_in[i]  && ~credit_in[i])   credit[i] <= credit[i]-1'b1;
                                        if( ~wr_in[i]  &&  credit_in[i])   credit[i] <= credit[i]+1'b1;
                                end //reset
                        end//always
 
                        assign  full_vc[i]   = (credit[i] == {DEPTH_WIDTH{1'b0}});
                        assign  nearly_full_vc[i]=  (credit[i] == 1) |  full_vc[i];
                        assign  empty_vc[i]  = (credit[i] == credit_init_val_in[i][DEPTH_WIDTH-1:0]);
                end//for
        endgenerate
endmodule
 
 
 
 
/**************************************
 *
 *
 * ***********************************/
 
 
 
module packet_injector_verilator
                import pronoc_pkg::*;
        (
                //general
                current_e_addr,
                reset,
                clk,
                //noc port
                chan_in,
                chan_out,
                //control interafce
                pck_injct_in_data,
                pck_injct_in_size,
                pck_injct_in_endp_addr,
                pck_injct_in_class_num,
                pck_injct_in_init_weight,
                pck_injct_in_vc,
                pck_injct_in_pck_wr,
                pck_injct_in_ready,
 
                pck_injct_out_data,
                pck_injct_out_size,
                pck_injct_out_endp_addr,
                pck_injct_out_class_num,
                pck_injct_out_init_weight,
                pck_injct_out_vc,
                pck_injct_out_pck_wr,
                pck_injct_out_ready,
                pck_injct_out_distance,
                pck_injct_out_h2t_delay,
                min_pck_size
 
 
        );
 
 
        //general
        input reset,clk;
        input [EAw-1 :0 ] current_e_addr;
 
        // the destination endpoint address
        //NoC interface
        input   smartflit_chanel_t      chan_in;
        output  smartflit_chanel_t      chan_out;
        //control interafce
 
 
        input [PCK_INJ_Dw-1 : 0] pck_injct_in_data;
        input [PCK_SIZw-1   : 0] pck_injct_in_size;
        input [DAw-1        : 0] pck_injct_in_endp_addr;
        input [Cw-1         : 0] pck_injct_in_class_num;
        input [WEIGHTw-1    : 0] pck_injct_in_init_weight;
        input [V-1          : 0] pck_injct_in_vc;
        input                    pck_injct_in_pck_wr;
        input [V-1          : 0] pck_injct_in_ready;
 
        output [PCK_INJ_Dw-1 : 0] pck_injct_out_data;
        output [PCK_SIZw-1   : 0] pck_injct_out_size;
        output [DAw-1        : 0] pck_injct_out_endp_addr;
        output [Cw-1         : 0] pck_injct_out_class_num;
        output [WEIGHTw-1    : 0] pck_injct_out_init_weight;
        output [V-1          : 0] pck_injct_out_vc;
        output                    pck_injct_out_pck_wr;
        output [V-1          : 0] pck_injct_out_ready;
        output [DISTw-1           : 0] pck_injct_out_distance;
        output [15                        : 0] pck_injct_out_h2t_delay;
        output [4                         : 0] min_pck_size;
 
        pck_injct_t pck_injct_in;
        pck_injct_t pck_injct_out;
 
        assign pck_injct_in.data         = pck_injct_in_data;
        assign pck_injct_in.size         = pck_injct_in_size;
        assign pck_injct_in.endp_addr    = pck_injct_in_endp_addr;
        assign pck_injct_in.class_num    = pck_injct_in_class_num;
        assign pck_injct_in.init_weight  = pck_injct_in_init_weight;
        assign pck_injct_in.vc           = pck_injct_in_vc;
        assign pck_injct_in.pck_wr        = pck_injct_in_pck_wr;
        assign pck_injct_in.ready        = pck_injct_in_ready;
 
        assign pck_injct_out_data        = pck_injct_out.data;
        assign pck_injct_out_size        = pck_injct_out.size;
        assign pck_injct_out_endp_addr   = pck_injct_out.endp_addr;
        assign pck_injct_out_class_num   = pck_injct_out.class_num;
        assign pck_injct_out_init_weight = pck_injct_out.init_weight;
        assign pck_injct_out_vc          = pck_injct_out.vc;
        assign pck_injct_out_pck_wr       = pck_injct_out.pck_wr;
        assign pck_injct_out_ready       = pck_injct_out.ready;
        assign pck_injct_out_distance    = pck_injct_out.distance;
        assign pck_injct_out_h2t_delay   = pck_injct_out.h2t_delay;
 
        packet_injector injector (
                        .current_e_addr  (current_e_addr ),
                        .reset           (reset          ),
                        .clk             (clk            ),
                        .chan_in         (chan_in        ),
                        .chan_out        (chan_out       ),
                        .pck_injct_in    (pck_injct_in   ),
                        .pck_injct_out   (pck_injct_out  ));
 
 
        localparam
                HDR_BYTE_NUM =  HDR_MAX_DATw / 8, // = HDR_MAX_DATw / (8 - HDR_MAX_DATw %8)
                HDR_DATA_w_tmp   =  HDR_BYTE_NUM * 8,
                HDR_DATA_w =
                (PCK_INJ_Dw < HDR_DATA_w_tmp)? PCK_INJ_Dw :
                (HDR_DATA_w_tmp==0)? 1: HDR_DATA_w_tmp,
                REMAIN_DATw =  PCK_INJ_Dw - HDR_DATA_w,
                REMAIN_DAT_FLIT_I = (REMAIN_DATw / Fpay),
                REMAIN_DAT_FLIT_F = (REMAIN_DATw % Fpay == 0)? 0 : 1,
                REMAIN_DAT_FLIT   = REMAIN_DAT_FLIT_I + REMAIN_DAT_FLIT_F,
                CNTw = log2(REMAIN_DAT_FLIT),
                MIN_PCK_SIZ = REMAIN_DAT_FLIT +1;
 
        assign  min_pck_size = MIN_PCK_SIZ[4:0];
 
 
        // `ifdef VERILATOR
        //      logic  endp_is_active   /*verilator public_flat_rd*/ ;
        //
        //      always @ (*) begin
        //              endp_is_active  = 1'b0;
        //              if (chan_out.flit_chanel.flit_wr) endp_is_active=1'b1;
        //              if (chan_out.flit_chanel.credit > {V{1'b0}} ) endp_is_active=1'b1;
        //              if (chan_out.smart_chanel.requests > {SMART_NUM{1'b0}} ) endp_is_active=1'b1;
        //      end
        // `endif
 
 
endmodule

Line No.	Rev	Author	Line
1	54	alirezamon	`include "pronoc_def.v"
2
3	48	alirezamon	`/****************************`
4			`* This module can inject and eject packets from the NoC.`
5			`* It can be used in simulation for injecting real application traces to the NoC`
6			`* *************************/`
7
8
9			`module packet_injector`
10			`import pronoc_pkg::*;`
11			`(`
12			`//general`
13			`current_e_addr,`
14			`reset,`
15			`clk,`
16			`//noc port`
17			`chan_in,`
18			`chan_out,`
19			`//control interafce`
20			`pck_injct_in,`
21			`pck_injct_out`
22			`);`
23
24			`//general`
25			`input reset,clk;`
26			`input [EAw-1 :0 ] current_e_addr;`
27
28			`// the destination endpoint address`
29			`//NoC interface`
30			`input smartflit_chanel_t chan_in;`
31			`output smartflit_chanel_t chan_out;`
32			`//control interafce`
33
34			`input pck_injct_t pck_injct_in;`
35			`output pck_injct_t pck_injct_out;`
36
37
38			`wire [RAw-1 :0 ] current_r_addr;`
39
40			`wire [DSTPw-1 : 0 ] destport;`
41			`reg flit_wr;`
42
43
44
45
46
47
48			`assign current_r_addr = chan_in.ctrl_chanel.neighbors_r_addr;`
49
50
51	54	alirezamon	`generate if(CAST_TYPE == "UNICAST") begin : uni`
52	48	alirezamon
53	54	alirezamon	`conventional_routing #(`
54			`.TOPOLOGY(TOPOLOGY),`
55			`.ROUTE_NAME(ROUTE_NAME),`
56			`.ROUTE_TYPE(ROUTE_TYPE),`
57			`.T1(T1),`
58			`.T2(T2),`
59			`.T3(T3),`
60			`.RAw(RAw),`
61			`.EAw(EAw),`
62			`.DSTPw(DSTPw),`
63			`.LOCATED_IN_NI(1)`
64			`)`
65			`routing_module`
66			`(`
67			`.reset(reset),`
68			`.clk(clk),`
69			`.current_r_addr(current_r_addr),`
70			`.dest_e_addr(pck_injct_in.endp_addr),`
71			`.src_e_addr(current_e_addr),`
72			`.destport(destport)`
73			`);`
74			`end endgenerate`
75	48	alirezamon
76
77			`localparam`
78			`HDR_BYTE_NUM = HDR_MAX_DATw / 8, // = HDR_MAX_DATw / (8 - HDR_MAX_DATw %8)`
79			`HDR_DATA_w_tmp = HDR_BYTE_NUM * 8,`
80	54	alirezamon	`HDR_DATA_w =`
81			`(PCK_INJ_Dw < HDR_DATA_w_tmp)? PCK_INJ_Dw :`
82			`(HDR_DATA_w_tmp==0)? 1: HDR_DATA_w_tmp;`
83	48	alirezamon
84			`wire [HDR_DATA_w-1 : 0] hdr_data_in = pck_injct_in.data [HDR_DATA_w-1 : 0];`
85			`wire [Fw-1 : 0] hdr_flit_out;`
86
87			`header_flit_generator #(`
88	54	alirezamon	`.DATA_w(HDR_DATA_w)`
89			`)`
90			`the_header_flit_generator`
91			`(`
92			`.flit_out (hdr_flit_out),`
93			`.vc_num_in (pck_injct_in.vc),`
94			`.class_in (pck_injct_in.class_num),`
95			`.dest_e_addr_in (pck_injct_in.endp_addr),`
96			`.src_e_addr_in (current_e_addr),`
97			`.weight_in (pck_injct_in.init_weight),`
98			`.destport_in (destport),`
99			`.data_in (hdr_data_in),`
100			`.be_in({BEw{1'b1}} )// Be is not used in simulation as we dont sent real data`
101			`);`
102	48	alirezamon
103
104			`localparam`
105			`REMAIN_DATw = PCK_INJ_Dw - HDR_DATA_w,`
106			`REMAIN_DAT_FLIT_I = (REMAIN_DATw / Fpay),`
107			`REMAIN_DAT_FLIT_F = (REMAIN_DATw % Fpay == 0)? 0 : 1,`
108			`REMAIN_DAT_FLIT = REMAIN_DAT_FLIT_I + REMAIN_DAT_FLIT_F,`
109			`CNTw = log2(REMAIN_DAT_FLIT),`
110			`MIN_PCK_SIZ = REMAIN_DAT_FLIT +1;`
111
112
113	54	alirezamon	`logic [PCK_SIZw-1 : 0] counter, counter_next;`
114			`logic [CNTw-1 : 0] counter2,counter2_next;`
115	48	alirezamon	`reg tail,head;`
116
117			`wire [Fpay -1 : 0] remain_dat [REMAIN_DAT_FLIT -1 : 0];`
118			`wire [Fpay-1 : 0] dataIn = remain_dat[counter2];`
119	54	alirezamon	`enum bit [2:0] {HEADER, BODY,TAIL} flit_type,flit_type_next;`
120	48	alirezamon
121
122
123			`wire [V-1 : 0] wr_vc_send = (flit_wr)? pck_injct_in.vc : {V{1'b0}};`
124			`wire [V-1 : 0] vc_fifo_full;`
125
126
127			`wire noc_ready;`
128
129			`localparam`
130			`LAST_TMP =PCK_INJ_Dw - (Fpay*REMAIN_DAT_FLIT_I)-HDR_DATA_w,`
131			`LASTw=(LAST_TMP==0)? Fpay : LAST_TMP;`
132			`genvar i;`
133			`generate`
134	54	alirezamon	`for(i=0; i`
135	48	alirezamon	`assign remain_dat [i] = pck_injct_in.data [Fpay(i+1)+HDR_DATA_w-1 : (Fpayi)+HDR_DATA_w];`
136			`end`
137	54	alirezamon	`if(REMAIN_DAT_FLIT_F ) begin :flt`
138	48	alirezamon
139			`assign remain_dat [REMAIN_DAT_FLIT_I][LASTw-1 : 0] = pck_injct_in.data [PCK_INJ_Dw-1 : (Fpay*REMAIN_DAT_FLIT_I)+HDR_DATA_w];`
140			`end`
141			`endgenerate`
142
143
144
145
146
147	54	alirezamon	`one_hot_mux #(`
148	48	alirezamon	`.IN_WIDTH (V ),`
149			`.SEL_WIDTH (V ),`
150			`.OUT_WIDTH (1 )`
151	54	alirezamon	`) one_hot_mux1 (`
152	48	alirezamon	`.mux_in (~ vc_fifo_full ),`
153			`.mux_out (noc_ready ),`
154			`.sel (pck_injct_in.vc ));`
155
156
157
158
159	54	alirezamon	`always @ (*) begin`
160			`counter_next = counter;`
161			`counter2_next =counter2;`
162			`flit_type_next =flit_type;`
163			`tail=1'b0;`
164			`head=1'b0;`
165			`flit_wr=0;`
166			`if(noc_ready)begin`
167			`case(flit_type)`
168			`HEADER:begin`
169			`if(pck_injct_in.pck_wr)begin`
170	48	alirezamon	`flit_wr=1;`
171	54	alirezamon	`counter_next = pck_injct_in.size-1;`
172			`counter2_next=0;`
173			`head=1'b1;`
174			`if(pck_injct_in.size == 1)begin`
175			`tail=1'b1;`
176			`end else if (pck_injct_in.size == 2) begin`
177	48	alirezamon	`flit_type_next = TAIL;`
178	54	alirezamon	`end else begin`
179			`flit_type_next = BODY;`
180			`end`
181	48	alirezamon	`end`
182	54	alirezamon	`end`
183			`BODY: begin`
184			`flit_wr=1;`
185			`counter_next = counter -1'b1;`
186			`counter2_next =counter2 +1'b1;`
187			`if(counter == 2) begin`
188			`flit_type_next = TAIL;`
189	48	alirezamon	`end`
190	54	alirezamon	`end`
191			`TAIL: begin`
192			`flit_type_next = HEADER;`
193			`flit_wr=1;`
194			`tail=1'b1;`
195			`end`
196			`default: begin`
197
198			`end`
199			`endcase`
200	48	alirezamon
201			`end`
202	54	alirezamon	`end`
203	48	alirezamon
204	54	alirezamon	`logic [V-1 : 0] credit_o, credit_o_next;`
205	48	alirezamon
206	54	alirezamon	`//pronoc_register #(.W(3),.RESET_TO(HEADER) ) reg1 (.in(flit_type_next ), .out(flit_type), .reset(reset), .clk(clk));`
207			`pronoc_register #(.W(PCK_SIZw)) reg2 (.in(counter_next ), .out(counter), .reset(reset), .clk(clk));`
208			`pronoc_register #(.W(CNTw)) reg3 (.in(counter2_next ), .out(counter2), .reset(reset), .clk(clk));`
209			`pronoc_register #(.W(V)) reg4 (.in(credit_o_next ), .out(credit_o), .reset(reset), .clk(clk));`
210	48	alirezamon
211	54	alirezamon
212			`always @ (*) begin`
213			`credit_o_next = credit_o;`
214			`if (chan_in.flit_chanel.flit_wr) credit_o_next = chan_in.flit_chanel.flit.vc;`
215			`else credit_o_next = {V{1'b0}};`
216			`end`
217
218			always @(`pronoc_clk_reset_edge)begin
219			if(`pronoc_reset) flit_type<=HEADER;
220			`else flit_type <= flit_type_next;`
221			`end`
222	48	alirezamon
223
224
225			`injector_ovc_status #(`
226	54	alirezamon	`.V(V),`
227			`.B(LB),`
228			`.CRDTw(CRDTw)`
229			`)`
230			`the_ovc_status`
231			`(`
232			`.credit_init_val_in ( chan_in.ctrl_chanel.credit_init_val),`
233			`.wr_in(wr_vc_send),`
234			`.credit_in(chan_in.flit_chanel.credit),`
235			`.full_vc(vc_fifo_full),`
236			`.nearly_full_vc( ),`
237			`.empty_vc( ),`
238			`.clk(clk),`
239			`.reset(reset)`
240			`);`
241	48	alirezamon
242
243
244
245
246
247
248			`wire [HDR_DATA_w-1 : 0] hdr_data_o;`
249			`hdr_flit_t hdr_flit_i;`
250
251			`header_flit_info`
252	54	alirezamon	`#(`
253			`.DATA_w (HDR_DATA_w )`
254			`) extractor (`
255			`.flit(chan_in.flit_chanel.flit),`
256			`.hdr_flit(hdr_flit_i),`
257			`.data_o(hdr_data_o)`
258			`);`
259	48	alirezamon
260			`wire [PCK_INJ_Dw-1 : 0] pck_data_o [V-1 : 0];`
261			`reg [Fpay-1 : 0] pck_data_o_gen [V-1 : 0][REMAIN_DAT_FLIT : 0];`
262
263			`genvar k;`
264
265			`reg [PCK_SIZw-1 : 0] rsv_counter [V-1 : 0];`
266			`reg [EAw-1 : 0] sender_endp_addr_reg [V-1 : 0];`
267			`logic [15:0] h2t_counter [V-1 : 0];`
268			`logic [15:0] h2t_counter_next [V-1 : 0];`
269
270
271
272			`//synthesis translate_off`
273			`wire [NEw-1 : 0] current_id;`
274			`wire [NEw-1 : 0] sendor_id;`
275			`endp_addr_decoder #( .TOPOLOGY(TOPOLOGY), .T1(T1), .T2(T2), .T3(T3), .EAw(EAw), .NE(NE)) encode1 ( .id(current_id), .code(current_e_addr));`
276	54	alirezamon	`endp_addr_decoder #( .TOPOLOGY(TOPOLOGY), .T1(T1), .T2(T2), .T3(T3), .EAw(EAw), .NE(NE)) encode2 ( .id(sendor_id), .code(pck_injct_out.endp_addr[EAw-1 : 0]));`
277	48	alirezamon	`//synthesis translate_on`
278
279	54	alirezamon	`wire [NE-1 :0] dest_mcast_all_endp;`
280	48	alirezamon
281	54	alirezamon
282
283
284	48	alirezamon	`generate`
285	54	alirezamon	`if(CAST_TYPE != "UNICAST") begin`
286			`mcast_dest_list_decode decode (`
287			`.dest_e_addr(hdr_flit_i.dest_e_addr),`
288			`.dest_o(dest_mcast_all_endp),`
289			`.row_has_any_dest(),`
290			`.is_unicast()`
291			`);`
292			`end`
293
294	48	alirezamon	`for(i=0; i`
295			`always@(*) begin`
296			`h2t_counter_next[i]=h2t_counter[i]+1'b1;`
297			`if(chan_in.flit_chanel.flit.vc[i] & chan_in.flit_chanel.flit_wr & chan_in.flit_chanel.flit.hdr_flag)begin`
298	54	alirezamon	`h2t_counter_next[i]= 16'd0; // reset once header flit is received`
299	48	alirezamon	`end//hdr flit wr`
300			`end//always`
301
302
303
304
305	54	alirezamon	always @ (`pronoc_clk_reset_edge )begin
306			if(`pronoc_reset) begin
307	48	alirezamon	`rsv_counter[i]<= {PCK_SIZw{1'b0}};`
308			`h2t_counter[i]<= 16'd0;`
309			`sender_endp_addr_reg [i]<= {EAw{1'b0}};`
310			`end else begin`
311			`h2t_counter[i]<=h2t_counter_next[i];`
312			`if(chan_in.flit_chanel.flit.vc[i] & chan_in.flit_chanel.flit_wr ) begin`
313			`if(chan_in.flit_chanel.flit.hdr_flag)begin`
314			`rsv_counter[i]<= {{(PCK_SIZw-1){1'b0}}, 1'b1};`
315			`sender_endp_addr_reg [i]<= hdr_flit_i.src_e_addr;`
316			`//synthesis translate_off`
317	54	alirezamon	`if(CAST_TYPE == "UNICAST") begin`
318			`if(hdr_flit_i.dest_e_addr[EAw-1:0] != current_e_addr) begin`
319			`$display("%t: ERROR: packet destination address %d does not match reciver endp address %d. %m",$time,hdr_flit_i.dest_e_addr , current_e_addr );`
320			`$finish;`
321			`end//if hdr_flit_i`
322			`end else begin`
323			`if(dest_mcast_all_endp[current_id] !=1'b1 ) begin`
324			`$display("%t: ERROR: packet destination address %b does not match reciver endp address %d. %m",$time,hdr_flit_i.dest_e_addr , current_e_addr ,current_id );`
325			`$finish;`
326			`end`
327	48	alirezamon	`end//if hdr_flit_i`
328			`//synthesis translate_on`
329			`end //if hdr_flag`
330			`else rsv_counter[i]<= rsv_counter[i]+1'b1;`
331			`end//flit wr`
332			`end//reset`
333			`end//always`
334
335
336
337
338			`for (k=0;k< REMAIN_DAT_FLIT+1;k++)begin : K_`
339
340	54	alirezamon	always @ (`pronoc_clk_reset_edge )begin
341			if(`pronoc_reset) begin
342	48	alirezamon	`pck_data_o_gen [i][k] <= {Fpay{1'b0}};`
343
344			`end else begin`
345			`if(chan_in.flit_chanel.flit.vc[i] & chan_in.flit_chanel.flit_wr ) begin`
346			`if (chan_in.flit_chanel.flit.hdr_flag )begin`
347			`if ( k ==0 ) pck_data_o_gen [i][k][HDR_DATA_w-1 : 0] <= hdr_data_o;`
348			`end`
349			`else begin`
350	54	alirezamon	`if (rsv_counter[i] == k ) pck_data_o_gen [i][k] <= chan_in.flit_chanel.flit.payload[Fpay-1 : 0];`
351	48	alirezamon
352			`end // else`
353			`end //if`
354			`end //else`
355			`end// always`
356
357	54	alirezamon	`if (k == 0 ) assign pck_data_o [i][HDR_DATA_w-1 : 0] = pck_data_o_gen [i][0][HDR_DATA_w-1 : 0];`
358			`else if (k == REMAIN_DAT_FLIT) assign pck_data_o [i][PCK_INJ_Dw-1 : (k-1)*Fpay+ HDR_DATA_w] = pck_data_o_gen [i][k][LASTw-1: 0];`
359			`else assign pck_data_o [i][(k)Fpay+HDR_DATA_w -1 : (k-1)Fpay+ HDR_DATA_w] = pck_data_o_gen [i][k];`
360	48	alirezamon
361			`end //for k`
362
363
364			`//synthesis translate_off`
365			`always @(posedge clk) begin`
366			`if((pck_injct_out.ready[i] == 1'b0 ) & pck_injct_in.vc[i] & pck_injct_in.pck_wr )begin`
367			`$display("%t: ERROR: a packet injection request is recived in core(%d), vc (%d) while packet injectore was not ready. %m",$time,current_id,i);`
368			`$finish;`
369			`end`
370
371			`end`
372			`//synthesis translate_on`
373
374
375
376
377			`end//for i`
378			`endgenerate`
379
380			`wire [V-1 : 0] vc_reg;`
381			`wire tail_flag_reg, hdr_flag_reg;`
382
383
384	54	alirezamon	`pronoc_register #(.W(V)) register1 (.in(chan_in.flit_chanel.flit.vc), .reset (reset ), .clk (clk),.out(vc_reg));`
385			`pronoc_register #(.W(1)) register2 (.in(chan_in.flit_chanel.flit.hdr_flag), .reset (reset ), .clk (clk),.out(hdr_flag_reg));`
386			`pronoc_register #(.W(1)) register3 (.in(chan_in.flit_chanel.flit.tail_flag & chan_in.flit_chanel.flit_wr ),.reset (reset ), .clk (clk),.out(tail_flag_reg));`
387	48	alirezamon
388			`wire [Vw-1 : 0] vc_bin;`
389
390			`one_hot_to_bin #(`
391	54	alirezamon	`.ONE_HOT_WIDTH (V),`
392			`.BIN_WIDTH (Vw )`
393			`) one_hot_to_bin (`
394			`.one_hot_code (vc_reg ),`
395			`.bin_code (vc_bin )`
396			`);`
397	48	alirezamon
398
399			`assign pck_injct_out.data = pck_data_o[vc_bin];`
400			`assign pck_injct_out.size = rsv_counter[vc_bin];`
401			`assign pck_injct_out.h2t_delay = h2t_counter[vc_bin];`
402			`assign pck_injct_out.ready = (flit_type == HEADER)? ~vc_fifo_full : {V{1'b0}};`
403	54	alirezamon	`assign pck_injct_out.endp_addr[EAw-1 : 0] = sender_endp_addr_reg[vc_bin];`
404	48	alirezamon	`assign pck_injct_out.vc = vc_reg;`
405			`assign pck_injct_out.pck_wr = tail_flag_reg;`
406
407			`assign chan_out.flit_chanel.flit.hdr_flag =head;`
408			`assign chan_out.flit_chanel.flit.tail_flag=tail;`
409			`assign chan_out.flit_chanel.flit.vc=pck_injct_in.vc;`
410			`assign chan_out.flit_chanel.flit_wr=flit_wr;`
411	54	alirezamon
412			`generate`
413			`/* verilator lint_off WIDTH */`
414			`if(PCK_TYPE == "SINGLE_FLIT" ) begin : single_f`
415			`/* verilator lint_on WIDTH */`
416			`assign chan_out.flit_chanel.flit.payload = hdr_flit_out[FPAYw-1 : 0];`
417			`end else begin`
418			`assign chan_out.flit_chanel.flit.payload = (flit_type== HEADER)? hdr_flit_out[Fpay-1 : 0] : dataIn;`
419			`end`
420			`endgenerate`
421
422	48	alirezamon	`assign chan_out.smart_chanel = {SMART_CHANEL_w{1'b0}};`
423			`assign chan_out.flit_chanel.congestion = {CONGw{1'b0}};`
424			`assign chan_out.flit_chanel.credit= credit_o;`
425			`assign chan_out.ctrl_chanel.credit_init_val= LB;`
426	54	alirezamon	`assign chan_out.ctrl_chanel.credit_release_en={V{1'b0}};`
427			`assign chan_out.ctrl_chanel.endp_port =1'b1;`
428	48	alirezamon
429
430
431			`distance_gen #(`
432			`.TOPOLOGY(TOPOLOGY),`
433			`.T1(T1),`
434			`.T2(T2),`
435			`.T3(T3),`
436			`.EAw(EAw),`
437			`.DISTw(DISTw)`
438			`)`
439			`the_distance_gen`
440			`(`
441			`.src_e_addr(sender_endp_addr_reg[vc_bin]),`
442			`.dest_e_addr(current_e_addr),`
443			`.distance(pck_injct_out.distance)`
444			`);`
445
446
447
448
449
450
451			`//synthesis translate_off`
452			//`define MONITOR_RSV_DAT
453
454
455
456			`always @(posedge clk) begin`
457			`if((pck_injct_in.vc == {V{1'b0}} ) & pck_injct_in.pck_wr )begin`
458			`$display("%t: ERROR: a packet injection request is recived while vc is not set. %m",$time);`
459			`$finish;`
460			`end`
461			`if(pck_injct_in.pck_wr && (pck_injct_in.size`
462			`$display("%t: ERROR: requested %d flit packet size is smaller than minimum %d flits to send %d bits of data. %m",$time,pck_injct_in.size,MIN_PCK_SIZ, PCK_INJ_Dw );`
463			`$finish;`
464			`end`
465
466			`ifdef MONITOR_RSV_DAT
467
468
469	54	alirezamon	`if(pck_injct_in.pck_wr) begin`
470			`$display ("pck_inj(%d) send a packet: size=%d, data=%h, v=%h",current_id,`
471			`pck_injct_in.size, pck_injct_in.data,pck_injct_in.vc);`
472			`end`
473	48	alirezamon
474	54	alirezamon	`if(pck_injct_out.pck_wr) begin`
475			`$display ("pck_inj(%d) got a packet: source=%d, size=%d, data=%h",current_id,`
476			`sendor_id,pck_injct_out.size,pck_injct_out.data);`
477			`end`
478	48	alirezamon
479
480			`endif
481
482			`end`
483
484
485			`//synthesis translate_on`
486
487
488
489
490
491			`endmodule`
492
493
494
495
496			`/******************`
497			`* ovc_status`
498			`*******************/`
499
500			`module injector_ovc_status #(`

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[/] [an-fpga-implementation-of-low-latency-noc-based-mpsoc/] [trunk/] [mpsoc/] [rtl/] [src_noc/] [packet_injector.sv] - Blame information for rev 54