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[/] [an-fpga-implementation-of-low-latency-noc-based-mpsoc/] [trunk/] [mpsoc/] [rtl/] [src_noc/] [router_top.sv] - Blame information for rev 48

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`timescale 1ns / 1ps
 
 
/****************************************************************************
 * router_top.v
 ****************************************************************************/
 
/**
 * Module: router_top
 *
 *  add optional bypass links to two stage router.
 */
module router_top
                import pronoc_pkg::*;
 
        # (
                parameter P = 5     // router port num
                )(
                        current_r_addr,// connected to constant parameter
 
                        chan_in,
                        chan_out,
 
                        clk,
                        reset
 
                );
 
 
        localparam DISABLED =P;
 
        input [RAw-1 :  0]  current_r_addr;
 
 
 
        input   smartflit_chanel_t chan_in [P-1 : 0];
        output  smartflit_chanel_t chan_out [P-1 : 0];
 
        input   clk,reset;
 
        genvar i,j;
 
 
        //synthesis translate_off
        //synopsys  translate_off
        /* verilator lint_off WIDTH */
        initial begin
                if((SSA_EN=="YES")  && (SMART_EN==1'b1) )begin
                        $display("ERROR: Only one of the SMART or SAA can be enabled at the same time");
                        $finish;
                end
                if((SMART_EN==1'b1) && COMBINATION_TYPE!="COMB_NONSPEC"  )begin
                        $display("ERROR: SMART only works with non-speculative VSA");
                        $finish;
                end
                if((MIN_PCK_SIZE > 1) && (PCK_TYPE == "SINGLE_FLIT")) begin
                        $display("ERROR: The minimum packet size must be set as one for single-flit packet type NoC");
                        $finish;
                end
        end
 
 
 
        logic report_active_ivcs = 0;
 
        generate
        for (i=0; i
                for (j=0; j
                always @ (posedge report_active_ivcs) begin
                        if(ivc_info[i][j].ivc_req) $display("%t : The IVC in router[%h] port[%d] VC [%d] is not empty",$time,current_r_addr,i,j);
                end
                end
        end
        endgenerate
 
        /* verilator lint_on WIDTH */
        //synopsys  translate_on
        //synthesis translate_on
 
 
 
 
 
        flit_chanel_t r2_chan_in  [P-1 : 0];
        flit_chanel_t r2_chan_out [P-1 : 0];
 
        ivc_info_t       ivc_info    [P-1 : 0][V-1 : 0];
        ovc_info_t   ovc_info    [P-1 : 0][V-1 : 0];
        iport_info_t iport_info  [P-1 : 0];
        oport_info_t oport_info  [P-1 : 0];
        smart_chanel_t smart_chanel_new  [P-1 : 0];
        smart_chanel_t smart_chanel_in   [P-1 : 0];
        smart_chanel_t smart_chanel_out  [P-1 : 0];
        smart_ctrl_t   smart_ctrl        [P-1 : 0];
 
 
        ctrl_chanel_t ctrl_in  [P-1 : 0];
        ctrl_chanel_t ctrl_out [P-1 : 0];
 
        generate
                for (i=0; i
                        assign  ctrl_in [i] = chan_in[i].ctrl_chanel;
                        assign  chan_out[i].ctrl_chanel= ctrl_out [i];
                end
        endgenerate
 
        // synthesis translate_off
 
        //header flit info, it is useful for debugin
        hdr_flit_t hdr_flit_i [P-1 : 0]; // the received packet header flit info
        hdr_flit_t hdr_flit_o [P-1 : 0]; // the sent packet header flit info
 
        generate
                for (i=0; i
 
 
 
                        header_flit_info in_extract(
                                        .flit(chan_in[i].flit_chanel.flit),
                                        .hdr_flit( hdr_flit_i[i]),
                                        .data_o()
                                );
 
                        header_flit_info out_extract(
                                        .flit(chan_out[i].flit_chanel.flit),
                                        .hdr_flit( hdr_flit_o[i]),
                                        .data_o()
                                );
 
                        if(DEBUG_EN) begin :dbg
                                check_flit_chanel_type_is_in_order #(
                                        .V(V),
                                        .PCK_TYPE(PCK_TYPE),
                                        .MIN_PCK_SIZE(MIN_PCK_SIZE)
                                )
                                IVC_flit_type_check
                                (
                                        .clk(clk),
                                        .reset(reset),
                                        .hdr_flg_in(chan_in[i].flit_chanel.flit.hdr_flag),
                                        .tail_flg_in(chan_in[i].flit_chanel.flit.tail_flag),
                                        .flit_in_wr(chan_in[i].flit_chanel.flit_wr),
                                        .vc_num_in(chan_in[i].flit_chanel.flit.vc)
                                );
 
                        end
 
 
                end
        endgenerate
        // synthesis translate_on
 
 
 
 
 
        wire [V-1 : 0] ovc_locally_requested [P-1 : 0];
        flit_chanel_t ss_flit_chanel [P-1 : 0]; //flit  bypass link goes to straight port
 
        router_two_stage  #(//r2
                        .P (P)
                )router_ref (
                        .ivc_info (ivc_info),
                        .ovc_info (ovc_info),
                        .iport_info (iport_info),
                        .oport_info (oport_info),
                        .smart_ctrl_in (smart_ctrl),
                        .current_r_addr(current_r_addr),
                        .chan_in  (r2_chan_in),
                        .chan_out (r2_chan_out),
                        .ctrl_in  (ctrl_in),
                        .ctrl_out (ctrl_out),
                        .clk (clk),
                        .reset (reset)
                );
 
        generate
 
                if(SMART_EN) begin :smart
 
 
                        smart_forward_ivc_info
                                #(
                                        .P(P)
                                )forward_ivc(
                                        .ivc_info(ivc_info),
                                        .iport_info(iport_info),
                                        .oport_info(oport_info),
                                        .smart_chanel(smart_chanel_new),
                                        .ovc_locally_requested(ovc_locally_requested),
                                        .reset(reset),
                                        .clk(clk)
                                );
 
                        smart_bypass_chanels
                                #(
                                        .P(P)
                                )smart_bypass(
                                        .ivc_info(ivc_info),
                                        .iport_info(iport_info),
                                        .oport_info(oport_info),
                                        .smart_chanel_new(smart_chanel_new),
                                        .smart_chanel_in(smart_chanel_in),
                                        .smart_chanel_out(smart_chanel_out),
                                        .smart_req( ),
                                        .reset(reset),
                                        .clk(clk)
                                );
 
                        wire  [RAw-1:  0]  neighbors_r_addr [P-1: 0];
                        wire  [V-1  :  0]  credit_out [P-1 : 0];
                        wire  [V-1  :  0]  ivc_smart_en [P-1 : 0];
                        for (i=0;i
                                localparam SS_PORT = strieght_port (P,i);
                                if(SS_PORT == DISABLED) begin: smart_dis
                                        assign r2_chan_in[i]   =  chan_in[i].flit_chanel;
                                        assign chan_out[i].flit_chanel     =  r2_chan_out[i];
                                        assign smart_ctrl[i]={SMART_CTRL_w{1'b0}};
                                end
                                else begin :smart_en
                                        assign neighbors_r_addr [i] = chan_in[i].ctrl_chanel.neighbors_r_addr;
                                        //smart allocator
                                        smart_allocator_per_iport #(
                                                        .P                         (P                        ),
                                                        .SW_LOC                    (i                                ),
                                                        .SS_PORT_LOC               (SS_PORT                      )
                                                ) smart_allocator(
                                                        .clk                       (clk                      ),
                                                        .reset                     (reset                    ),
                                                        .current_r_addr_i          (current_r_addr   ),
                                                        .neighbors_r_addr_i        (neighbors_r_addr         ),
                                                        .smart_chanel_i              (chan_in[i].smart_chanel    ),
                                                        .flit_chanel_i             (chan_in[i].flit_chanel   ),
                                                        .ivc_info                  (ivc_info[i]              ),
                                                        .ss_ovc_info               (ovc_info[SS_PORT]        ),
                                                        .ovc_locally_requested     (ovc_locally_requested[SS_PORT] ),
                                                        .ss_smart_chanel_new               (smart_chanel_new[SS_PORT]),
                                                        .ss_port_link_reg_flit_wr  (r2_chan_out[SS_PORT].flit_wr),
 
                                                        .smart_ivc_single_flit_pck_o   (smart_ctrl[i].ivc_single_flit_pck),
                                                        .smart_destport_o                                (smart_ctrl[i].destport     ),
                                                        .smart_lk_destport_o                     (smart_ctrl[i].lk_destport  ),
                                                        .smart_hdr_flit_req_o          (smart_ctrl[i].hdr_flit_req ),
                                                        .smart_ivc_smart_en_o                    (ivc_smart_en[i]   ),
                                                        .smart_credit_o                          (smart_ctrl[i].credit_out   ),
                                                        .smart_buff_space_decreased_o    (smart_ctrl[SS_PORT].buff_space_decreased),
                                                        .smart_ivc_num_getting_ovc_grant_o(smart_ctrl[i].ivc_num_getting_ovc_grant),
                                                        .smart_ivc_reset_o             (smart_ctrl[i].ivc_reset),
                                                        .smart_ivc_granted_ovc_num_o   (smart_ctrl[i].ivc_granted_ovc_num),
                                                        .smart_ovc_single_flit_pck_o   (smart_ctrl[SS_PORT].ovc_single_flit_pck),
                                                        .smart_ss_ovc_is_allocated_o     (smart_ctrl[SS_PORT].ovc_is_allocated),
                                                        .smart_ss_ovc_is_released_o      (smart_ctrl[SS_PORT].ovc_is_released),
                                                        .smart_mask_available_ss_ovc_o (smart_ctrl[SS_PORT].mask_available_ovc)
 
                                                );
 
                                        assign smart_ctrl[i].ivc_smart_en = ivc_smart_en[i];
                                        assign smart_ctrl[i].smart_en = |ivc_smart_en[i];
 
 
 
 
                                        // synthesis translate_off
                                        //assign chan_out[i].smart_chanel = (smart_chanel[i].requests[0]) ? smart_chanel_new[i] : take ss shifted smart;
                                        smart_chanel_check check (
                                                        .flit_chanel(chan_out[i].flit_chanel),
                                                        .smart_chanel(chan_out[i].smart_chanel),
                                                        .reset(reset),
                                                        .clk(clk)
                                                );
                                        // synthesis translate_on
 
                                        assign smart_chanel_in[i] =   chan_in[i].smart_chanel;
                                        assign chan_out[i].smart_chanel = smart_chanel_out[i];
 
                                        //r2 demux
                                        // flit_in_wr demux
                                        always @(*) begin
                                                //mask only flit_wr if smart_en is asserted
                                                r2_chan_in[i]   =  chan_in[i].flit_chanel;
                                                //can replace destport here and remove lk rout from internal router
                                                if (smart_ctrl[i].smart_en) r2_chan_in[i].flit_wr = 1'b0;
 
                                                //send flit_in to straight out port. Replace lk destport in header flit
                                                ss_flit_chanel[SS_PORT] = chan_in[i].flit_chanel;
                                                if(smart_ctrl[i].hdr_flit_req) ss_flit_chanel[SS_PORT].flit[DST_P_MSB : DST_P_LSB] =  smart_ctrl[i].lk_destport;
                                        end
 
                                        always @(*) begin
                                                // mux out flit channel
                                                chan_out[i].flit_chanel = r2_chan_out[i];
                                                chan_out[i].flit_chanel.credit    =  credit_out[i] ;
                                                if(smart_ctrl[SS_PORT].smart_en) begin
                                                        chan_out[i].flit_chanel.flit    =  ss_flit_chanel[i].flit;
                                                        chan_out[i].flit_chanel.flit_wr =  ss_flit_chanel[i].flit_wr;
 
                                                end
                                        end
 
                                        smart_credit_manage #(
                                                        .V             (V             ),
                                                        .B             (B            )
                                                ) smart_credit_manage (
                                                        .credit_in      (r2_chan_out[i].credit     ),
                                                        .smart_credit_in  (smart_ctrl[i].credit_out ),
                                                        .credit_out     ( credit_out[i]   ),
                                                        .reset          (reset         ),
                                                        .clk            (clk           ));
 
 
 
                                end //for
                        end//smart_en
 
 
 
                end else begin :no_smart
                        for (i=0;i
                                assign r2_chan_in[i]   =  chan_in[i].flit_chanel;
                                assign chan_out[i].flit_chanel     =  r2_chan_out[i];
                                assign smart_ctrl[i]={SMART_CTRL_w{1'b0}};
                        end//for
                end
        endgenerate
 
 
//`ifdef VERILATOR
//      logic  nb_router_active [P-1 : 0] /*verilator public_flat_rd*/ ;
//      logic  router_is_ideal /*verilator public_flat_rd*/ ;
//      logic  not_ideal_next,not_ideal;
//      integer ii,jj;
//      always @ (*) begin
//              router_is_ideal = 1'b1;
//              not_ideal_next  = 1'b0;
//              for (ii=0; ii
//                      nb_router_active[ii]= 1'b0;
//                      if (chan_out[ii].flit_chanel.flit_wr) nb_router_active[ii]=1'b1;
//                      if (chan_out[ii].flit_chanel.credit > {V{1'b0}} ) nb_router_active[ii]=1'b1;
//                      if (chan_out[ii].smart_chanel.requests > {SMART_NUM{1'b0}} ) nb_router_active[ii]=1'b1;
//
//                      for (jj=0; jj
//                              //no active request is in any input queues
//                              if(ivc_info[ii][jj].ivc_req)begin
//                                      router_is_ideal=1'b0;
//                                      not_ideal_next=1'b1;
//                              end
//                      end
//                      //no output flit wr
//                      if (r2_chan_out[ii].flit_wr)  router_is_ideal=1'b0;
//              end
//              if (not_ideal) router_is_ideal =1'b0; // delay one clock cycle if the input req exist in last clock cycle bot not on the current one
//      end
//      register #(     .W(1)) no_ideal_register (.in(not_ideal_next), .reset (reset),  .clk(clk), .out (not_ideal));
//`endif
 
 
 
endmodule
 
 
 
module router_top_v //to be used as top module in veralator
                import pronoc_pkg::*;
 
        # (
                parameter P = 5     // router port num
                )(
                        current_r_addr,
 
                        chan_in,
                        chan_out,
 
                        clk,
                        reset
 
                );
 
 
 
        input  [RAw-1 : 0] current_r_addr;
 
        input   smartflit_chanel_t chan_in [P-1 : 0];
        output  smartflit_chanel_t chan_out [P-1 : 0];
        input reset,clk;
 
        router_top # (
                        .P(P)
                )
                router
                (
                        .current_r_addr(current_r_addr),
                        .chan_in (chan_in),
                        .chan_out(chan_out),
                        .clk(clk),
                        .reset(reset)
                );
 
 
endmodule
 
 

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[/] [an-fpga-implementation-of-low-latency-noc-based-mpsoc/] [trunk/] [mpsoc/] [rtl/] [src_noc/] [router_top.sv] - Blame information for rev 48

Line No.	Rev	Author	Line
1	48	alirezamon	`timescale 1ns / 1ps
2
3
4			`/****************************************************************************`
5			`* router_top.v`
6			`****************************************************************************/`
7
8			`/**`
9			`* Module: router_top`
10			`*`
11			`* add optional bypass links to two stage router.`
12			`*/`
13			`module router_top`
14			`import pronoc_pkg::*;`
15
16			`# (`
17			`parameter P = 5 // router port num`
18			`)(`
19			`current_r_addr,// connected to constant parameter`
20
21			`chan_in,`
22			`chan_out,`
23
24			`clk,`
25			`reset`
26
27			`);`
28
29
30			`localparam DISABLED =P;`
31
32			`input [RAw-1 : 0] current_r_addr;`
33
34
35
36			`input smartflit_chanel_t chan_in [P-1 : 0];`
37			`output smartflit_chanel_t chan_out [P-1 : 0];`
38
39			`input clk,reset;`
40
41			`genvar i,j;`
42
43
44			`//synthesis translate_off`
45			`//synopsys translate_off`
46			`/* verilator lint_off WIDTH */`
47			`initial begin`
48			`if((SSA_EN=="YES") && (SMART_EN==1'b1) )begin`
49			`$display("ERROR: Only one of the SMART or SAA can be enabled at the same time");`
50			`$finish;`
51			`end`
52			`if((SMART_EN==1'b1) && COMBINATION_TYPE!="COMB_NONSPEC" )begin`
53			`$display("ERROR: SMART only works with non-speculative VSA");`
54			`$finish;`
55			`end`
56			`if((MIN_PCK_SIZE > 1) && (PCK_TYPE == "SINGLE_FLIT")) begin`
57			`$display("ERROR: The minimum packet size must be set as one for single-flit packet type NoC");`
58			`$finish;`
59			`end`
60			`end`
61
62
63
64			`logic report_active_ivcs = 0;`
65
66			`generate`
67			`for (i=0; i`
68			`for (j=0; j`
69			`always @ (posedge report_active_ivcs) begin`
70			`if(ivc_info[i][j].ivc_req) $display("%t : The IVC in router[%h] port[%d] VC [%d] is not empty",$time,current_r_addr,i,j);`
71			`end`
72			`end`
73			`end`
74			`endgenerate`
75
76			`/* verilator lint_on WIDTH */`
77			`//synopsys translate_on`
78			`//synthesis translate_on`
79
80
81
82
83
84			`flit_chanel_t r2_chan_in [P-1 : 0];`
85			`flit_chanel_t r2_chan_out [P-1 : 0];`
86
87			`ivc_info_t ivc_info [P-1 : 0][V-1 : 0];`
88			`ovc_info_t ovc_info [P-1 : 0][V-1 : 0];`
89			`iport_info_t iport_info [P-1 : 0];`
90			`oport_info_t oport_info [P-1 : 0];`
91			`smart_chanel_t smart_chanel_new [P-1 : 0];`
92			`smart_chanel_t smart_chanel_in [P-1 : 0];`
93			`smart_chanel_t smart_chanel_out [P-1 : 0];`
94			`smart_ctrl_t smart_ctrl [P-1 : 0];`
95
96
97			`ctrl_chanel_t ctrl_in [P-1 : 0];`
98			`ctrl_chanel_t ctrl_out [P-1 : 0];`
99
100			`generate`
101			`for (i=0; i`
102			`assign ctrl_in [i] = chan_in[i].ctrl_chanel;`
103			`assign chan_out[i].ctrl_chanel= ctrl_out [i];`
104			`end`
105			`endgenerate`
106
107			`// synthesis translate_off`
108
109			`//header flit info, it is useful for debugin`
110			`hdr_flit_t hdr_flit_i [P-1 : 0]; // the received packet header flit info`
111			`hdr_flit_t hdr_flit_o [P-1 : 0]; // the sent packet header flit info`
112
113			`generate`
114			`for (i=0; i`
115
116
117
118			`header_flit_info in_extract(`
119			`.flit(chan_in[i].flit_chanel.flit),`
120			`.hdr_flit( hdr_flit_i[i]),`
121			`.data_o()`
122			`);`
123
124			`header_flit_info out_extract(`
125			`.flit(chan_out[i].flit_chanel.flit),`
126			`.hdr_flit( hdr_flit_o[i]),`
127			`.data_o()`
128			`);`
129
130			`if(DEBUG_EN) begin :dbg`
131			`check_flit_chanel_type_is_in_order #(`
132			`.V(V),`
133			`.PCK_TYPE(PCK_TYPE),`
134			`.MIN_PCK_SIZE(MIN_PCK_SIZE)`
135			`)`
136			`IVC_flit_type_check`
137			`(`
138			`.clk(clk),`
139			`.reset(reset),`
140			`.hdr_flg_in(chan_in[i].flit_chanel.flit.hdr_flag),`
141			`.tail_flg_in(chan_in[i].flit_chanel.flit.tail_flag),`
142			`.flit_in_wr(chan_in[i].flit_chanel.flit_wr),`
143			`.vc_num_in(chan_in[i].flit_chanel.flit.vc)`
144			`);`
145
146			`end`
147
148
149			`end`
150			`endgenerate`
151			`// synthesis translate_on`
152
153
154
155
156
157			`wire [V-1 : 0] ovc_locally_requested [P-1 : 0];`
158			`flit_chanel_t ss_flit_chanel [P-1 : 0]; //flit bypass link goes to straight port`
159
160			`router_two_stage #(//r2`
161			`.P (P)`
162			`)router_ref (`
163			`.ivc_info (ivc_info),`
164			`.ovc_info (ovc_info),`
165			`.iport_info (iport_info),`
166			`.oport_info (oport_info),`
167			`.smart_ctrl_in (smart_ctrl),`
168			`.current_r_addr(current_r_addr),`
169			`.chan_in (r2_chan_in),`
170			`.chan_out (r2_chan_out),`
171			`.ctrl_in (ctrl_in),`
172			`.ctrl_out (ctrl_out),`
173			`.clk (clk),`
174			`.reset (reset)`
175			`);`
176
177			`generate`
178
179			`if(SMART_EN) begin :smart`
180
181
182			`smart_forward_ivc_info`
183			`#(`
184			`.P(P)`
185			`)forward_ivc(`
186			`.ivc_info(ivc_info),`
187			`.iport_info(iport_info),`
188			`.oport_info(oport_info),`
189			`.smart_chanel(smart_chanel_new),`
190			`.ovc_locally_requested(ovc_locally_requested),`
191			`.reset(reset),`
192			`.clk(clk)`
193			`);`
194
195			`smart_bypass_chanels`
196			`#(`
197			`.P(P)`
198			`)smart_bypass(`
199			`.ivc_info(ivc_info),`
200			`.iport_info(iport_info),`
201			`.oport_info(oport_info),`
202			`.smart_chanel_new(smart_chanel_new),`
203			`.smart_chanel_in(smart_chanel_in),`
204			`.smart_chanel_out(smart_chanel_out),`
205			`.smart_req( ),`
206			`.reset(reset),`
207			`.clk(clk)`
208			`);`
209
210			`wire [RAw-1: 0] neighbors_r_addr [P-1: 0];`
211			`wire [V-1 : 0] credit_out [P-1 : 0];`
212			`wire [V-1 : 0] ivc_smart_en [P-1 : 0];`
213			`for (i=0;i`
214			`localparam SS_PORT = strieght_port (P,i);`
215			`if(SS_PORT == DISABLED) begin: smart_dis`
216			`assign r2_chan_in[i] = chan_in[i].flit_chanel;`
217			`assign chan_out[i].flit_chanel = r2_chan_out[i];`
218			`assign smart_ctrl[i]={SMART_CTRL_w{1'b0}};`
219			`end`
220			`else begin :smart_en`
221			`assign neighbors_r_addr [i] = chan_in[i].ctrl_chanel.neighbors_r_addr;`
222			`//smart allocator`
223			`smart_allocator_per_iport #(`
224			`.P (P ),`
225			`.SW_LOC (i ),`
226			`.SS_PORT_LOC (SS_PORT )`
227			`) smart_allocator(`
228			`.clk (clk ),`
229			`.reset (reset ),`
230			`.current_r_addr_i (current_r_addr ),`
231			`.neighbors_r_addr_i (neighbors_r_addr ),`
232			`.smart_chanel_i (chan_in[i].smart_chanel ),`
233			`.flit_chanel_i (chan_in[i].flit_chanel ),`
234			`.ivc_info (ivc_info[i] ),`
235			`.ss_ovc_info (ovc_info[SS_PORT] ),`
236			`.ovc_locally_requested (ovc_locally_requested[SS_PORT] ),`
237			`.ss_smart_chanel_new (smart_chanel_new[SS_PORT]),`
238			`.ss_port_link_reg_flit_wr (r2_chan_out[SS_PORT].flit_wr),`
239
240			`.smart_ivc_single_flit_pck_o (smart_ctrl[i].ivc_single_flit_pck),`
241			`.smart_destport_o (smart_ctrl[i].destport ),`
242			`.smart_lk_destport_o (smart_ctrl[i].lk_destport ),`
243			`.smart_hdr_flit_req_o (smart_ctrl[i].hdr_flit_req ),`
244			`.smart_ivc_smart_en_o (ivc_smart_en[i] ),`
245			`.smart_credit_o (smart_ctrl[i].credit_out ),`
246			`.smart_buff_space_decreased_o (smart_ctrl[SS_PORT].buff_space_decreased),`
247			`.smart_ivc_num_getting_ovc_grant_o(smart_ctrl[i].ivc_num_getting_ovc_grant),`
248			`.smart_ivc_reset_o (smart_ctrl[i].ivc_reset),`
249			`.smart_ivc_granted_ovc_num_o (smart_ctrl[i].ivc_granted_ovc_num),`
250			`.smart_ovc_single_flit_pck_o (smart_ctrl[SS_PORT].ovc_single_flit_pck),`
251			`.smart_ss_ovc_is_allocated_o (smart_ctrl[SS_PORT].ovc_is_allocated),`
252			`.smart_ss_ovc_is_released_o (smart_ctrl[SS_PORT].ovc_is_released),`
253			`.smart_mask_available_ss_ovc_o (smart_ctrl[SS_PORT].mask_available_ovc)`
254
255			`);`
256
257			`assign smart_ctrl[i].ivc_smart_en = ivc_smart_en[i];`
258			`assign smart_ctrl[i].smart_en = \|ivc_smart_en[i];`
259
260
261
262
263			`// synthesis translate_off`
264			`//assign chan_out[i].smart_chanel = (smart_chanel[i].requests[0]) ? smart_chanel_new[i] : take ss shifted smart;`
265			`smart_chanel_check check (`
266			`.flit_chanel(chan_out[i].flit_chanel),`
267			`.smart_chanel(chan_out[i].smart_chanel),`
268			`.reset(reset),`
269			`.clk(clk)`
270			`);`
271			`// synthesis translate_on`
272
273			`assign smart_chanel_in[i] = chan_in[i].smart_chanel;`
274			`assign chan_out[i].smart_chanel = smart_chanel_out[i];`
275
276			`//r2 demux`
277			`// flit_in_wr demux`
278			`always @(*) begin`
279			`//mask only flit_wr if smart_en is asserted`
280			`r2_chan_in[i] = chan_in[i].flit_chanel;`
281			`//can replace destport here and remove lk rout from internal router`
282			`if (smart_ctrl[i].smart_en) r2_chan_in[i].flit_wr = 1'b0;`
283
284			`//send flit_in to straight out port. Replace lk destport in header flit`
285			`ss_flit_chanel[SS_PORT] = chan_in[i].flit_chanel;`
286			`if(smart_ctrl[i].hdr_flit_req) ss_flit_chanel[SS_PORT].flit[DST_P_MSB : DST_P_LSB] = smart_ctrl[i].lk_destport;`
287			`end`
288
289			`always @(*) begin`
290			`// mux out flit channel`
291			`chan_out[i].flit_chanel = r2_chan_out[i];`
292			`chan_out[i].flit_chanel.credit = credit_out[i] ;`
293			`if(smart_ctrl[SS_PORT].smart_en) begin`
294			`chan_out[i].flit_chanel.flit = ss_flit_chanel[i].flit;`
295			`chan_out[i].flit_chanel.flit_wr = ss_flit_chanel[i].flit_wr;`
296
297			`end`
298			`end`
299
300			`smart_credit_manage #(`
301			`.V (V ),`
302			`.B (B )`
303			`) smart_credit_manage (`
304			`.credit_in (r2_chan_out[i].credit ),`
305			`.smart_credit_in (smart_ctrl[i].credit_out ),`
306			`.credit_out ( credit_out[i] ),`
307			`.reset (reset ),`
308			`.clk (clk ));`
309
310
311
312			`end //for`
313			`end//smart_en`
314
315
316
317			`end else begin :no_smart`
318			`for (i=0;i`
319			`assign r2_chan_in[i] = chan_in[i].flit_chanel;`
320			`assign chan_out[i].flit_chanel = r2_chan_out[i];`
321			`assign smart_ctrl[i]={SMART_CTRL_w{1'b0}};`
322			`end//for`
323			`end`
324			`endgenerate`
325
326
327			//`ifdef VERILATOR
328			`// logic nb_router_active [P-1 : 0] /verilator public_flat_rd/ ;`
329			`// logic router_is_ideal /verilator public_flat_rd/ ;`
330			`// logic not_ideal_next,not_ideal;`
331			`// integer ii,jj;`
332			`// always @ (*) begin`
333			`// router_is_ideal = 1'b1;`
334			`// not_ideal_next = 1'b0;`
335			`// for (ii=0; ii`
336			`// nb_router_active[ii]= 1'b0;`
337			`// if (chan_out[ii].flit_chanel.flit_wr) nb_router_active[ii]=1'b1;`
338			`// if (chan_out[ii].flit_chanel.credit > {V{1'b0}} ) nb_router_active[ii]=1'b1;`
339			`// if (chan_out[ii].smart_chanel.requests > {SMART_NUM{1'b0}} ) nb_router_active[ii]=1'b1;`
340			`//`
341			`// for (jj=0; jj`
342			`// //no active request is in any input queues`
343			`// if(ivc_info[ii][jj].ivc_req)begin`
344			`// router_is_ideal=1'b0;`
345			`// not_ideal_next=1'b1;`
346			`// end`
347			`// end`
348			`// //no output flit wr`
349			`// if (r2_chan_out[ii].flit_wr) router_is_ideal=1'b0;`
350			`// end`
351			`// if (not_ideal) router_is_ideal =1'b0; // delay one clock cycle if the input req exist in last clock cycle bot not on the current one`
352			`// end`
353			`// register #( .W(1)) no_ideal_register (.in(not_ideal_next), .reset (reset), .clk(clk), .out (not_ideal));`
354			//`endif
355
356
357
358			`endmodule`
359
360
361
362			`module router_top_v //to be used as top module in veralator`
363			`import pronoc_pkg::*;`
364
365			`# (`
366			`parameter P = 5 // router port num`
367			`)(`
368			`current_r_addr,`
369
370			`chan_in,`
371			`chan_out,`
372
373			`clk,`
374			`reset`
375
376			`);`
377
378
379
380			`input [RAw-1 : 0] current_r_addr;`
381
382			`input smartflit_chanel_t chan_in [P-1 : 0];`
383			`output smartflit_chanel_t chan_out [P-1 : 0];`
384			`input reset,clk;`
385
386			`router_top # (`
387			`.P(P)`
388			`)`
389			`router`
390			`(`
391			`.current_r_addr(current_r_addr),`
392			`.chan_in (chan_in),`
393			`.chan_out(chan_out),`
394			`.clk(clk),`
395			`.reset(reset)`
396			`);`
397
398
399			`endmodule`
400
401