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[/] [an-fpga-implementation-of-low-latency-noc-based-mpsoc/] [trunk/] [mpsoc/] [rtl/] [src_noc/] [router_top.sv] - Blame information for rev 54

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`include "pronoc_def.v"
 
 
/****************************************************************************
 * router_top.v
 ****************************************************************************/
 
/**
 * Module: router_top
 *
 *  add optional bypass links to two stage router.
 */
module router_top
                import pronoc_pkg::*;
 
        # (
                parameter P = 5     // router port num
                )(
                        current_r_id,
                        current_r_addr,
 
                        chan_in,
                        chan_out,
 
                        router_event,
 
                        clk,
                        reset
 
                );
 
 
        localparam DISABLED =P;
 
        input [RAw-1 :  0]  current_r_addr;
        input [31 : 0] current_r_id;
 
 
        input   smartflit_chanel_t chan_in [P-1 : 0];
        output  smartflit_chanel_t chan_out [P-1 : 0];
 
        output router_event_t router_event [P-1 : 0];
 
 
 
        input   clk,reset;
 
        genvar i,j;
 
 
        //synthesis translate_off
        //synopsys  translate_off
        /* verilator lint_off WIDTH */
        initial begin
                if((SSA_EN=="YES")  && (SMART_EN==1'b1) )begin
                        $display("ERROR: Only one of the SMART or SAA can be enabled at the same time");
                        $finish;
                end
                if((SMART_EN==1'b1) && COMBINATION_TYPE!="COMB_NONSPEC"  )begin
                        $display("ERROR: SMART only works with non-speculative VSA");
                        $finish;
                end
                if((MIN_PCK_SIZE > 1) && (PCK_TYPE == "SINGLE_FLIT")) begin
                        $display("ERROR: The minimum packet size must be set as one for single-flit packet type NoC");
                        $finish;
                end
                if(((SSA_EN=="YES")  || (SMART_EN==1'b1) ) && CAST_TYPE!="UNICAST") begin
                        $display("ERROR: SMART or SAA do not support muticast/braodcast packets");
                        $finish;
                end
 
        end
        /* verilator lint_on WIDTH */
 
 
 
 
 
        logic report_active_ivcs = 0;
 
        generate
        for (i=0; i
                for (j=0; j
                        always @ (posedge report_active_ivcs) begin
                                if(ivc_info[i][j].ivc_req) $display("%t : The IVC in router[%h] port[%d] VC [%d] is not empty",$time,current_r_addr,i,j);
                        end
                end
        end
        endgenerate
 
        //synopsys  translate_on
        //synthesis translate_on
 
 
 
        generate
        for (i=0; i
                assign router_event[i].flit_wr_i = chan_in[i].flit_chanel.flit_wr;
                assign router_event[i].bypassed_num = chan_in[i].smart_chanel.bypassed_num;
                assign router_event[i].pck_wr_i  = chan_in[i].flit_chanel.flit_wr & chan_in[i].flit_chanel.flit.hdr_flag;
                assign router_event[i].flit_wr_o = chan_out[i].flit_chanel.flit_wr;
                assign router_event[i].pck_wr_o  = chan_out[i].flit_chanel.flit_wr & chan_out[i].flit_chanel.flit.hdr_flag;
                assign router_event[i].flit_in_bypassed = chan_out[i].smart_chanel.flit_in_bypassed;
 
        end
        endgenerate
 
 
 
 
 
 
        flit_chanel_t r2_chan_in  [P-1 : 0];
        flit_chanel_t r2_chan_out [P-1 : 0];
 
        ivc_info_t       ivc_info    [P-1 : 0][V-1 : 0];
        ovc_info_t   ovc_info    [P-1 : 0][V-1 : 0];
        iport_info_t iport_info  [P-1 : 0];
        oport_info_t oport_info  [P-1 : 0];
        smart_chanel_t smart_chanel_new  [P-1 : 0];
        smart_chanel_t smart_chanel_in   [P-1 : 0];
        smart_chanel_t smart_chanel_out  [P-1 : 0];
        smart_ctrl_t   smart_ctrl        [P-1 : 0];
 
 
        ctrl_chanel_t ctrl_in  [P-1 : 0];
        ctrl_chanel_t ctrl_out [P-1 : 0];
 
        generate
                for (i=0; i
                        assign  ctrl_in [i] = chan_in[i].ctrl_chanel;
                        assign  chan_out[i].ctrl_chanel= ctrl_out [i];
 
                end
        endgenerate
 
        // synthesis translate_off
 
        //header flit info, it is useful for debugin
        hdr_flit_t hdr_flit_i [P-1 : 0]; // the received packet header flit info
        hdr_flit_t hdr_flit_o [P-1 : 0]; // the sent packet header flit info
 
        generate
                for (i=0; i
 
 
 
                        header_flit_info in_extract(
                                        .flit(chan_in[i].flit_chanel.flit),
                                        .hdr_flit( hdr_flit_i[i]),
                                        .data_o()
                                );
 
                        header_flit_info out_extract(
                                        .flit(chan_out[i].flit_chanel.flit),
                                        .hdr_flit( hdr_flit_o[i]),
                                        .data_o()
                                );
 
                        if(DEBUG_EN) begin :dbg
                                check_flit_chanel_type_is_in_order #(
                                        .V(V),
                                        .PCK_TYPE(PCK_TYPE),
                                        .MIN_PCK_SIZE(MIN_PCK_SIZE)
                                )
                                IVC_flit_type_check
                                (
                                        .clk(clk),
                                        .reset(reset),
                                        .hdr_flg_in(chan_in[i].flit_chanel.flit.hdr_flag),
                                        .tail_flg_in(chan_in[i].flit_chanel.flit.tail_flag),
                                        .flit_in_wr(chan_in[i].flit_chanel.flit_wr),
                                        .vc_num_in(chan_in[i].flit_chanel.flit.vc)
                                );
 
                                check_pck_size #(
                                                .V(V),
                                                .MIN_PCK_SIZE(MIN_PCK_SIZE),
                                                .Fw(Fw),
                                                .DAw(DAw),
                                                .CAST_TYPE(CAST_TYPE),
                                                .NE(NE),
                                                .B(B),
                                                .LB(LB)
                                        )
                                        check_pck_siz
                                        (
                                                .clk(clk),
                                                .reset(reset),
                                                .hdr_flg_in(chan_in[i].flit_chanel.flit.hdr_flag),
                                                .tail_flg_in(chan_in[i].flit_chanel.flit.tail_flag),
                                                .flit_in_wr(chan_in[i].flit_chanel.flit_wr),
                                                .vc_num_in(chan_in[i].flit_chanel.flit.vc),
                                                .dest_e_addr_in(chan_in[i].flit_chanel.flit.payload[E_DST_MSB : E_DST_LSB])
                                        );
 
 
                        end
 
 
                end
        endgenerate
        // synthesis translate_on
 
 
 
 
 
        wire [V-1 : 0] ovc_locally_requested [P-1 : 0];
        flit_chanel_t ss_flit_chanel [P-1 : 0]; //flit  bypass link goes to straight port
 
        router_two_stage  #(//r2
                        .P (P)
                )router_ref (
                        .ivc_info (ivc_info),
                        .ovc_info (ovc_info),
                        .iport_info (iport_info),
                        .oport_info (oport_info),
                        .smart_ctrl_in (smart_ctrl),
                        .current_r_addr(current_r_addr),
                        .current_r_id(current_r_id),
                        .chan_in  (r2_chan_in),
                        .chan_out (r2_chan_out),
                        .ctrl_in  (ctrl_in),
                        .ctrl_out (ctrl_out),
                        .clk (clk),
                        .reset (reset)
                );
 
        generate
 
                if(SMART_EN) begin :smart
 
 
                        smart_forward_ivc_info
                                #(
                                        .P(P)
                                )forward_ivc(
                                        .ivc_info(ivc_info),
                                        .iport_info(iport_info),
                                        .oport_info(oport_info),
                                        .smart_chanel(smart_chanel_new),
                                        .ovc_locally_requested(ovc_locally_requested),
                                        .reset(reset),
                                        .clk(clk)
                                );
 
                        smart_bypass_chanels
                                #(
                                        .P(P)
                                )smart_bypass(
                                        .ivc_info(ivc_info),
                                        .iport_info(iport_info),
                                        .oport_info(oport_info),
                                        .smart_chanel_new(smart_chanel_new),
                                        .smart_chanel_in(smart_chanel_in),
                                        .smart_chanel_out(smart_chanel_out),
                                        .smart_req( ),
                                        .reset(reset),
                                        .clk(clk)
                                );
 
                        wire  [RAw-1:  0]  neighbors_r_addr [P-1: 0];
                        wire  [V-1  :  0]  credit_out [P-1 : 0];
                        wire  [V-1  :  0]  ivc_smart_en [P-1 : 0];
                        for (i=0;i
                                localparam SS_PORT = strieght_port (P,i);
                                if(SS_PORT == DISABLED) begin: smart_dis
                                        assign r2_chan_in[i]   =  chan_in[i].flit_chanel;
                                        assign chan_out[i].flit_chanel     =  r2_chan_out[i];
                                        assign smart_ctrl[i]={SMART_CTRL_w{1'b0}};
                                end
                                else begin :smart_en
                                        assign neighbors_r_addr [i] = chan_in[i].ctrl_chanel.neighbors_r_addr;
                                        //smart allocator
                                        smart_allocator_per_iport #(
                                                        .P                         (P                        ),
                                                        .SW_LOC                    (i                                ),
                                                        .SS_PORT_LOC               (SS_PORT                      )
                                                ) smart_allocator(
                                                        .clk                       (clk                      ),
                                                        .reset                     (reset                    ),
                                                        .current_r_addr_i          (current_r_addr   ),
                                                        .neighbors_r_addr_i        (neighbors_r_addr         ),
                                                        .smart_chanel_i            (chan_in[i].smart_chanel    ),
                                                        .flit_chanel_i             (chan_in[i].flit_chanel   ),
                                                        .ivc_info                  (ivc_info[i]              ),
                                                        .ss_ovc_info               (ovc_info[SS_PORT]        ),
                                                        .ovc_locally_requested     (ovc_locally_requested[SS_PORT] ),
                                                        .ss_smart_chanel_new               (smart_chanel_new[SS_PORT]),
                                                        .ss_port_link_reg_flit_wr  (r2_chan_out[SS_PORT].flit_wr),
 
                                                        .smart_ivc_single_flit_pck_o   (smart_ctrl[i].ivc_single_flit_pck),
                                                        .smart_destport_o                                (smart_ctrl[i].destport     ),
                                                        .smart_lk_destport_o                     (smart_ctrl[i].lk_destport  ),
                                                        .smart_hdr_flit_req_o          (smart_ctrl[i].hdr_flit_req ),
                                                        .smart_ivc_smart_en_o                    (ivc_smart_en[i]   ),
                                                        .smart_credit_o                          (smart_ctrl[i].credit_out   ),
                                                        .smart_buff_space_decreased_o    (smart_ctrl[SS_PORT].buff_space_decreased),
                                                        .smart_ivc_num_getting_ovc_grant_o(smart_ctrl[i].ivc_num_getting_ovc_grant),
                                                        .smart_ivc_reset_o             (smart_ctrl[i].ivc_reset),
                                                        .smart_ivc_granted_ovc_num_o   (smart_ctrl[i].ivc_granted_ovc_num),
                                                        .smart_ovc_single_flit_pck_o   (smart_ctrl[SS_PORT].ovc_single_flit_pck),
                                                        .smart_ss_ovc_is_allocated_o     (smart_ctrl[SS_PORT].ovc_is_allocated),
                                                        .smart_ss_ovc_is_released_o      (smart_ctrl[SS_PORT].ovc_is_released),
                                                        .smart_mask_available_ss_ovc_o (smart_ctrl[SS_PORT].mask_available_ovc)
 
                                                );
 
                                        assign smart_ctrl[i].ivc_smart_en = ivc_smart_en[i];
                                        assign smart_ctrl[i].smart_en = |ivc_smart_en[i];
 
 
 
 
                                        // synthesis translate_off
                                        //assign chan_out[i].smart_chanel = (smart_chanel[i].requests[0]) ? smart_chanel_new[i] : take ss shifted smart;
                                        smart_chanel_check check (
                                                        .flit_chanel(chan_out[i].flit_chanel),
                                                        .smart_chanel(chan_out[i].smart_chanel),
                                                        .reset(reset),
                                                        .clk(clk)
                                                );
                                        // synthesis translate_on
 
                                        assign smart_chanel_in[i] =   chan_in[i].smart_chanel;
 
 
                                        //r2 demux
                                        // flit_in_wr demux
                                        always @(*) begin
                                                chan_out[i].smart_chanel = smart_chanel_out[i];
                                                chan_out[i].smart_chanel.flit_in_bypassed =smart_ctrl[i].smart_en & chan_in[i].flit_chanel.flit_wr ;
 
 
                                                //mask only flit_wr if smart_en is asserted
                                                r2_chan_in[i]   =  chan_in[i].flit_chanel;
                                                //can replace destport here and remove lk rout from internal router
                                                if (smart_ctrl[i].smart_en) r2_chan_in[i].flit_wr = 1'b0;
 
 
                                                //send flit_in to straight out port. Replace lk destport in header flit
                                                ss_flit_chanel[SS_PORT] = chan_in[i].flit_chanel;
                                                if(smart_ctrl[i].hdr_flit_req) ss_flit_chanel[SS_PORT].flit[DST_P_MSB : DST_P_LSB] =  smart_ctrl[i].lk_destport;
                                        end
 
                                        always @(*) begin
                                                // mux out flit channel
                                                chan_out[i].flit_chanel = r2_chan_out[i];
                                                chan_out[i].flit_chanel.credit    =  credit_out[i] ;
                                                if(smart_ctrl[SS_PORT].smart_en) begin
                                                        chan_out[i].flit_chanel.flit    =  ss_flit_chanel[i].flit;
                                                        chan_out[i].flit_chanel.flit_wr =  ss_flit_chanel[i].flit_wr;
 
                                                end
                                        end
 
                                        smart_credit_manage #(
                                                        .V             (V             ),
                                                        .B             (B            )
                                                ) smart_credit_manage (
                                                        .credit_in      (r2_chan_out[i].credit     ),
                                                        .smart_credit_in  (smart_ctrl[i].credit_out ),
                                                        .credit_out     ( credit_out[i]   ),
                                                        .reset          (reset         ),
                                                        .clk            (clk           ));
 
 
 
                                end //for
                        end//smart_en
 
 
 
                end else begin :no_smart
                        for (i=0;i
                                assign r2_chan_in[i]   =  chan_in[i].flit_chanel;
                                assign chan_out[i].flit_chanel     =  r2_chan_out[i];
                                assign smart_ctrl[i]={SMART_CTRL_w{1'b0}};
                        end//for
                end
        endgenerate
 
 
//`ifdef VERILATOR
//      logic  nb_router_active [P-1 : 0] /*verilator public_flat_rd*/ ;
//      logic  router_is_ideal /*verilator public_flat_rd*/ ;
//      logic  not_ideal_next,not_ideal;
//      integer ii,jj;
//      always @ (*) begin
//              router_is_ideal = 1'b1;
//              not_ideal_next  = 1'b0;
//              for (ii=0; ii
//                      nb_router_active[ii]= 1'b0;
//                      if (chan_out[ii].flit_chanel.flit_wr) nb_router_active[ii]=1'b1;
//                      if (chan_out[ii].flit_chanel.credit > {V{1'b0}} ) nb_router_active[ii]=1'b1;
//                      if (chan_out[ii].smart_chanel.requests > {SMART_NUM{1'b0}} ) nb_router_active[ii]=1'b1;
//
//                      for (jj=0; jj
//                              //no active request is in any input queues
//                              if(ivc_info[ii][jj].ivc_req)begin
//                                      router_is_ideal=1'b0;
//                                      not_ideal_next=1'b1;
//                              end
//                      end
//                      //no output flit wr
//                      if (r2_chan_out[ii].flit_wr)  router_is_ideal=1'b0;
//              end
//              if (not_ideal) router_is_ideal =1'b0; // delay one clock cycle if the input req exist in last clock cycle bot not on the current one
//      end
//      pronoc_register #(      .W(1)) no_ideal_register (.in(not_ideal_next), .reset (reset),  .clk(clk), .out (not_ideal));
//`endif
 
 
 
endmodule
 
 
 
module router_top_v //to be used as top module in veralator
                import pronoc_pkg::*;
 
        # (
                parameter P = 5     // router port num
                )(
                        current_r_addr,
                        current_r_id,
 
                        chan_in,
                        chan_out,
 
                        router_event,
 
                        clk,
                        reset
 
                );
 
 
 
        input  [RAw-1 : 0] current_r_addr;
        input [31:0] current_r_id;
 
        input   smartflit_chanel_t chan_in [P-1 : 0];
        output  smartflit_chanel_t chan_out [P-1 : 0];
        input   reset,clk;
 
        output router_event_t router_event [P-1 : 0];
 
 
        router_top # (
                        .P(P)
                )
                router
                (
                        .current_r_id(current_r_id),
                        .current_r_addr(current_r_addr),
                        .chan_in (chan_in),
                        .chan_out(chan_out),
                        .router_event(router_event),
                        .clk(clk),
                        .reset(reset)
                );
 
 
endmodule
 
 

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Subversion Repositories an-fpga-implementation-of-low-latency-noc-based-mpsoc

[/] [an-fpga-implementation-of-low-latency-noc-based-mpsoc/] [trunk/] [mpsoc/] [rtl/] [src_noc/] [router_top.sv] - Blame information for rev 54

Line No.	Rev	Author	Line
1	54	alirezamon	`include "pronoc_def.v"
2	48	alirezamon
3
4			`/****************************************************************************`
5			`* router_top.v`
6			`****************************************************************************/`
7
8			`/**`
9			`* Module: router_top`
10			`*`
11			`* add optional bypass links to two stage router.`
12			`*/`
13			`module router_top`
14			`import pronoc_pkg::*;`
15
16			`# (`
17			`parameter P = 5 // router port num`
18			`)(`
19	54	alirezamon	`current_r_id,`
20			`current_r_addr,`
21	48	alirezamon
22			`chan_in,`
23			`chan_out,`
24
25	54	alirezamon	`router_event,`
26
27	48	alirezamon	`clk,`
28	54	alirezamon	`reset`
29	48	alirezamon
30			`);`
31
32
33			`localparam DISABLED =P;`
34
35			`input [RAw-1 : 0] current_r_addr;`
36	54	alirezamon	`input [31 : 0] current_r_id;`
37	48	alirezamon
38
39			`input smartflit_chanel_t chan_in [P-1 : 0];`
40			`output smartflit_chanel_t chan_out [P-1 : 0];`
41
42	54	alirezamon	`output router_event_t router_event [P-1 : 0];`
43
44
45
46	48	alirezamon	`input clk,reset;`
47
48			`genvar i,j;`
49
50
51			`//synthesis translate_off`
52			`//synopsys translate_off`
53			`/* verilator lint_off WIDTH */`
54			`initial begin`
55			`if((SSA_EN=="YES") && (SMART_EN==1'b1) )begin`
56			`$display("ERROR: Only one of the SMART or SAA can be enabled at the same time");`
57			`$finish;`
58			`end`
59			`if((SMART_EN==1'b1) && COMBINATION_TYPE!="COMB_NONSPEC" )begin`
60			`$display("ERROR: SMART only works with non-speculative VSA");`
61			`$finish;`
62			`end`
63			`if((MIN_PCK_SIZE > 1) && (PCK_TYPE == "SINGLE_FLIT")) begin`
64			`$display("ERROR: The minimum packet size must be set as one for single-flit packet type NoC");`
65			`$finish;`
66			`end`
67	54	alirezamon	`if(((SSA_EN=="YES") \|\| (SMART_EN==1'b1) ) && CAST_TYPE!="UNICAST") begin`
68			`$display("ERROR: SMART or SAA do not support muticast/braodcast packets");`
69			`$finish;`
70			`end`
71
72			`end`
73			`/* verilator lint_on WIDTH */`
74	48	alirezamon
75
76
77	54	alirezamon
78
79	48	alirezamon	`logic report_active_ivcs = 0;`
80
81			`generate`
82	54	alirezamon	`for (i=0; i`
83	48	alirezamon	`for (j=0; j`
84	54	alirezamon	`always @ (posedge report_active_ivcs) begin`
85			`if(ivc_info[i][j].ivc_req) $display("%t : The IVC in router[%h] port[%d] VC [%d] is not empty",$time,current_r_addr,i,j);`
86			`end`
87			`end`
88	48	alirezamon	`end`
89			`endgenerate`
90	54	alirezamon
91	48	alirezamon	`//synopsys translate_on`
92			`//synthesis translate_on`
93
94
95
96	54	alirezamon	`generate`
97			`for (i=0; i`
98			`assign router_event[i].flit_wr_i = chan_in[i].flit_chanel.flit_wr;`
99			`assign router_event[i].bypassed_num = chan_in[i].smart_chanel.bypassed_num;`
100			`assign router_event[i].pck_wr_i = chan_in[i].flit_chanel.flit_wr & chan_in[i].flit_chanel.flit.hdr_flag;`
101			`assign router_event[i].flit_wr_o = chan_out[i].flit_chanel.flit_wr;`
102			`assign router_event[i].pck_wr_o = chan_out[i].flit_chanel.flit_wr & chan_out[i].flit_chanel.flit.hdr_flag;`
103			`assign router_event[i].flit_in_bypassed = chan_out[i].smart_chanel.flit_in_bypassed;`
104
105			`end`
106			`endgenerate`
107	48	alirezamon
108
109	54	alirezamon
110
111
112
113	48	alirezamon	`flit_chanel_t r2_chan_in [P-1 : 0];`
114			`flit_chanel_t r2_chan_out [P-1 : 0];`
115
116			`ivc_info_t ivc_info [P-1 : 0][V-1 : 0];`
117			`ovc_info_t ovc_info [P-1 : 0][V-1 : 0];`
118			`iport_info_t iport_info [P-1 : 0];`
119			`oport_info_t oport_info [P-1 : 0];`
120			`smart_chanel_t smart_chanel_new [P-1 : 0];`
121			`smart_chanel_t smart_chanel_in [P-1 : 0];`
122			`smart_chanel_t smart_chanel_out [P-1 : 0];`
123			`smart_ctrl_t smart_ctrl [P-1 : 0];`
124
125
126			`ctrl_chanel_t ctrl_in [P-1 : 0];`
127			`ctrl_chanel_t ctrl_out [P-1 : 0];`
128
129			`generate`
130			`for (i=0; i`
131			`assign ctrl_in [i] = chan_in[i].ctrl_chanel;`
132			`assign chan_out[i].ctrl_chanel= ctrl_out [i];`
133	54	alirezamon
134	48	alirezamon	`end`
135			`endgenerate`
136
137			`// synthesis translate_off`
138
139			`//header flit info, it is useful for debugin`
140			`hdr_flit_t hdr_flit_i [P-1 : 0]; // the received packet header flit info`
141			`hdr_flit_t hdr_flit_o [P-1 : 0]; // the sent packet header flit info`
142
143			`generate`
144			`for (i=0; i`
145
146
147
148			`header_flit_info in_extract(`
149			`.flit(chan_in[i].flit_chanel.flit),`
150			`.hdr_flit( hdr_flit_i[i]),`
151			`.data_o()`
152			`);`
153
154			`header_flit_info out_extract(`
155			`.flit(chan_out[i].flit_chanel.flit),`
156			`.hdr_flit( hdr_flit_o[i]),`
157			`.data_o()`
158			`);`
159
160			`if(DEBUG_EN) begin :dbg`
161			`check_flit_chanel_type_is_in_order #(`
162			`.V(V),`
163			`.PCK_TYPE(PCK_TYPE),`
164			`.MIN_PCK_SIZE(MIN_PCK_SIZE)`
165			`)`
166			`IVC_flit_type_check`
167			`(`
168			`.clk(clk),`
169			`.reset(reset),`
170			`.hdr_flg_in(chan_in[i].flit_chanel.flit.hdr_flag),`
171			`.tail_flg_in(chan_in[i].flit_chanel.flit.tail_flag),`
172			`.flit_in_wr(chan_in[i].flit_chanel.flit_wr),`
173			`.vc_num_in(chan_in[i].flit_chanel.flit.vc)`
174			`);`
175	54	alirezamon
176			`check_pck_size #(`
177			`.V(V),`
178			`.MIN_PCK_SIZE(MIN_PCK_SIZE),`
179			`.Fw(Fw),`
180			`.DAw(DAw),`
181			`.CAST_TYPE(CAST_TYPE),`
182			`.NE(NE),`
183			`.B(B),`
184			`.LB(LB)`
185			`)`
186			`check_pck_siz`
187			`(`
188			`.clk(clk),`
189			`.reset(reset),`
190			`.hdr_flg_in(chan_in[i].flit_chanel.flit.hdr_flag),`
191			`.tail_flg_in(chan_in[i].flit_chanel.flit.tail_flag),`
192			`.flit_in_wr(chan_in[i].flit_chanel.flit_wr),`
193			`.vc_num_in(chan_in[i].flit_chanel.flit.vc),`
194			`.dest_e_addr_in(chan_in[i].flit_chanel.flit.payload[E_DST_MSB : E_DST_LSB])`
195			`);`
196
197	48	alirezamon
198			`end`
199
200
201			`end`
202			`endgenerate`
203			`// synthesis translate_on`
204
205
206
207
208
209			`wire [V-1 : 0] ovc_locally_requested [P-1 : 0];`
210			`flit_chanel_t ss_flit_chanel [P-1 : 0]; //flit bypass link goes to straight port`
211
212			`router_two_stage #(//r2`
213			`.P (P)`
214			`)router_ref (`
215			`.ivc_info (ivc_info),`
216			`.ovc_info (ovc_info),`
217			`.iport_info (iport_info),`
218			`.oport_info (oport_info),`
219			`.smart_ctrl_in (smart_ctrl),`
220			`.current_r_addr(current_r_addr),`
221	54	alirezamon	`.current_r_id(current_r_id),`
222	48	alirezamon	`.chan_in (r2_chan_in),`
223			`.chan_out (r2_chan_out),`
224			`.ctrl_in (ctrl_in),`
225			`.ctrl_out (ctrl_out),`
226			`.clk (clk),`
227			`.reset (reset)`
228			`);`
229
230			`generate`
231
232			`if(SMART_EN) begin :smart`
233
234
235			`smart_forward_ivc_info`
236			`#(`
237			`.P(P)`
238			`)forward_ivc(`
239			`.ivc_info(ivc_info),`
240			`.iport_info(iport_info),`
241			`.oport_info(oport_info),`
242			`.smart_chanel(smart_chanel_new),`
243			`.ovc_locally_requested(ovc_locally_requested),`
244			`.reset(reset),`
245			`.clk(clk)`
246			`);`
247
248			`smart_bypass_chanels`
249			`#(`
250			`.P(P)`
251			`)smart_bypass(`
252			`.ivc_info(ivc_info),`
253			`.iport_info(iport_info),`
254			`.oport_info(oport_info),`
255			`.smart_chanel_new(smart_chanel_new),`
256			`.smart_chanel_in(smart_chanel_in),`
257			`.smart_chanel_out(smart_chanel_out),`
258			`.smart_req( ),`
259			`.reset(reset),`
260			`.clk(clk)`
261			`);`
262
263			`wire [RAw-1: 0] neighbors_r_addr [P-1: 0];`
264			`wire [V-1 : 0] credit_out [P-1 : 0];`
265			`wire [V-1 : 0] ivc_smart_en [P-1 : 0];`
266			`for (i=0;i`
267			`localparam SS_PORT = strieght_port (P,i);`
268			`if(SS_PORT == DISABLED) begin: smart_dis`
269			`assign r2_chan_in[i] = chan_in[i].flit_chanel;`
270			`assign chan_out[i].flit_chanel = r2_chan_out[i];`
271			`assign smart_ctrl[i]={SMART_CTRL_w{1'b0}};`
272			`end`
273			`else begin :smart_en`
274			`assign neighbors_r_addr [i] = chan_in[i].ctrl_chanel.neighbors_r_addr;`
275			`//smart allocator`
276			`smart_allocator_per_iport #(`
277			`.P (P ),`
278			`.SW_LOC (i ),`
279			`.SS_PORT_LOC (SS_PORT )`
280			`) smart_allocator(`
281			`.clk (clk ),`
282			`.reset (reset ),`
283			`.current_r_addr_i (current_r_addr ),`
284			`.neighbors_r_addr_i (neighbors_r_addr ),`
285	54	alirezamon	`.smart_chanel_i (chan_in[i].smart_chanel ),`
286	48	alirezamon	`.flit_chanel_i (chan_in[i].flit_chanel ),`
287			`.ivc_info (ivc_info[i] ),`
288			`.ss_ovc_info (ovc_info[SS_PORT] ),`
289			`.ovc_locally_requested (ovc_locally_requested[SS_PORT] ),`
290			`.ss_smart_chanel_new (smart_chanel_new[SS_PORT]),`
291			`.ss_port_link_reg_flit_wr (r2_chan_out[SS_PORT].flit_wr),`
292
293			`.smart_ivc_single_flit_pck_o (smart_ctrl[i].ivc_single_flit_pck),`
294			`.smart_destport_o (smart_ctrl[i].destport ),`
295			`.smart_lk_destport_o (smart_ctrl[i].lk_destport ),`
296			`.smart_hdr_flit_req_o (smart_ctrl[i].hdr_flit_req ),`
297			`.smart_ivc_smart_en_o (ivc_smart_en[i] ),`
298			`.smart_credit_o (smart_ctrl[i].credit_out ),`
299			`.smart_buff_space_decreased_o (smart_ctrl[SS_PORT].buff_space_decreased),`
300			`.smart_ivc_num_getting_ovc_grant_o(smart_ctrl[i].ivc_num_getting_ovc_grant),`
301			`.smart_ivc_reset_o (smart_ctrl[i].ivc_reset),`
302			`.smart_ivc_granted_ovc_num_o (smart_ctrl[i].ivc_granted_ovc_num),`
303			`.smart_ovc_single_flit_pck_o (smart_ctrl[SS_PORT].ovc_single_flit_pck),`
304			`.smart_ss_ovc_is_allocated_o (smart_ctrl[SS_PORT].ovc_is_allocated),`
305			`.smart_ss_ovc_is_released_o (smart_ctrl[SS_PORT].ovc_is_released),`
306			`.smart_mask_available_ss_ovc_o (smart_ctrl[SS_PORT].mask_available_ovc)`
307
308			`);`
309
310			`assign smart_ctrl[i].ivc_smart_en = ivc_smart_en[i];`
311			`assign smart_ctrl[i].smart_en = \|ivc_smart_en[i];`
312
313
314
315
316			`// synthesis translate_off`
317			`//assign chan_out[i].smart_chanel = (smart_chanel[i].requests[0]) ? smart_chanel_new[i] : take ss shifted smart;`
318			`smart_chanel_check check (`
319			`.flit_chanel(chan_out[i].flit_chanel),`
320			`.smart_chanel(chan_out[i].smart_chanel),`
321			`.reset(reset),`
322			`.clk(clk)`
323			`);`
324			`// synthesis translate_on`
325
326			`assign smart_chanel_in[i] = chan_in[i].smart_chanel;`
327	54	alirezamon
328	48	alirezamon
329			`//r2 demux`
330			`// flit_in_wr demux`
331			`always @(*) begin`
332	54	alirezamon	`chan_out[i].smart_chanel = smart_chanel_out[i];`
333			`chan_out[i].smart_chanel.flit_in_bypassed =smart_ctrl[i].smart_en & chan_in[i].flit_chanel.flit_wr ;`
334
335
336	48	alirezamon	`//mask only flit_wr if smart_en is asserted`
337			`r2_chan_in[i] = chan_in[i].flit_chanel;`
338			`//can replace destport here and remove lk rout from internal router`
339			`if (smart_ctrl[i].smart_en) r2_chan_in[i].flit_wr = 1'b0;`
340	54	alirezamon
341	48	alirezamon
342			`//send flit_in to straight out port. Replace lk destport in header flit`
343			`ss_flit_chanel[SS_PORT] = chan_in[i].flit_chanel;`
344			`if(smart_ctrl[i].hdr_flit_req) ss_flit_chanel[SS_PORT].flit[DST_P_MSB : DST_P_LSB] = smart_ctrl[i].lk_destport;`
345			`end`
346
347			`always @(*) begin`
348			`// mux out flit channel`
349			`chan_out[i].flit_chanel = r2_chan_out[i];`
350			`chan_out[i].flit_chanel.credit = credit_out[i] ;`
351			`if(smart_ctrl[SS_PORT].smart_en) begin`
352			`chan_out[i].flit_chanel.flit = ss_flit_chanel[i].flit;`
353			`chan_out[i].flit_chanel.flit_wr = ss_flit_chanel[i].flit_wr;`
354
355			`end`
356			`end`
357
358			`smart_credit_manage #(`
359			`.V (V ),`
360			`.B (B )`
361			`) smart_credit_manage (`
362			`.credit_in (r2_chan_out[i].credit ),`
363			`.smart_credit_in (smart_ctrl[i].credit_out ),`
364			`.credit_out ( credit_out[i] ),`
365			`.reset (reset ),`
366			`.clk (clk ));`
367
368
369
370			`end //for`
371			`end//smart_en`
372
373
374
375			`end else begin :no_smart`
376			`for (i=0;i`
377			`assign r2_chan_in[i] = chan_in[i].flit_chanel;`
378			`assign chan_out[i].flit_chanel = r2_chan_out[i];`
379			`assign smart_ctrl[i]={SMART_CTRL_w{1'b0}};`
380			`end//for`
381			`end`
382			`endgenerate`
383
384
385			//`ifdef VERILATOR
386			`// logic nb_router_active [P-1 : 0] /verilator public_flat_rd/ ;`
387			`// logic router_is_ideal /verilator public_flat_rd/ ;`
388			`// logic not_ideal_next,not_ideal;`
389			`// integer ii,jj;`
390			`// always @ (*) begin`
391			`// router_is_ideal = 1'b1;`
392			`// not_ideal_next = 1'b0;`
393			`// for (ii=0; ii`
394			`// nb_router_active[ii]= 1'b0;`
395			`// if (chan_out[ii].flit_chanel.flit_wr) nb_router_active[ii]=1'b1;`
396			`// if (chan_out[ii].flit_chanel.credit > {V{1'b0}} ) nb_router_active[ii]=1'b1;`
397			`// if (chan_out[ii].smart_chanel.requests > {SMART_NUM{1'b0}} ) nb_router_active[ii]=1'b1;`
398			`//`
399			`// for (jj=0; jj`
400			`// //no active request is in any input queues`
401			`// if(ivc_info[ii][jj].ivc_req)begin`
402			`// router_is_ideal=1'b0;`
403			`// not_ideal_next=1'b1;`
404			`// end`
405			`// end`
406			`// //no output flit wr`
407			`// if (r2_chan_out[ii].flit_wr) router_is_ideal=1'b0;`
408			`// end`
409			`// if (not_ideal) router_is_ideal =1'b0; // delay one clock cycle if the input req exist in last clock cycle bot not on the current one`
410			`// end`
411	54	alirezamon	`// pronoc_register #( .W(1)) no_ideal_register (.in(not_ideal_next), .reset (reset), .clk(clk), .out (not_ideal));`
412	48	alirezamon	//`endif
413
414
415
416			`endmodule`
417
418
419
420			`module router_top_v //to be used as top module in veralator`
421			`import pronoc_pkg::*;`
422
423			`# (`
424			`parameter P = 5 // router port num`
425			`)(`
426			`current_r_addr,`
427	54	alirezamon	`current_r_id,`
428	48	alirezamon
429			`chan_in,`
430			`chan_out,`
431
432	54	alirezamon	`router_event,`
433
434	48	alirezamon	`clk,`
435			`reset`
436
437			`);`
438
439
440
441			`input [RAw-1 : 0] current_r_addr;`
442	54	alirezamon	`input [31:0] current_r_id;`
443	48	alirezamon
444			`input smartflit_chanel_t chan_in [P-1 : 0];`
445			`output smartflit_chanel_t chan_out [P-1 : 0];`
446	54	alirezamon	`input reset,clk;`
447
448			`output router_event_t router_event [P-1 : 0];`
449
450
451	48	alirezamon	`router_top # (`
452			`.P(P)`
453			`)`
454			`router`
455			`(`
456	54	alirezamon	`.current_r_id(current_r_id),`
457	48	alirezamon	`.current_r_addr(current_r_addr),`
458			`.chan_in (chan_in),`
459	54	alirezamon	`.chan_out(chan_out),`
460			`.router_event(router_event),`
461	48	alirezamon	`.clk(clk),`
462			`.reset(reset)`
463			`);`
464
465
466			`endmodule`
467
468